JP2008258337A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate circuit design, which considers temperature guarantee, by providing a resistance element small in temperature depending property. <P>SOLUTION: A second N-well 3 is formed on the surface of a P-type semiconductor substrate 1 and a P+-type semiconductor layer 8 is formed on the surface of the second N-well 3. An N-type semiconductor layer 13 is formed further on the surface of the P+-type semiconductor layer 8. Further, a first resistance electrode 15, connected electrically to the N-type semiconductor layer 13, is formed through a contact hole CH3 formed in an interlayer insulating film 11 on the N-type semiconductor layer 13. On the other hand, an N+-type semiconductor layer 10 is formed on the front surface of the second N-well 3 and a second resistance electrode 16, connected electrically to the N+-type semiconductor layer 10 through the contact hole CH4 formed in the interlayer insulating film 11 on the N+-type semiconductor layer 10, is formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique for forming a resistor on a semiconductor substrate.

In general, a semiconductor integrated circuit is often formed of a transistor and a resistance element. Therefore, the transistor and the resistor are formed on one semiconductor substrate as circuit components. As a resistance element formed on a semiconductor substrate, a polysilicon resistance, a diffusion resistance, or the like is known. These resistance elements are described in Patent Documents 1 and 2.
JP 2004-221307 A JP 2005-191228 A

  However, since the resistance values of the polysilicon resistance and the well resistance are highly temperature dependent, circuit design may be difficult in consideration of temperature assurance.

  The semiconductor device of the present invention includes a semiconductor substrate, a first conductivity type well formed on the surface of the semiconductor substrate, a second conductivity type first semiconductor layer formed on the surface of the well, and the first A first conductive type second semiconductor layer formed on the surface of the first semiconductor layer, a first electrode electrically connected to the well, and an electrical connection to the second semiconductor layer; And a second electrode.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first conductivity type well on a surface of a semiconductor substrate, and a second conductivity type impurity is ion-implanted into the surface of the well. Forming the first semiconductor layer, forming the insulating film so as to cover the first semiconductor layer, etching the insulating film on the first semiconductor layer to form the first semiconductor layer Forming a first-conductivity-type second semiconductor layer on the surface of the first semiconductor layer by ion-implanting a first-conductivity-type impurity through the contact hole. And forming an electrode that is electrically connected to the second semiconductor layer through the contact hole.

  According to the present invention, it is possible to provide a resistance element having a small temperature dependency. This facilitates circuit design taking temperature guarantee into consideration.

  Next, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  First, as shown in FIG. 1, a first N well 2 and a second N well 3 are formed on the surface of a P-type semiconductor substrate 1 (silicon substrate) so as to be separated from each other. Further, an element isolation film 4 is formed on the surface of the P-type semiconductor substrate 1. The element isolation film 4 is formed so as to surround the element formation region, and can be formed by, for example, a selective oxidation method (LOCOS). Thereafter, a gate insulating film 5 is formed in the element formation region.

Next, as shown in FIG. 2, a gate electrode 6A is formed on the gate insulating film 5 in the P-channel MOS transistor formation region 20, and a gate electrode 6B is formed on the gate insulating film 5 in the N-channel MOS transistor formation region 30. Form. Thereafter, P + type source layer 7S and P + type drain layer 7D are formed by implanting ions of P type impurities such as boron into the surface of first N well 2 on both sides of gate electrode 6A. Then, the P + type semiconductor layer 8 is formed on the surface of the second N well 3 in the resistance forming region 40. The boron ion implantation conditions at this time are an acceleration energy of 50 KeV and a dose of 2.0 × 10 ¹⁵ / cm ² .

Also, N + type source layer 9S and N + type drain layer 9D are formed by ion-implanting N-type impurities such as arsenic into the surface of P-type semiconductor substrate 1 on both sides of gate electrode 6B. An N + type semiconductor layer 10 is formed adjacent to the P + type semiconductor layer 8 on the surface of the second N well 3 in the resistance forming region 40. The arsenic ion implantation conditions at this time are an acceleration energy of 70 KeV and a dose of 5.0 × 10 ¹⁵ / cm ² .

  The P + type semiconductor layer 8 and the N + type semiconductor layer 10 are separated with the element isolation film 4 interposed therebetween. Thereafter, an interlayer insulating film 11 such as BPSG is formed on the entire surface of the P-type semiconductor substrate 1 by a CVD method.

Next, as shown in FIG. 3, the interlayer insulating film 11 and the gate insulating film 5 are selectively etched to form contact holes CH1 to CH6. These contact holes CH1 to CH6 are respectively provided with interlayer insulation over the P + type source layer 7S, P + type drain layer 7D, P + type semiconductor layer 8, N + type semiconductor layer 10, N + type source layer 9S, and N + type drain layer 9D. Formed on the film 11. Then, through the contact holes CH1 to CH6, boron difluoride (BF ₂ +) is converted into a P + type source layer 7S, a P + type drain layer 7D, a P + type semiconductor layer 8, an N + type semiconductor layer 10, an N + type source layer 9S, respectively. Implanted into the surface of the N + type drain layer 9D. The ion implantation at this time is a whole surface implantation without a photoresist, and the conditions are an acceleration energy of 50 KeV and a dose of 2 × 10 ¹⁵ / cm ² .

  By this ion implantation, the P-type impurity concentration on the surface corresponding to the contact holes CH1, CH2, and CH3 of the P + type source layer 7S, the P + type drain layer 7D, and the P + type semiconductor layer 8 is increased, and is formed in a later process. Contact resistance with the electrode is reduced. On the other hand, the surfaces corresponding to the contact holes CH3, CH4, and CH5 of the N + type semiconductor layer 10, the N + type source layer 9S, and the N + type drain layer 9D are made P-type.

Next, as shown in FIG. 4, a photoresist 12 is formed to cover the contact holes CH1 and CH2 in the P-channel MOS transistor formation region 20, and the contact holes CH3, CH4, CH5, and CH6 are formed using the photoresist 12 as a mask. Then, phosphorus (P +) is ion-implanted into the surfaces of the P + type semiconductor layer 8, the N + type semiconductor layer 10, the N + type source layer 9S, and the N + type drain layer 9D, respectively. The ion implantation conditions at this time are an acceleration energy of 25 KeV and a dose of 3 × 10 ¹⁴ / cm ² .

  By this ion implantation, the P-type surfaces of the N + -type semiconductor layer 10, the N + -type source layer 9S, and the N + -type drain layer 9D are changed to N-type by compensation, and contact resistance with electrodes formed in later steps Is reduced. On the other hand, since phosphorus (P +) is injected into the surface of the P + type semiconductor layer 8 through the contact hole CH <b> 3, the N type semiconductor layer 13 is formed on the surface of the P + type semiconductor layer 8.

  Next, as shown in FIG. 5, after removing the photoresist 12, a metal layer is formed by sputtering a metal such as aluminum on the interlayer insulating film 11 including in the contact holes CH <b> 1 to CH <b> 6. By selectively etching the metal layer so as to remain in the contact holes CH1 to CH6, the source electrode 14S and the P + type drain layer 7D electrically connected to the P + type source layer 7S of the P channel type MOS transistor are electrically connected. Connected drain electrode 14D, first resistance electrode 15 electrically connected to N-type semiconductor layer 13, second resistance electrode 16 electrically connected to N + type semiconductor layer 10, N-channel type A source electrode 17S electrically connected to the N + type source layer 9S of the MOS transistor and a drain electrode 17D electrically connected to the N + type drain layer 9D are formed.

  As described above, on the P-type semiconductor substrate 1, the P-channel MOS transistor, the N-channel MOS transistor, and the resistance element (between the first resistance electrode 15 and the second resistance electrode 16 in the resistance formation region 40) (Resistive element) is formed.

  Next, the measurement result of the characteristic of the resistance element will be described with reference to FIG. FIG. 6A is a diagram illustrating current characteristics of the resistance element, and the horizontal axis indicates the voltage VD applied between the first resistance electrode 15 and the second resistance electrode 16. With reference to the second resistance electrode 16, a positive voltage is set when the first resistance electrode 15 is at a high potential, and a negative voltage is set when the first resistance electrode 15 is at a low potential. The vertical axis indicates the current ID flowing through the resistance element.

  As is apparent from this measurement diagram, the current characteristic of the resistance element is a curve that approximates the forward characteristic of the PN junction when a positive voltage is applied to the resistance element. This is considered to be due to the contribution of the PN junction characteristic formed by the P + type semiconductor layer 8 and the second N well 3. On the other hand, the current characteristic of the resistance element when a negative voltage is applied to the resistance element is different from a normal PN junction, and a current ID substantially proportional to the applied voltage is obtained. Therefore, this resistance element exhibits resistance characteristics when a negative voltage is applied. The current at this time is considered to be a kind of leakage current that flows from the second N well 3 to the N type semiconductor layer 13 through the P + type semiconductor layer 8.

  FIG. 6B is a diagram showing the temperature dependence of the current (leakage current) flowing through the resistance element. The voltage applied to the resistance element is −5V. The current value is −0.02 A at room temperature (about 25 ° C.), and it can be seen that the change is very small even when the temperature rises. The current value at 120 ° C. is −0.019 A. When converted into a resistance value R, R = 250Ω at room temperature (about 25 ° C.) and R = 263Ω at 120 ° C., and the current change from room temperature (about 25 ° C.) to 120 ° C. is only about 5%.

  For comparison, FIG. 7 shows the measurement results of the PN junction characteristics. This is a measurement result when there is no N-type semiconductor layer 13 on the surface of the P + -type semiconductor layer 8. The current characteristics in FIG. 7A indicate normal PN junction characteristics. That is, when the PN junction is biased in the forward direction, the current ID rises sharply at the threshold value, and when it is biased in the reverse direction, only a small leak current flows. FIG. 7B shows the temperature dependence of current (leakage current) when a negative voltage is applied. From this it can be seen that the temperature change of the current is very large.

  As described above, by forming the N-type semiconductor layer 13 on the surface of the P + -type semiconductor layer 8, a resistance element having extremely low temperature dependence can be obtained. In addition, this resistance element can be formed using the CMOS process as described above without any additional process. In addition, since this resistance element is formed using the contact formation region of the P + type semiconductor layer 8, there is an advantage that the pattern area can be reduced.

  Needless to say, the present invention is not limited to the above-described embodiment and can be changed without departing from the scope of the invention. For example, the N-type semiconductor layer 13 on the surface of the P + type semiconductor layer 8 is formed by ion implantation through the contact hole CH3 formed in the interlayer insulating film 11, but before the formation of the interlayer insulating film 11, a dedicated layer is formed. It can also be formed by ion implantation. Moreover, the ion implantation conditions in the said embodiment are illustrations, Comprising: It can change in order to set resistance value and its temperature dependence appropriately.

  Furthermore, although an example of a single-layer wiring structure has been described in the above embodiment, the present invention can also be applied to a multilayer wiring structure. For example, another interlayer insulating film is formed on the interlayer insulating film 11 so as to cover the first resistance electrode 15 and the second resistance electrode 16, and the first resistance electrode 15 and the second resistance electrode are formed on the other interlayer insulating film. Via holes corresponding to the respective resistance electrodes 16 can be respectively formed, and the upper layer electrode or the upper layer wiring electrically connected to the first resistance electrode 15 and the second resistance electrode 16 can be formed through the via holes. . These upper-layer electrodes or upper-layer wirings are electrically connected to the N-type semiconductor layer 13 and the N + -type semiconductor layer 10 (second well N3) of the resistance element, respectively.

It is sectional drawing which shows the manufacturing method of the semiconductor device by embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device by embodiment of this invention. It is a figure which shows the measurement result of the characteristic of the resistive element by embodiment of this invention. It is a figure which shows the measurement result of a PN junction characteristic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 P type semiconductor substrate 2 1st N well 3 2nd N well 4 Element isolation film 5 Gate insulating film 6A, 6B Gate electrode 7SP P + type source layer 7D P + type drain layer 8P + type semiconductor layer 9S N + type source layer 9D N + type drain layer 10 N + type semiconductor layer 11 Interlayer insulating film 12 Photo resist 13 N type semiconductor layer 14S Source electrode 14D Drain electrode 15 First resistance electrode
16 Second resistance electrode 17S Source electrode 17D Drain electrodes CH1 to CH6 Contact hole

Claims (2)

A semiconductor substrate, a first conductivity type well formed on the surface of the semiconductor substrate, a second conductivity type first semiconductor layer formed on the surface of the well, and a surface of the first semiconductor layer A first semiconductor layer of the first conductivity type formed; a first electrode electrically connected to the well; and a second electrode electrically connected to the second semiconductor layer. A semiconductor device. Forming a first conductivity type well on the surface of the semiconductor substrate;
Forming a second conductive type first semiconductor layer by ion-implanting a second conductive type impurity into the surface of the well;
Forming an insulating film covering the first semiconductor layer;
Etching the insulating film on the first semiconductor layer to form a contact hole that partially exposes the first semiconductor layer;
Forming a second semiconductor layer of the first conductivity type on the surface of the first semiconductor layer by ion-implanting a first conductivity type impurity through the contact hole;
And a step of forming an electrode electrically connected to the second semiconductor layer through the contact hole.

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