JP2006135351A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a high resistor element on the same substrate, without giving adverse effects on the characteristics of a transistor element in an LDD structure. <P>SOLUTION: An n-well region 3, a device separation oxide film 5, a gate oxide film 7, a polycide gate electrode 9, and lightly-doped diffusion regions 17, 21 are formed on a silicon substrate 1. A CVD oxide film is then formed over the entire surface of the silicon substrate 1. Furthermore, a high resistor element pattern 25, which introduces BF<SB>2</SB>as impurity for resistance value control, is formed thereon, etching-back of the CVD oxide film is performed to form a sidewall spacer 15a and a CVD oxide film pattern 15b, and low-resistance regions 29 are formed on both terminal sides of the high resistor element pattern 25 to form a resistor region 27. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor device, and in particular, includes a transistor element having an LDD (Lightly Doped Drain) structure having a sidewall spacer on a side wall of a gate electrode and a polysilicon film, and impurities for controlling a resistance value are introduced. The present invention relates to a semiconductor device including a high-resistance element having a resistor region and a low-resistance region into which impurities are introduced at a higher concentration than the resistor region.
Such a semiconductor device is applied to a semiconductor device including an analog circuit, for example.

  In a highly integrated SRAM (Static Random Access Memory) and an LSI (Large Scale Integration) equipped with an analog circuit, a resistor element having a relatively high resistance value using a polysilicon film as a resistor is used. Is the mainstream. These resistor elements are usually formed using a polysilicon film formed in the same process as the polysilicon film used for the gate electrode of the transistor element.

  In recent years, in order to cope with further higher integration and improvement in circuit operation speed, the gate electrode of the transistor element is changed from a single polysilicon film layer to a refractory metal or refractory metal silicide film and a polysilicon film. There is a need to change the gate electrode to a so-called polycide gate electrode and to reduce the resistance of the gate electrode.

  However, when a high-resistance element having the same laminated structure as a low-resistance gate electrode such as a polycide gate electrode is formed, the area of the resistor element increases to obtain a necessary resistance value, and the circuit area cannot be reduced. Occurs. For this reason, it becomes difficult to form the gate electrode of the transistor element and the high resistance element from the polysilicon film formed in the same process, and there is a method of forming the gate electrode of the transistor element and the high resistance element from different polysilicon films. It is done.

  12 and 13 show a general method for forming a semiconductor device including a transistor element having an LDD (Lightly Doped Drain) structure and a polycide gate electrode and a high resistance element. The LDD structure is a technique for improving the reliability of transistor elements. Here, a case where an N-channel MOS transistor element (an N-channel gate insulating field effect transistor, hereinafter referred to as an Nch transistor element) is formed on a P-type silicon substrate will be described.

(1) An element isolation oxide film 5 is formed on a P-type silicon substrate (semiconductor substrate) 1 using a known technique. A gate oxide film 7 is formed on the surface of the active region of the silicon substrate 1 surrounded by the element isolation oxide film 5. The lower layer is a low resistance polysilicon film 11 and the upper layer is a refractory metal silicide film 13 on the gate oxide film 7. A polycide gate electrode 9 having a laminated structure is formed. Ion implantation is performed to form an N-type low concentration diffusion region 17 in a self-aligned manner with respect to the gate electrode 9. Sidewall spacers 73 are formed on the side walls of the gate electrode 9. Ion implantation is performed to form an N-type high-concentration diffusion region 19 in a self-aligned manner with respect to the sidewall spacer 73, thereby forming an Nch transistor element (see FIG. 12A).

(2) A thermal CVD oxide film 75 serving as an insulating film between the high-resistance element and the Nch transistor element is formed on the entire surface of the silicon substrate 1 by thermal CVD (chemical vapor deposition) (FIG. 12B). )reference).

(3) A polysilicon film for forming a high-resistance element is formed on the thermal CVD oxide film 75, and phosphorus implantation for controlling the resistance value of the high-resistance element is performed on the entire surface of the polysilicon film. A polysilicon film 77 is formed (see FIG. 12C).

(4) A resist mask pattern 79 is formed on the high-resistance polysilicon film 77 so as to cover a region that becomes a resistor region of the high-resistance element. In order to form a low resistance region of the high resistance element for stabilizing the connection between the high resistance element and the metal wiring, ion implantation is performed using the resist mask pattern 79 as a mask to form a low resistance polysilicon film 81. It is formed (see FIG. 13D).

(5) After removing the resist mask pattern 79, a resist mask pattern 83 for defining a high-resistance element forming region is formed on the high-resistance polysilicon film 77 and the low-resistance polysilicon film 81. The high resistance polysilicon film 77 and the low resistance polysilicon film 81 are selectively removed by the etching technique using the resist mask pattern 83 as a mask to form a high resistance element pattern 85 constituting a high resistance element. . In the high resistance element pattern 85, a resistor region 87 is formed from the high resistance polysilicon film 77, and a low resistance region 89 is formed from the low resistance polysilicon film 81 (see FIG. 13E).

(6) When the resist mask pattern 83 is removed, the formation of the high-resistance element pattern 85 is completed (see FIG. 13F). Thereafter, a wiring formation step, a passivation film formation step, and the like are performed to complete the semiconductor device.

  In the prior art, as described in the step (2), after forming the transistor element, a polysilicon film for the high resistance element and a CVD oxide film 75 for insulating the transistor element are formed by a thermal CVD method. (See FIG. 12B).

  For example, the formation of a CVD oxide film by a thermal CVD method such as a low pressure CVD method generally requires a heat treatment at around 800 ° C., and the characteristics of the transistor element change due to the influence of this heat treatment. For this reason, the characteristics of transistor elements cannot be matched with high accuracy between a semiconductor device having a high-resistance element and a semiconductor device not having a high-resistance element. There is a problem in that the load at the time of design increases because it is necessary to distinguish between these during circuit design.

  Further, in order to form a high resistance element, one implantation mask for defining a formation region of a low resistance region for stabilizing the contact resistance between the high resistance element and the metal wiring (step (4) and 13D), one mask for defining the formation region of the high resistance element (see step (5) and FIG. 13E), a total of two mask steps (photoengraving step). There is a problem that it is necessary in addition and increases the manufacturing cost and the manufacturing period.

In order to solve such problems, conventionally, the following methods have been proposed.
For example, in order to form the polysilicon film of the polycide gate electrode and the high-resistance element from the polysilicon film formed in the same process, the high-resistance element is formed before forming the refractory metal film on the polysilicon film. There is a method of forming an insulating film pattern on a polysilicon film in a region (see, for example, Patent Documents 1 and 2).

  In this method, after forming a polysilicon film, an insulating film pattern made of a silicon oxide film or a silicon nitride film is formed only in a region that becomes a resistor region of a high-resistance element, and a refractory metal on the insulating film pattern is formed. By removing, a high resistance element having a low resistance region on both ends of the resistor region and a low resistance gate electrode of the MOS transistor element are formed at the same time.

  However, since it is necessary to align the insulating film pattern on the high-resistance element and the mask pattern for defining the formation region of the low-resistance region, the interval between the high-resistance elements is reduced to reduce the circuit area. There was a problem that it was difficult to do.

  Furthermore, since the resistor region is etched using the insulating film pattern as a mask during patterning of the high resistance element, it is difficult to form a sidewall protective film that stabilizes the pattern size, and the polysilicon film size varies. There was a problem that became larger.

  Furthermore, since the etching rates of the polysilicon film in the low resistance region and the resistor region are greatly different, if the etching time in the low resistance region is optimized, the etching in the resistor region is insufficient, and the etching time in the resistor region is optimized. Etching of the low resistance region becomes excessive, and there is a problem that it is difficult to finish the dimensions of both regions to the optimum size.

  Furthermore, since the impurity to be injected for controlling the resistance value of the high resistance element is also injected into the gate electrode of the transistor element, it is necessary to select an injection type and an injection condition in consideration of the characteristics of the transistor element. There is a problem that optimization of the high resistance element becomes difficult. For example, when the implantation energy is high, the implanted impurity penetrates into the channel region of the transistor element, resulting in a problem that the characteristics of the transistor element fluctuate. In addition, in order to avoid this, there is a method of forming a resist pattern that covers the formation region of the transistor element at the time of impurity implantation for resistance control of the high resistance element, but this adversely affects the manufacturing cost and the construction period. Result.

As another method, there is a method of removing only the refractory metal on the high-resistance element (see, for example, Patent Document 3).
This method forms a high-resistance element and a polysilicon film for power supply wiring, forms a refractory metal layer on the polysilicon film, and then forms only the refractory metal layer on the resistor region of the high-resistance element. Are removed by etching, and a high-resistance element and a low-resistance element are formed simultaneously. However, it is very difficult to remove only the refractory metal layer on the polysilicon film with a high selectivity, and the specific method is not described.
JP-A-5-275620 JP 7-147403 A JP-A-5-183130

  An object of the present invention is to provide a semiconductor device capable of forming a high-resistance element on the same substrate without adversely affecting the characteristics of transistor elements having an LDD structure.

The semiconductor device according to the present invention takes an LDD transistor element having a side wall spacer on the side wall of a gate electrode, a resistor region and a potential of a resistor region into which an impurity for resistance value control is introduced. Therefore, the semiconductor device includes a high resistance element having a low resistance region in which impurities are introduced at a higher concentration than the resistor region, and the resistance region of the high resistance element is used for resistance value control. BF ₂ is introduced as an impurity, and the high-resistance element is formed on a silicon oxide film pattern formed simultaneously with the silicon oxide film constituting the sidewall spacer.

A method of manufacturing a semiconductor device according to the present invention includes a transistor element having an LDD structure having a sidewall spacer on a side wall of a gate electrode and a polysilicon film, and BF ₂ is introduced as an impurity for resistance control. A method for manufacturing a semiconductor device including a resistor region and a high-resistance element having a low-resistance region into which impurities are introduced at a higher concentration than the resistor region, and includes the following steps (A) to (E): Including.
(A) forming an element isolation oxide film on a semiconductor substrate, sequentially forming a gate oxide film and a gate electrode on the active region, and forming a low concentration diffusion region of an LDD structure in the active region;
(B) forming a silicon oxide film for forming the sidewall spacer on the entire surface of the semiconductor substrate;
(C) forming a high-resistance element pattern made of a high-resistance polysilicon film into which BF ₂ is introduced as an impurity for controlling the resistance value on the silicon oxide film in the formation region of the high-resistance element;
(D) etching back the silicon oxide film to form a sidewall spacer on the side wall of the gate electrode, leaving a silicon oxide film pattern under the high-resistance element pattern;
(E) A step of introducing an impurity into a predetermined region of the high resistance element pattern to form the resistor region and the low resistance region.

In the semiconductor device of the present invention, BF ₂ is introduced as an impurity for controlling the resistance value in the resistor region of the high-resistance element, so that, as will be described in detail later, compared to the case where phosphorus or arsenic is used. The lowest temperature coefficient of resistance is obtained with the same sheet resistance.
In the semiconductor device of the present invention, the high resistance element is formed on the silicon oxide film pattern formed simultaneously with the silicon oxide film constituting the sidewall spacer. Therefore, unlike the prior art, it is not necessary to additionally form a polysilicon film for a high resistance element and an insulating film for insulating the transistor element, and 800 ° C. when the insulating film is formed by the CVD method. Do not perform heat treatment before and after. As a result, the high resistance element can be formed on the same substrate without adversely affecting the characteristics of the transistor element having the LDD structure, and the load during circuit design can be greatly reduced.

  Furthermore, unlike the prior art, it is not necessary to additionally form a polysilicon film for a high-resistance element and an insulating film for insulating the transistor element, so that the manufacturing cost and the construction period can be shortened. it can.

  In the case of forming a polysilicon film for forming a high resistance element by the CVD method, a heat treatment is performed. Usually, the polysilicon film can be formed at a temperature of 500 to 650 ° C. Since this heat treatment does not affect the characteristics of the transistor element, there is no problem.

2. The semiconductor device according to claim 1, wherein the resistor region of the high-resistance element is an impurity for controlling a resistance value in the semiconductor device including an LDD transistor element and a high-resistance element made of a polysilicon film. As BF ₂ is introduced, a small resistance temperature coefficient can be obtained.
Further, since the high resistance element is formed on the silicon oxide film pattern formed at the same time as the silicon oxide film constituting the side wall spacer, the poly resistor for the high resistance element is formed as in the prior art. No heat treatment is performed when an additional insulating film is formed to insulate the silicon film from the transistor element, so that a high resistance element is formed on the same substrate without adversely affecting the characteristics of the transistor element of the LDD structure. can do. Thereby, it is possible to reduce the load at the time of circuit design, reduce the manufacturing cost, and shorten the construction period.

In the semiconductor device according to claim 2, since the introduction amount of BF ₂ is adjusted so that the sheet resistance of the resistor region of the high-resistance element is about 500 to 1000Ω / □, the resistance temperature A high-resistance element having a coefficient of almost zero can be obtained, and a high-accuracy circuit with very little characteristic variation due to temperature can be formed.
In the semiconductor device according to the third aspect, the gate electrode has a laminated structure in which the lower layer is made of a polysilicon film and the upper layer is made of a refractory metal film or a refractory metal silicide film. Can be achieved. Here, since the high-resistance element and the gate electrode are formed of a polysilicon film formed in separate processes, a refractory metal film or a refractory metal silicide film is formed on the polysilicon film in the gate electrode. However, the high melting point metal film or the high melting point metal silicide film is not formed on the high resistance element, and only the gate electrode can be reduced in resistance.

  According to another aspect of the semiconductor device of the present invention, a dividing resistor for dividing the voltage to be detected and supplying the divided voltage, a reference voltage source for supplying a reference voltage, a divided voltage from the dividing resistor, and the above Since the analog circuit including the comparison circuit for comparing the reference voltage from the reference voltage source is provided, and the resistance circuit constituting the dividing resistor is provided with the high resistance element constituting the semiconductor device of the present invention. The high resistance element can be formed on the same substrate without adversely affecting the characteristics of the transistor element having the LDD structure, and the load at the time of circuit design can be greatly reduced.

In the semiconductor device of the present invention, the gate electrode preferably has a laminated structure in which the lower layer is a polysilicon film and the upper layer is a refractory metal film or a refractory metal silicide film.
In the semiconductor device of the present invention, since the high-resistance element and the gate electrode are formed of the polysilicon film formed in separate processes, the refractory metal film or the refractory metal is formed on the polysilicon film in the gate electrode. Even if the silicide film is formed, the refractory metal film or the refractory metal silicide film is not formed on the high resistance element, and the resistance of only the gate electrode can be reduced.

  As an example of an analog circuit to which a high resistance element constituting a semiconductor device of the present invention is applied, a divided resistor for dividing a voltage to be detected and supplying a divided voltage, and a reference voltage for supplying a reference voltage And a source having a comparison circuit for comparing the divided voltage from the dividing resistor and the reference voltage from the reference voltage source. In the analog circuit, by using a resistor circuit comprising the high-resistance element constituting the semiconductor device of the present invention as the resistance circuit constituting the divided resistor, the high-resistance element constituting the present invention is an LDD transistor. Since a high-resistance element can be formed on the same substrate without adversely affecting the characteristics of the element, the load during circuit design can be greatly reduced.

[Example]
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device.
An N well region 3 is formed in a P-type silicon substrate (semiconductor substrate) 1. An element isolation oxide film 5 is formed on the surface of the silicon substrate 1. The active region A of the silicon substrate 1 surrounded by the element isolation oxide film 5 is a region where an Nch transistor element is formed, and the active region B of the N well region 3 is a P channel type MOS transistor element (hereinafter referred to as a Pch transistor element). This is a region where the

  Polycide gate electrodes 9 are formed on the silicon substrate 1 in the active region A and on the N well region 3 in the active region B through a gate oxide film 7, respectively. The polycide gate electrode 9 has a laminated structure in which the lower layer is a low resistance polysilicon film 11 and the upper layer is, for example, a tungsten silicide film 13. Sidewall spacers 15 a made of a silicon oxide film are formed on the side walls of the gate electrode 9.

  In this embodiment, a tungsten silicide film is used as the refractory metal silicide film for reducing the resistance of the gate electrode. However, the present invention is not limited to this, and the refractory metal silicide film is made of other materials. Or a refractory metal. Further, the gate electrode may be a polysilicon gate electrode that does not include a refractory metal or a refractory metal silicide film.

  Two N-type low concentration diffusion regions 17 are formed on the surface side of the silicon substrate 1 in the active region A with the channel region under the gate electrode 9 interposed therebetween. Two N-type high-concentration diffusion regions 19 having an impurity concentration higher than that of the N-type low-concentration diffusion region 17 are formed with a gap between the channel region and the gate electrode 9.

  Two P-type low concentration diffusion regions 21 are formed on the surface side of the N well region 3 in the active region B with the channel region under the gate electrode 9 interposed therebetween. Two P-type high-concentration diffusion regions 23 having an impurity concentration higher than that of the P-type low-concentration diffusion region 21 are formed with a gap between the channel region and the gate electrode 9.

  A high resistance element pattern 25 made of a polysilicon film is formed on the element isolation oxide film 5 through a CVD oxide film pattern 15b formed simultaneously with a CVD oxide film (silicon oxide film) constituting the sidewall spacer 15a. Has been. The high resistance element pattern 25 constitutes a high resistance element. The high resistor element pattern 25 has a resistor region 27 into which impurities for resistance value control are introduced at the center side, and a potential at which impurities are introduced at a higher concentration than the impurities introduced into the resistor region 27. A low resistance region 29 is provided on both end sides.

  An interlayer insulating film 31 made of, for example, a silicon oxide film is formed on the entire surface of the silicon substrate 1 including the element isolation oxide film 5, the gate electrode 9, the sidewall spacers 15a, and the high resistance element pattern 25. Connection holes are formed in the interlayer insulating film 31 on the gate electrode 9, the N-type high concentration diffusion region 19, the P-type high concentration diffusion region 23, and the low resistance region 29. Metal wirings 33 are formed in the connection holes and on the interlayer insulating film 31.

2 to 4 are process cross-sectional views illustrating an example of a method of manufacturing a semiconductor device according to the embodiment. This manufacturing method will be described with reference to FIGS.
(1) An N well region 3 and an element isolation oxide film 5 are formed on a P-type silicon substrate 1 using a known technique. The active region A surrounded by the element isolation oxide film 5 is a region where an Nch transistor element is formed, and the active region B is a region where a Pch transistor element is formed (see FIG. 2A).

(2) A gate oxide film 7 is formed on the surface of the silicon substrate 1 in the active region A and the surface of the N well region 3 in the active region B. For example, after a polysilicon film is formed to a thickness of 1500 Å (angstrom) by low pressure CVD, impurities are introduced into the polysilicon film to form a low resistance polysilicon film 35. For example, a tungsten silicide film 37 is formed to a thickness of 1500 mm on the low-resistance polysilicon film 35 by sputtering or CVD (see FIG. 2B). Although not described here, a process such as ion implantation for controlling the threshold value of the transistor element may be performed before the step of forming the polysilicon film 35.

(3) A resist mask pattern 39 for defining a region for forming a gate electrode of a transistor element is formed on the tungsten silicide film 37 by photolithography. By the dry etching technique, the tungsten silicide film 37 and the low resistance polysilicon film 35 are selectively removed using the resist mask pattern 39 as a mask. A gate electrode 9 having a stacked structure is formed (see FIG. 2C).

(4) After removing the resist mask pattern 39, a low concentration diffusion region for forming an LDD structure, which is a well-known technique for improving the reliability of transistor elements, using photolithography and ion implantation The active region A and the active region B are individually implanted to form an N-type low-concentration diffusion region 17 in a self-aligned manner with respect to the gate electrode 9 on the silicon substrate 1 in the active region A, and N in the active region B A P-type low concentration diffusion region 21 is formed in the well region 3 (see FIG. 2D).

(5) A CVD oxide film 41 for forming side wall spacers necessary for forming the LDD structure is formed to a thickness of, for example, 1500 mm by CVD (see FIG. 2E).

(6) A polysilicon film for forming a high-resistance element is formed on the CVD oxide film 41 by, for example, a low pressure CVD method, for example, to a thickness of 1200 mm. By ion implantation, an impurity for controlling the resistance value of the high-resistance element, such as arsenic, is implanted into the polysilicon film under the conditions of an acceleration voltage of 30 KeV and an implantation amount of 2.0 × 10 ¹⁵ / cm ^2. A resistive polysilicon film 43 is formed (see FIG. 3F). Here, heat treatment is performed when forming the polysilicon film for forming the high-resistance element by the low pressure CVD method. Since the heat treatment can be performed at a temperature of 500 to 650 ° C., for example, the characteristics of the transistor element A polysilicon film can be formed without affecting the above.

  At the time of ion implantation in the step (6), the active regions A and B, which are transistor element formation regions, are covered with the thick CVD oxide film 41 and the high-resistance polysilicon film 43. Is less than 200 KeV), the implanted impurity hardly reaches the channel region of the transistor element near the surface of the silicon substrate 1 or the low-concentration diffusion regions 17, 21, so that the impurity is implanted into the high-resistance polysilicon film 43. The implantation conditions such as the acceleration voltage and the implantation amount can be freely set.

Further, since a polysilicon film formed separately from the low-resistance polysilicon film 35 for the gate electrode 9 is used as the polysilicon film for the high-resistance element, impurities to be implanted into the polysilicon film for the high-resistance element As a result, the transistor element is not affected at all even if an impurity such as BF ₂ that adversely affects the polysilicon film for the gate electrode is selected.

(7) A resist mask pattern 45 for defining a high-resistance element forming region is formed on the high-resistance polysilicon film 43 by photolithography (see FIG. 3G).
(8) The high resistance polysilicon film 43 is selectively removed using the resist mask pattern 45 as a mask by a dry etching technique to form the high resistance element pattern 25 (see FIG. 3H). The impurity concentration of the high-resistance polysilicon film 43 to be etched at this time is uniform, and the etching rate difference due to the difference in impurity concentration as described in the prior art does not occur, and the etching time is optimized with high accuracy. can do. Furthermore, since the underlying CVD oxide film 41 has a sufficiently thick film thickness, overetching necessary for removing the residue of the polysilicon film that tends to remain at the position corresponding to the side wall portion of the gate electrode 9 of the transistor element. There is no problem at all.

(9) With the resist mask pattern 45 left without being removed, the CVD oxide film 41 is etched back by a dry etching technique to form a sidewall spacer 15a on the sidewall of the gate electrode 9. At this time, the CVD oxide film 41 under the high resistance element pattern 25 remains without being removed. The CVD oxide film remaining under the high resistance element pattern 25 is defined as a CVD oxide film pattern 15b (see FIG. 3I).

  When the CVD oxide film 41 is etched back, the surface of the high-resistance element pattern 25 made of a high-resistance polysilicon film is protected by the resist mask pattern 45, so that the high-resistance element pattern 25 is etched and damaged. Can be prevented. However, even if the CVD oxide film 41 is etched back after the resist mask pattern 45 is removed, the etching rate of the polysilicon film at the time of etching back for the silicon oxide film is usually kept low, so that the high resistance A body element can be formed.

(10) After removing the resist mask pattern 45, a resist mask that covers the region that becomes the resistor region of the high-resistance element pattern 25 and covers the active region B that is the formation region of the Pch transistor element by photolithography. A pattern 47 is formed. By ion implantation, for example, arsenic is applied to the region that becomes the low resistance region of the high resistance element pattern 25 and the active region A of the silicon substrate 1 using the gate electrode 9, the sidewall spacer 15a, and the resist mask pattern 47 as a mask. The acceleration voltage is 50 KeV and the injection amount is 4.0 × 10 ¹⁵ / cm ² (see FIG. 4J).

  Thus, ion implantation for forming a low resistance region for stabilizing the contact resistance between the high resistance element and the metal wiring and ion implantation for forming a high concentration diffusion region of the Nch transistor device are simultaneously performed. Can do. Therefore, the additional number of mask patterns necessary for forming the high-resistance element is only one mask pattern for defining the formation region of the high-resistance element pattern 25 used in the step (7) (FIG. 3 (G)), increase in manufacturing cost and construction period can be minimized.

(11) The resist mask pattern 47 is removed. By the ion implantation in the step (10), the low resistance region 29 is formed in the high resistance element pattern 25, and the N type high concentration diffusion region 19 is formed in the active region A in a self-aligned manner with respect to the sidewall spacer 15a. 9 is formed with an interval. In the high resistance element pattern 25, a region sandwiched between the low resistance regions 29 becomes a resistor region 27 (see FIG. 4K).
Here, heat treatment for activating the impurities implanted into the N-type high concentration diffusion region 19 and the low resistance region 29 may be performed using a diffusion furnace or a lamp annealing apparatus.

(12) A resist mask pattern 49 is formed by photolithography so as to cover the high-resistance element pattern 25 and the active region A that is the formation region of the Nch transistor element. By ion implantation, the gate electrode 9, the side wall spacers 15a and the resist mask pattern 49 are used as a mask. For example, BF ₂ is accelerated into the active region B of the N well region 3 at an acceleration voltage of 30 KeV and the implantation amount is 2.0 × 10. Injection is performed under the condition of ¹⁵ / cm ² (see FIG. 4L).

(13) The resist mask pattern 49 is removed. By the ion implantation performed in the step (12), the P-type high concentration diffusion region 23 is formed in the active region B in a self-aligned manner with respect to the side wall spacer 15a (see FIG. 4M). reference).
Here, a heat treatment for activating the impurities implanted in the P-type high concentration diffusion region 23 may be performed using a diffusion furnace or a lamp annealing apparatus. When heat treatment for activating the impurities implanted into the N-type high concentration diffusion region 19 and the low resistance region 29 is not performed, the N type high concentration diffusion region 19, the P type high concentration diffusion region 23, and the low resistance region A heat treatment for activating the impurities implanted into the electrode 29 may be performed simultaneously.

  In this example of the manufacturing method, since arsenic is used as an impurity for controlling the resistance of the high resistance element, ion implantation for forming the low resistance region 29 is performed to form the N-type high concentration diffusion region 19. Although it is performed simultaneously with the ion implantation, the present invention is not limited to this. When a P-type impurity is used as an impurity for controlling the resistance of the high-resistance element, a P-type high concentration diffusion region is used. Simultaneously with the ion implantation for forming 23, ion implantation for forming the low resistance region of the high resistance element may be performed.

(14) An interlayer insulating film 31 is formed on the entire surface of the silicon substrate 1 by a normal wiring formation technique. The gate electrode 9, the N-type high concentration diffusion region 19, the P-type high concentration diffusion region 23, and the low resistance are formed. A connection hole is formed in the interlayer insulating film 31 on the region 29, and a metal wiring 33 is formed in the connection hole and on the interlayer insulating film 31 (see FIG. 1). Thereafter, the manufacturing of the semiconductor device is completed through a normal passivation film forming process and the like.

  In this embodiment, the high-resistance element pattern 25 constituting the high-resistance element is formed on the CVD oxide film pattern 15b made of the CVD oxide film formed to form the sidewall spacer 15a. Unlike the technology, it is not necessary to additionally form a polysilicon film for a high-resistance element and an insulating film for insulating the transistor element, and heat treatment at around 800 ° C. when the insulating film is formed by the CVD method. There is no need to do. As a result, transistor elements and high-resistance elements having an LDD structure can be formed without adversely affecting the characteristics of the transistor elements formed on the same silicon substrate 1, and the load during circuit design is greatly reduced. be able to. Furthermore, unlike the prior art, it is not necessary to additionally form a polysilicon film for a high-resistance element and an insulating film for insulating the transistor element, so that the manufacturing cost and the construction period can be shortened. it can.

FIG. 5 shows data comparing the characteristics (pair property) of the high resistance element when the polysilicon film thickness is 1200 mm (solid line) and when it is 3500 mm (broken line). In a sample having a polysilicon film thickness of 1200 mm, impurity implantation for resistance control was performed using arsenic as an implantation species, an acceleration voltage of 30 KeV, and an implantation amount of 2.1 × 10 ¹⁵ / cm ² . In a sample having a polysilicon film thickness of 3500 mm, impurity implantation for resistance control was performed using phosphorus as an implantation species, an acceleration voltage of 30 KeV, and an implantation amount of 1.2 × 10 ¹⁵ / cm ² . In both cases, the sheet resistance is about 2.0 KΩ / □. The vertical axis of the graph shows a characteristic called pair property, which is important as a characteristic of the high resistance element, and shows a percentage (%) obtained by dividing the difference between the resistance values of adjacent high resistance elements by the resistance value. The horizontal axis of the graph represents the resistor width (μm (micrometer)).

  In general, when the resistor width becomes narrower, the pair property tends to deteriorate (increase), but the polysilicon film thickness does not affect the tendency. However, the absolute value of the sample having a polysilicon film thickness of 1200 mm is about half that of the sample of 3500 mm, which is a lower value in all resistor widths. From this, it is understood that the pair property of the high resistance element can be greatly improved by reducing the thickness of the polysilicon film constituting the high resistance element in the present invention.

  FIG. 6 shows data comparing the characteristics of the high-resistance element (relation between resistance temperature coefficient and resistance value) when the polysilicon film thickness is 1200 mm (solid line) and 3500 mm (dashed line). The manufacturing conditions of the high resistance element are the same as those of the sample used in FIG. The vertical axis of the graph represents the temperature coefficient of resistance (ppm / ° C.), and the horizontal axis represents the sheet resistance (Ω / □).

  In general, it is known that the temperature coefficient of resistance depends on the sheet resistance value. Even in this characteristic, by reducing the thickness of the polysilicon film constituting the high resistance element in the present invention, it becomes possible to obtain a resistance temperature coefficient having a smaller absolute value with the same resistance value, and a more accurate analog A circuit can be formed.

Further, since the polysilicon film for the high-resistance element is formed on the CVD oxide film for forming the sidewall spacer of the LDD structure transistor element, the CVD oxide film and the polysilicon film are formed when the polysilicon film thickness is 2000 mm or more. As a result, the total step in the step becomes larger than the step in the gate electrode of the transistor element, and the focus margin in the photolithography process in the wiring forming process is reduced. Further, with the increase in the total level difference, it becomes difficult to planarize the interlayer insulating film in the wiring formation process, which may cause a short circuit or disconnection between the wirings. Therefore, the thickness of the polysilicon film for the high resistance element is preferably suppressed to 2000 mm or less.
On the other hand, when the polysilicon film thickness for the high-resistance element is set to 500 mm or less, the connection hole penetrates the polysilicon film when the connection hole (contact hole) with the metal wiring is opened, and normal connection is not achieved. It becomes difficult.
Therefore, in the present invention, the thickness of the polysilicon film for the high resistance element is preferably set between 500 and 2000 mm.

FIG. 7 shows data comparing the characteristics (pair property) of the high-resistance element when the implantation type for controlling the resistance value is phosphorus (broken line) and arsenic (solid line). In the sample in which the implantation type was phosphorus, phosphorus implantation for resistance control was performed under the conditions of an acceleration voltage of 30 KeV and an implantation amount of 1.3 × 10 ¹⁵ / cm ² . In the case where the implantation type is arsenic, arsenic implantation for resistance control was performed under the conditions of an acceleration voltage of 30 KeV and an implantation amount of 2.1 × 10 ¹⁵ / cm ² . In both cases, the polysilicon film thickness is 1200 mm, and the sheet resistance value is about 2.0 KΩ / □. The vertical axis of the graph indicates pairing (%), and the horizontal axis indicates the resistor width (μm).

  In any resistor width, the pairing property of the sample using arsenic as the implantation species is suppressed by 20 to 30% lower than that of the sample using phosphorus. When the high resistance element of the present invention is applied to a circuit that desires a lower pairing property, a circuit with higher accuracy can be formed by using arsenic as an implantation seed.

  FIG. 8 shows data comparing the characteristics of the high-resistance element (relation between the temperature coefficient of resistance and the width of the resistor) when the implantation type for controlling the resistance value is phosphorus (broken line) and when arsenic is used (solid line). is there. The manufacturing conditions of the high resistance element are the same as those of the sample used in FIG. The vertical axis of the graph represents the temperature coefficient of resistance (ppm / ° C.), and the horizontal axis represents the resistor width (μm).

  In any resistor width, the absolute value of the resistance temperature coefficient is suppressed smaller in the sample implanted with phosphorus as the implanted species than in the sample implanted with arsenic. Therefore, when the high-resistance element is applied to a circuit that desires a lower resistance temperature coefficient, a circuit with higher accuracy can be formed by using phosphorus rather than arsenic as an implantation seed.

FIG. 9 shows the characteristics of the high-resistance element (the relationship between the resistance temperature coefficient and the resistance value) when the implantation type for controlling the resistance value is BF ₂ (solid line), phosphorus (dashed line), and arsenic ( It is the data which compared the dashed-dotted line. In the case where the implantation type is BF ₂ , BF ₂ implantation for resistance control was performed under the conditions of an acceleration voltage of 30 KeV and an implantation amount of 5.0 × 10 ^{13 to} 3.0 × 10 ¹⁵ / cm ² . In the sample in which the implantation type was phosphorus, phosphorus implantation for resistance control was performed under the conditions of an acceleration voltage of 30 KeV and an implantation amount of 3.0 × 10 ^{14 to} 1.3 × 10 ¹⁵ / cm ² . In the case where the implantation type was arsenic, arsenic implantation for resistance control was performed under the conditions of an acceleration voltage of 30 KeV and an implantation amount of 5.0 × 10 ^{14 to} 3.0 × 10 ¹⁵ / cm ² . In both cases, the polysilicon film thickness is 1500 mm.

It can be seen that when BF ₂ is used as the implantation seed, the resistance temperature coefficient having the smallest absolute value can be obtained with the same sheet resistance as compared with the case where phosphorus or arsenic is used. In particular, by using BF ₂ as an injection type and adjusting the injection amount of BF ₂ so as to obtain a sheet resistance of about 500 to 1000Ω / □, a high resistance element having a resistance temperature coefficient of almost 0 is formed. Therefore, it is possible to form a high-accuracy circuit with very little characteristic variation due to temperature.

  As described above, according to the semiconductor device of the present invention, since a polysilicon film different from the polysilicon film for the gate electrode is used as the polysilicon film for the high resistance element, the desired characteristics of the high resistance element are obtained. Accordingly, the implantation type and implantation conditions of the resistance control impurities of the high resistance element can be freely selected, and therefore optimization according to the purpose can be performed.

FIG. 10 is a circuit diagram showing an embodiment of a semiconductor device provided with a constant voltage generation circuit which is an analog circuit.
A constant voltage generation circuit 55 is provided in order to stably supply power from the DC power supply 51 to the load 53. The constant voltage generation circuit 55 includes an input terminal (Vbat) 57 to which the DC power supply 51 is connected, a reference voltage generation circuit (Vref) 59 as a reference voltage source, an operational amplifier 61, and a P-channel MOS transistor that constitutes an output driver ( Hereinafter, it is provided with 63, abbreviated as PMOS, division resistors R1 and R2, and an output terminal (Vout) 65.

  In the constant voltage generating circuit 55, the output terminal of the operational amplifier 61 is connected to the gate electrode of the PMOS 63, the reference voltage Vref is applied from the reference voltage generating circuit 59 to the inverting input terminal, and the output voltage Vout is divided to the non-inverting input terminal. A voltage divided by R1 and R2 is applied, and the divided voltage from the divided resistors R1 and R2 is controlled to be equal to the reference voltage Vref.

  In the constant voltage generation circuit 55, the high resistance element constituting the present invention is used as the high resistance element constituting the dividing resistors R1 and R2. According to the high-resistance element constituting the present invention, the high-resistance element can be formed on the same substrate without adversely affecting the characteristics of the transistor element having the LDD structure. Can be reduced.

FIG. 11 is a circuit diagram showing an embodiment of a semiconductor device provided with a voltage detection circuit which is an analog circuit.
In the voltage detection circuit 67, 61 is an operational amplifier, the reference voltage generation circuit 59 is connected to the inverting input terminal, and the reference voltage Vref is applied. The voltage of the terminal to be measured input from the input terminal (Vsens) 69 is divided by the dividing resistors R1 and R2 and input to the non-inverting input terminal of the operational amplifier 61. The output of the operational amplifier 61 is output to the outside through an output terminal (Vout) 71.

  In the voltage detection circuit 67, when the voltage of the terminal to be measured is high and the voltage divided by the dividing resistors R1 and R2 is higher than the reference voltage Vref, the output of the operational amplifier 61 maintains H, and the voltage of the terminal to be measured When the voltage drops and the voltage divided by the dividing resistors R1 and R2 becomes equal to or lower than the reference voltage Vref, the output of the operational amplifier 61 becomes L.

  In the voltage detection circuit 67, the high resistance element constituting the present invention is used as the high resistance element constituting the dividing resistors R1 and R2. According to the high-resistance element constituting the present invention, the high-resistance element can be formed on the same substrate without adversely affecting the characteristics of the transistor element having the LDD structure. Can be reduced.

  10 and 11, the semiconductor device of the present invention is applied to a semiconductor device including a constant voltage generation circuit or a voltage detection circuit, but the semiconductor device to which the semiconductor device of the present invention is applied is limited to these. Any semiconductor device including a high-resistance element can be applied.

  As mentioned above, although the Example of this invention was described, this invention is not limited to this, A various change is possible within the range of this invention described in the claim.

It is sectional drawing which shows one Example of a semiconductor device. It is process sectional drawing which shows a part of example of a manufacturing method. FIG. 3 is a process sectional view showing a part of the manufacturing method and showing a continuation of FIG. 2. FIG. 4 is a process sectional view showing a part of the manufacturing method and showing a continuation of FIG. 3. Regarding the characteristics (pair property) of the high resistance element, the data is a comparison between a case where the polysilicon film thickness is 1200 mm and a case where the film thickness is 3500 mm. Regarding the characteristics of the high resistance element (relationship between the temperature coefficient of resistance and the resistance value), the data is a comparison between a case where the polysilicon film thickness is 1200 mm and a case where the film thickness is 3500 mm. This is data comparing the characteristics of the high resistance element (pair property) when the implantation type for controlling the resistance value is phosphorus and arsenic. The characteristics of the high-resistance element (relationship between the temperature coefficient of resistance and the width of the resistor) are data comparing the case where the implantation type for controlling the resistance value is phosphorus and the case of arsenic. Regarding the characteristics of the high-resistance element (relation between the temperature coefficient of resistance and the resistance value), the data is a comparison between the case where the implantation type for controlling the resistance value is BF ₂ , the case of phosphorus, and the case of arsenic. 1 is a circuit diagram showing an embodiment of a semiconductor device including a constant voltage generation circuit which is an analog circuit. It is a circuit diagram which shows one Example of the semiconductor device provided with the voltage detection circuit which is an analog circuit. It is process sectional drawing which shows the manufacturing method of the conventional semiconductor device. FIG. 15 is a process cross-sectional view illustrating the continuation of FIG. 14.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 N well region 5 Element isolation oxide film 7 Gate oxide film 9 Gate electrode 11 Low resistance polysilicon film 13 Tungsten silicide film 15a Side wall spacer 15b Silicon oxide film 17 N type low concentration diffusion region 19 N type high concentration diffusion Region 21 P type low concentration diffusion region 23 P type high concentration diffusion region 25 high resistance element pattern 27 resistor region 29 low resistance region 31 interlayer insulating film 33 metal wiring 35 low resistance polysilicon film 37 tungsten silicide film 39, 45, 47, 49 Resist mask pattern 41 Polysilicon film 43 High resistance polysilicon film

Claims (4)

A transistor element having an LDD structure having a sidewall spacer on the side wall of the gate electrode, a polysilicon film, and a resistor region into which impurities for resistance value control are introduced, and a higher region than the resistor region for taking a potential. In a semiconductor device including a high resistance element having a low resistance region in which impurities are introduced in the concentration,
In the resistor region of the high resistance element, BF ₂ is introduced as an impurity for controlling the resistance value, and
The semiconductor device according to claim 1, wherein the high resistance element is formed on a silicon oxide film pattern formed simultaneously with the silicon oxide film constituting the sidewall spacer. _2. The semiconductor device according to claim 1, wherein the amount of BF ₂ introduced is adjusted so that the resistor region of the high-resistance element has a sheet resistance of about 500 to 1000 Ω / □.   3. The semiconductor device according to claim 1, wherein the gate electrode has a laminated structure in which a lower layer is a polysilicon film and an upper layer is a refractory metal film or a refractory metal silicide film. A dividing resistor for dividing a voltage to be detected and supplying a divided voltage, a reference voltage source for supplying a reference voltage, a divided voltage from the dividing resistor and a reference voltage from the reference voltage source are compared. 4. A semiconductor device comprising: an analog circuit comprising a comparison circuit for providing a resistance circuit comprising the high-resistance element according to claim 1;

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