JP2010016059A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To more strongly prevent the entry of hydrogen than with a method for arranging metals on a group of resistors, in order to suppress that a change in resistance value during the entry of hydrogen into a resistor, to shorten overlapping of metallic sections and to miniaturize ICs. <P>SOLUTION: A silicon nitride protective film is deposited in a manner to cover a polycrystal silicon formed of a heavily-doped impurity area and a lightly-doped impurity area, and an interlayer dielectric is then deposited on the silicon nitride protective film. The interlayer dielectric and the silicon nitride protective film are etched to make a contact hole, which is used to connect a plurality of resistors made of polycrystal silicon by metal wiring. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a polycrystalline silicon resistor.

  Examples of the resistor used in the semiconductor integrated circuit include a diffused resistor in which an impurity having a conductivity type opposite to that of the semiconductor substrate is implanted into a single crystal silicon semiconductor substrate, and a polycrystalline silicon resistor in which an impurity is implanted into polycrystalline silicon. Polycrystalline silicon resistors are widely used in semiconductor devices because they have advantages such as low leakage current because they are surrounded by an insulating film, and high resistance values due to defects present at the grain boundaries. Has been.

  FIG. 2 is a schematic cross-sectional view of a conventional polycrystalline silicon resistor.

Impurities are introduced into the polycrystalline silicon thin film deposited on the field oxide film 202 formed on the silicon semiconductor substrate 201 to provide a low concentration impurity region 203 at the center and high concentration impurity regions 204 at both ends. A resistor is made by using the shape of In order to accurately control the resistivity of the low concentration impurity region, a method of introducing impurities by an ion implantation method is generally used. The impurity concentration is set according to the target resistivity and is in the range of 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ . Impurities such as boron are generally implanted when a P-type resistor is required, and impurities such as arsenic and phosphorus are generally implanted when an N-type resistor is required.

The high-concentration impurity region 204 is a region having a low resistance, and is connected to the metal wiring 207 through a contact 206 formed in the interlayer insulating film 205 so as to extract the potential. between a crystal silicon and the metal wire, the polycrystalline silicon in order to obtain a good ohmic contact are implanted at a high concentration of impurities such as a 1 × 10 ²⁰ / cm ³ or more.

  When various potentials are extracted from the resistor circuit, each resistor group is selected based on a unit resistor, and a resistor group having various configurations is selected by connecting the resistors in series or in parallel. And in order to stabilize resistance value for every resistance group, a metal is formed on a resistance group and this metal is connected to the terminal of one end with a resistance group in many cases.

  The first reason is to obtain the stability of the potential of the polycrystalline silicon resistor. Since polycrystalline silicon is a semiconductor, when a wiring or electrode is formed on it, the inside of the polycrystalline silicon is depleted or accumulated due to the relative relationship between the potential of the wiring or electrode and the potential of the polycrystalline silicon resistance. The resistance value changes depending on the situation. Specifically, in a polycrystalline silicon implanted with a P-type impurity, if a wiring or an electrode having a higher potential than the polycrystalline silicon resistance exists immediately above the polycrystalline silicon, the P-type polycrystalline silicon is depleted. The value becomes higher. In the case of the reverse potential relationship, the resistance value is low because of the accumulation state.

  In order to avoid such resistance value fluctuations, the same resistance value can always be maintained by intentionally forming a wiring close to the potential of the polycrystalline silicon on the polycrystalline silicon. In the cross-sectional view of FIG. 2, such an example is shown, and the potential is fixed by extending the electrode on one side of the polycrystalline silicon resistor so as to cover the resistor.

  Such a phenomenon naturally depends not only on the upper wiring of the polycrystalline silicon but also on the lower state. That is, the resistance value varies depending on the relative relationship between the polycrystalline silicon resistance and the potential of the semiconductor substrate under the polycrystalline silicon resistance. Although not shown, a measure is known in which a diffusion region or the like is intentionally formed under polycrystalline silicon resistance as in the case of the previous metal wiring to stabilize the potential.

  The second reason is to prevent diffusion of hydrogen into the polycrystalline silicon which affects the polycrystalline silicon resistance value in the semiconductor process.

  Polycrystalline silicon is composed of grains having relatively high crystallinity and grain boundaries between grains having low crystallinity, that is, having a high level density. The resistance value of the polycrystalline silicon resistor is almost determined by trapping electrons or holes as carriers at levels existing at many grain boundaries. However, when hydrogen having a high diffusion coefficient is generated in the semiconductor manufacturing process, this hydrogen easily reaches the polycrystalline silicon, and is trapped at a level to change the resistance value.

Examples of such a hydrogen generation process include a sintering process using a hydrogen atmosphere after forming a metal electrode and a plasma nitride film forming process using ammonia gas. By covering the metal wiring on the polycrystalline silicon resistor, it is possible to suppress the variation in the resistance value of the polycrystalline silicon due to such hydrogen diffusion. A method of stably providing such a polycrystalline silicon resistance value is disclosed in Patent Document 1.
Japanese Patent Application Laid-Open No. 2002-076281

  However, as described above, even if a metal is arranged on the resistor group, there are cases where hydrogen cannot be prevented from entering the polycrystalline silicon. For example, when forming a resistor group, several resistors having the same size are arranged side by side and a metal is arranged thereon. In this case, the resistor at the end of the resistor group and the resistor in the resistor group are arranged. There is a phenomenon in which the degree of influence of hydrogen is different. The resistor located at the end is more susceptible to hydrogen, the resistance values at both ends of the resistor group fluctuate, and the relative accuracy of the resistor group deteriorates.

  As a method for solving these problems, there is a method in which the metal layout has a sufficient length from both ends of the resistor group, but this leads to an increase in the area occupied by the resistor group, which is disadvantageous in the miniaturization of the IC. . Under the present circumstances, there is a case where a layout in which resistors that are not used at both ends are increased is taken.

  The present invention proposes a method for reducing the influence of hydrogen without sufficient metal overlap on the upper part of the resistance group.

  In order to solve the above problems, the present invention takes the following forms.

  A field oxide film is formed on a semiconductor substrate, a resistor made of a polycrystalline silicon film is formed on the field oxide film, and a protective film made of a nitride film for preventing intrusion of hydrogen is formed on the resistor. Further, an interlayer insulating film is formed on the interlayer insulating film, a contact connecting the resistor and the metal is formed on the interlayer insulating film, and a metal serving as an electrode is formed on the interlayer insulating film. A manufacturing method of a semiconductor device forming a group.

  According to the manufacturing method of the present invention, the resistor of the semiconductor device according to the present invention can firmly prevent hydrogen intrusion into the resistor due to a process that may cause hydrogen intrusion after forming the resistor. As a result, each resistor in the resistor group can be made with high precision, and the product yield in an IC using them can be improved and stabilized.

  In addition, the metal overlap on the resistor, which has been performed so far, does not have to be taken sufficiently, and the area occupied by the resistor group can be reduced. Furthermore, the mask pattern and layout are not changed by the manufacturing method of the present invention, and as a result, there is no cost increase associated with manufacturing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a semiconductor device manufactured using the method for manufacturing a semiconductor device according to the present invention. Such a method of manufacturing a semiconductor device includes a resistor forming step of forming a resistor on a part of the surface of the field oxide film 102 provided on the semiconductor substrate 101, and a step of forming a metal wiring thereon. Have. Before these steps, a field oxide film forming step and a gate electrode forming step in a transistor are generally included, but in the present embodiment, these will be omitted. 1 will be sequentially described in the following description.

  Hereinafter, the resistor forming process will be described with reference to the schematic cross-sectional views in order of the processes shown in FIGS. This resistor is formed on the field oxide film. In the following description, it is assumed that the semiconductor substrate is N-type and a PMOS transistor and a P-type resistor are formed. Actually, a P-type substrate may be used. Although the well is not formed in the following description, the well may be formed according to the type of transistor to be formed and the process to be used.

In this resistor forming step, first, a polycrystalline silicon film 104 having a thickness of, for example, 500 to 3000 mm is formed over substantially the entire surface of the N-type semiconductor substrate 101 by CVD or sputtering. Then, an impurity such as Boron or BF _{2 is} ion-implanted over the entire surface of the polycrystalline silicon film 104 at a dose of about 1 × 10 ¹⁴ atoms / cm ² , and the entire polycrystalline silicon film 104 is made to be a low-concentration P-type. To do. Prior to the deposition of the polycrystalline silicon film 104, the gate electrode 103 of the PMOS transistor has already been formed (FIG. 3).

Instead of Boron or BF _{2 as an} impurity, phosphorus or arsenic may be ion-implanted to form an N-type resistor. Alternatively, patterning may be performed using a photoresist, and boron or BF ₂ and phosphorus or arsenic may be implanted only at specific locations to form both P-type and N-type resistance films. In the present embodiment, a P-type resistance film is taken as an example and will be described below.

  Photoresist 115 is applied and patterning of a desired shape is performed. Then, an unnecessary portion of the polycrystalline silicon film 104 is removed by, for example, anisotropic dry etching to form the resistor 105 (FIG. 4).

Next, although not shown in particular, in order to make an N-type low-concentration impurity region in the NMOS transistor, the photoresist is patterned, and arsenic is ion-implanted at a desired location to be 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 6. An impurity region of about ¹⁸ atoms / cm ³ is formed. Similarly, in order to obtain a P-type low-concentration impurity region 108 in the PMOS transistor, the photoresist is patterned, and Boron or BF ₂ is ion-implanted at a desired location, and 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁸ atoms. An impurity region of / cm ³ is formed (FIG. 5).

Next, after removing the photoresist, the photoresist is patterned except for the portions where the source and drain of the NMOS transistor are formed, and arsenic is ion-implanted at a dose of 5 × 10 ¹⁵ atoms / cm ² to form an N-type high concentration impurity. By forming the region, the source and drain of the NMOS transistor are obtained.

Next, after removing the photoresist, the photoresist is patterned except for the portions where the source and drain of the PMOS transistor are formed, and BF ₂ is ion-implanted at a dose of 5 × 10 ¹⁵ atoms / cm ² to form a P-type high concentration impurity. By forming the region, the source and drain of the PMOS transistor are obtained.

  When the resistor is made of N-type polycrystalline silicon so that the conductor wiring made of aluminum alloy is connected well, it is made of P-type polycrystalline silicon when forming the N + high-concentration impurity region In the case where the p-type high concentration impurity region 107 is formed, the high concentration impurity region is formed in each resistor.

  In this embodiment, a resistor is formed of P-type polycrystalline silicon. At the same time as forming the P-type high concentration impurity region 109 in the PMOS transistor, the P-type high concentration impurity region 107 in the resistor is also formed. In addition to the above-described high resistance, a low resistance can also be formed by performing ion implantation on the entire desired resistor simultaneously with the formation of the respective high-concentration impurity regions.

Next, a protective film 110 that prevents intrusion of hydrogen is formed on the entire surface of the semiconductor substrate. A silicon nitride film is used as the protective film and is deposited by a low pressure CVD method (LPCVD) or the like. A film formed by low pressure CVD is preferable compared to plasma CVD because the film is dense and contains less hydrogen. (Fig. 6)
Thereafter, an interlayer insulating film 111 is formed. In general, a TEOS film, a BPSG film, or the like is used for the interlayer insulating film 111. Thereafter, a contact hole 112 is formed. For this purpose, the protective film 110 formed of the silicon nitride film and the interlayer insulating film 111 are etched with the same mask pattern using a photoresist 115 (FIG. 7).

  Thereafter, the MOS semiconductor device shown in FIG. 1 is formed by forming the metal wiring 113, the passivation 114, and the like in the same manner as the manufacturing process of the conventional semiconductor device.

  By adopting the semiconductor device manufacturing method as described above, hydrogen can be firmly prevented from entering the resistor.

It is a typical sectional view of a semiconductor device showing an embodiment of the present invention. It is typical sectional drawing of the semiconductor device which has the conventional polycrystalline silicon resistance. It is a schematic cross section which shows the semiconductor device concerning embodiment of this invention in process order. FIG. 4 is a schematic cross-sectional view in order of the steps of the semiconductor device showing the embodiment of the present invention, following FIG. 3; FIG. 5 is a schematic cross-sectional view in order of the steps of the semiconductor device showing the embodiment of the present invention, following FIG. 4. FIG. 6 is a schematic cross-sectional view in order of the steps of the semiconductor device showing the embodiment of the present invention, following FIG. 5; FIG. 7 is a schematic cross-sectional view in order of the steps of the semiconductor device showing the embodiment of the present invention following FIG. 6;

Explanation of symbols

101 silicon semiconductor N-type substrate 102 field oxide film 103 gate electrode 104 polycrystalline silicon film 105 P-type resistor 106 P-type resistor: low-concentration impurity region 107 P-type resistor: high-concentration impurity region 108 P-type low-concentration impurity region 109 P-type high-concentration impurity region 110 Protective film 111 for preventing hydrogen from entering interlayer insulating film 112 contact 113 metal wiring 114 passivation 115 photoresist film

Claims (5)

Forming a field oxide film on a semiconductor substrate;
Depositing polycrystalline silicon to form a resistor on the field oxide film;
Forming a high concentration impurity region in the polycrystalline silicon;
Forming a low concentration impurity region in the polycrystalline silicon;
Depositing a protective film for preventing intrusion of hydrogen on the surface of the semiconductor substrate having polycrystalline silicon composed of the high concentration impurity region and the low concentration impurity region;
Depositing an interlayer insulating film on the protective film;
Etching the interlayer insulating film and the protective film to form a contact hole;
Connecting a plurality of resistors made of the polycrystalline silicon through the contact holes with a metal wiring;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the protective film is a silicon nitride film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon nitride film is formed by a low pressure CVD method. _{2. The} method of manufacturing a semiconductor device according to claim 1, wherein when the low-concentration impurity region and the high-concentration impurity are P-type, Boron or BF2 is ion-implanted.   2. The method of manufacturing a semiconductor device according to claim 1, wherein when the low concentration impurity region and the high concentration impurity are N-type, phosphorus or arsenic is ion-implanted.

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