JP2009070871A - Nonvolatile semiconductor storage device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable nonvolatile semiconductor storage device by preventing variation in Vt caused by UV light generated in the manufacturing process of a semiconductor storage device, and to provide a manufacturing method thereof. <P>SOLUTION: In a nonvolatile semiconductor storage device consisting of a nonvolatile memory having a gate insulating trap film, an interlayer insulating film 108 is formed on a memory cell and then a first opening 120 reaching a bit line 103, and a second opening 121 reaching a dummy word line 105 contiguous to the first opening 120 are formed simultaneously in the interlayer insulating film 108. Subsequently, a shading layer 110 is formed in the second opening 121 and on the interlayer insulating film 108, and a bit line contact plug 112 is formed in the first opening 120. The shading layer 110 formed on the interlayer insulating film 108 is formed to cover at least the memory cell. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device including a nonvolatile memory having a trapping gate insulating film, and a manufacturing method thereof.

  As an electrically writable nonvolatile memory, a memory structure is known in which a wiring layer composed of a diffusion layer has a structure (virtual grounding system) that also serves as a source / drain of a memory transistor.

  In recent years, there has been a demand for ultra-miniaturization, high integration, high performance, and high reliability of semiconductor devices. In particular, it is important to have high reliability in a fine nonvolatile memory.

  FIG. 11 is a diagram showing a general configuration of a memory cell 200 having a trapping gate insulating film. The memory cell 200 includes a bit line 202 made of a diffusion layer formed on a semiconductor substrate 201, a bit line oxide film 210, a trapping gate insulating film 203, and a word line 204.

  The memory cell 200 is driven by the following method. First, writing is performed by injecting electrons into the gate insulating film 203. The injected electrons are trapped in the gate insulating film 203, thereby increasing the threshold voltage Vt. Here, hot electrons generated near the bit line 202 are used as the injected electrons. Erase is performed by injecting holes into the gate insulating film 203. The injected holes neutralize the electrons trapped in the gate insulating film 203, thereby lowering Vt. Here, as the injected holes, a BTBT current (Band To Band Tunneling current) generated in the vicinity of the bit line 202 is used.

  By the way, after the memory cell 200 is formed, a manufacturing process for forming a wiring for driving the memory cell 200 is performed. The wiring is formed using a plasma etching method, and UV light is generated in the plasma etching process. Then, when this UV light enters the semiconductor substrate on which the memory cell or the like is formed, excited electrons may be generated there.

  In recent years, there has been a problem that the excitation electrons generated by the UV light enter the gate insulating film 203 to reduce the reliability of the memory cell 200. That is, as described above, writing to the memory cell 200 is performed by injecting electrons into the gate insulating film 203, but if excited electrons generated by UV light are injected into the gate insulating film 203, Since extra electrons are injected, the preset Vt rises. Further, even when predetermined holes are injected into the gate insulating film 203 during erasing, electrons trapped in the gate insulating film 203 cannot be completely neutralized, and as a result, the voltage drops to a preset Vt. Can not do it.

  In particular, neutralization of electrons trapped in the gate insulating film 203 is performed by injecting holes into the gate insulating film 203 using a BTBT current generated in the vicinity of the bit line 202. If trapped near the center of the gate insulating film 203, neutralization of such unnecessary electrons becomes difficult. Incidentally, in the case of a floating gate, even if unnecessary electrons are injected into the floating gate, it can be easily erased by irradiating with UV light.

  For the above reasons, when excited electrons generated by UV light enter the gate insulating film 203, it becomes extremely difficult to adjust Vt by writing and erasing the memory cell 200. As a result, the reliability of the memory cell 200 is improved. Cause a decline.

  In order to cope with this problem, a method is known in which a light-shielding film for preventing intrusion of UV light generated in the wiring manufacturing process is previously formed above the memory cell 200.

  FIG. 12 is a cross-sectional view showing a configuration of a semiconductor memory device in which a light shielding film is formed on a memory cell, and shows a configuration in the vicinity of the bit line contact plug 209.

  As shown in FIG. 12, an interlayer insulating film 206 is formed on the memory cell 200, and a light shielding film 205 is formed on the interlayer insulating film 206 and in a region located above the memory cell 200. The light shielding film 205 prevents the UV light generated in the manufacturing process of the wiring (not shown) formed on the interlayer insulating film 206 from entering the vicinity of the memory cell 200. It is possible to prevent unnecessary excitation electrons from being injected into the insulating film 203.

  The semiconductor memory device shown in FIG. 12 can be formed using the manufacturing method shown in FIGS.

  First, as shown in FIG. 13A, a bit line 202 made of a diffusion layer, a bit line oxide film 210, a trapping gate insulating film (not shown), and a word line 204 are provided on a semiconductor substrate 201. The memory cell 200 is formed by a normal method.

  Next, as shown in FIG. 13B, after an interlayer insulating film 206 and a light-shielding film 205 are deposited on the memory cell 200, the photomask 213 is used as shown in FIG. The light shielding film 205 other than the region located above the cell 200 is removed.

  Finally, as shown in FIG. 13D, after the insulating film 207 is deposited on the light shielding film 205, a contact hole reaching the bit line 202 is formed in the insulating film 207 and the interlayer insulating film 206. A bit line contact plug 209 is formed by embedding a wiring material in.

  By the way, since the light shielding film 205 uses a conductive film such as an amorphous silicon film or a tungsten film, the light shielding film 205 is formed away from the bit line contact plug 209 in order to avoid short circuit between the bit line contact plugs 209. There is a need to.

  As a result, after the bit line contact plug 209 is formed, in the step of forming a wiring on the insulating film 207, UV light passes through the insulating film 207 between the light shielding film 205 and the bit line contact plug 209 and the memory. There is a problem that the Vt of the memory cell in the vicinity of the bit line contact plug 209 rises due to the penetration into the vicinity of the cell.

  Further, if the distance from the bit line contact plug to the memory cell is increased in order to avoid the influence of the increase in Vt due to the penetration of UV light, the area of the entire semiconductor memory device increases accordingly.

  Therefore, Patent Document 1 discloses a method of blocking the UV light intrusion route as described above. This will be described below with reference to FIG.

As shown in FIG. 14, an interlayer insulating film 206 and a light shielding film 205 are formed on the memory cell 200.
The bit line contact plug 209 is formed so as to penetrate the light shielding film 205 and the interlayer insulating film 206. Here, since the light shielding film 205 uses an insulating film such as a silicon-rich oxide film or a silicon-rich nitride film, even if the light shielding film 205 is in contact with the bit line contact plug 209, the bit line contact plugs are short-circuited. Does not happen.

By forming the light shielding film 205 in this way, a path through which UV light generated in a manufacturing process of a wiring formed on the interlayer insulating film 206 enters can be blocked by the light shielding film 205 and the bit line contact plug 209. Therefore, unnecessary excited electrons can be prevented from being injected into the gate insulating film 203 included in the memory cell 200.
US Pat. No. 6,833,581

  The method described in Patent Document 1 is effective in that unnecessary excitation electrons can be prevented from being injected into the gate insulating film 203 by blocking the path through which UV light enters. Since it is formed of an insulating film, it has a lower light shielding property than a conductive light shielding film, and in practice, UV light cannot be sufficiently prevented from entering.

  The present invention has been made in view of the above points, and provides a highly reliable non-volatile semiconductor memory device and a method for manufacturing the same that prevent Vt fluctuation caused by UV light generated in the manufacturing process of the semiconductor memory device. For the purpose.

  A non-volatile semiconductor memory device manufacturing method according to the present invention includes a plurality of bit lines formed of diffusion layers formed on a semiconductor substrate, a trapping gate insulating film formed between adjacent bit lines, and the gate A method of manufacturing a semiconductor memory device including a memory cell including a word line formed on an insulating film, the step (a) of forming an interlayer insulating film on the memory cell, (B) simultaneously forming a first opening reaching the bit line and a second opening reaching the word line adjacent to the first opening or the semiconductor substrate in the vicinity of the word line; A step (c) of forming a light-shielding film in the opening and on the interlayer insulating film, and a step (d) of forming a bit line contact plug in which the conductive film is embedded in the first opening. In (c), the interlayer insulating film Light shielding film formed on is characterized in that it is formed in a region covering at least the memory cell.

  According to the above method, it is possible to form a light shielding film above the memory cell and on the side in the vicinity of the bit line contact plug by a simple method, whereby UV light generated in the wiring process is applied to the memory cell. An intrusion can be prevented and a highly reliable nonvolatile semiconductor memory device can be realized.

  In a preferred embodiment, in the step (c), a light shielding film is formed in the first opening continuously with the light shielding film formed on the interlayer insulating film, and the step (d) A step (d1) of selectively removing the light-shielding film formed in the one opening, and a step (d2) of embedding the conductive film in the first opening after the step (d1).

  In a preferred embodiment, the light shielding film is made of the same material as the conductive film, and in the step (c), the light shielding film is continuous with the light shielding film formed on the interlayer insulating film in the first opening. In the step (d), the bit line contact plug removes at least a part of the light shielding film formed between the first opening and the second opening on the interlayer insulating film. Thus, the light shielding film is formed so as to be electrically separated.

  In a preferred embodiment, the step (d2) includes a step of forming a conductive film in the first opening and on the interlayer insulating film via a light shielding film, and a step of forming the conductive film formed on the interlayer insulating film. And polishing until the light shielding film is exposed.

  In a preferred embodiment, the word line to which the light shielding film formed in the second opening is connected is a dummy word line that is not used for data retention.

  In a preferred embodiment, in the step (c), the light shielding film is formed to be embedded in the second opening.

  In a preferred embodiment, in the step (b), the second opening is formed in parallel to the word line.

  A nonvolatile semiconductor memory device according to the present invention includes a plurality of bit lines formed of diffusion layers formed on a semiconductor substrate, a trapping gate insulating film formed between adjacent bit lines, and a gate insulating film formed on the gate insulating film. A memory cell comprising a word line formed, an interlayer insulating film is formed on the memory cell, a bit line contact plug connected to the bit line is formed in the interlayer insulating film, and at least on the interlayer insulating film A light shielding film is formed in a region covering the memory cell, and a part of the light shielding film formed on the interlayer insulating film is adjacent to the bit line contact plug in the vicinity of the bit line contact plug or in the vicinity of the word line. The upper surface of the bit line contact plug is flush with the surface of the interlayer insulating film so as to be in contact with the semiconductor substrate. And characterized in that it.

  In a preferred embodiment, a part of the light shielding film formed extending in the interlayer insulating film is formed in parallel to the word line.

  In a preferred embodiment, the word line in contact with a part of the light shielding film is a dummy word line that is not used for data retention.

  In a preferred embodiment, the bit line contact plug and the light shielding film are made of the same material.

  In a preferred embodiment, an interval between word lines adjacent to the bit line contact plug is wider than an interval between other adjacent word lines in the memory cell.

  According to the nonvolatile semiconductor memory device of the present invention, it is possible to form a light shielding film above the memory cell and on the side in the vicinity of the bit line contact plug by a simple method. Intrusion of UV light into the memory cell can be prevented, and a highly reliable nonvolatile semiconductor memory device can be realized.

(First embodiment)
Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of simplicity. In addition, this invention is not limited to the following embodiment.

  1 to 5 are process cross-sectional views schematically showing the method for manufacturing the nonvolatile semiconductor memory device in the first embodiment of the present invention. In each figure, (a) is a plan view of a memory cell near the bit line contact plug, (b) is a cross-sectional view taken along line BB ′ of (a), and (c) is a cross-sectional view of (a). Sectional drawing in CC 'line, (d) has each shown sectional drawing in the DD' line of (a).

  First, as shown in FIGS. 1A to 1D, an element isolation film 101 that electrically isolates a region where a bit line contact plug will be formed later is formed on a semiconductor substrate 100. Next, a bit line 103 made of an n + diffusion layer and a bit line oxide film 106 are formed by a CVD (Chemical Vapor Deposition) method. Thereafter, a lower silicon oxide film is formed by a thermal oxidation method, an intermediate silicon nitride film is formed by a CVD method, and an upper silicon oxide film is formed by a thermal silicon oxide film method, and a trapping gate insulating film 102 made of an ONO laminated film is formed. Form each one. Next, a word line 104 made of polysilicon (including the dummy word line 105) and a buried insulating film 107 (for example, a silicon nitride film) are formed between the word lines 104. Here, the dummy word line 105 refers to a word line that is not used for data retention, and is formed with a bit line contact plug described later interposed therebetween.

  Next, as shown in FIGS. 2A to 2D, an interlayer insulating film (for example, silicon oxide film) 108 is formed on the entire surface of the substrate 100 by a CVD method, and connected to a bit line to be described later. A resist mask 109 having openings in regions where the bit line contact plug and the light shielding film connected to the dummy word line 105 are formed is formed.

  Next, as shown in FIGS. 3A to 3D, the interlayer insulating film 108 is removed by etching using the resist mask 109 as a mask, and the first insulating layer 108 reaches the bit line 103. An opening (contact hole) 120 and a second opening 121 reaching the dummy word line 105 adjacent to the first opening 120 are formed at the same time. Here, the first opening 120 and the second opening 121 are for embedding a bit line contact plug and a light shielding film, which will be described later, respectively.

  Next, as shown in FIGS. 4A to 4D, a light-shielding film (for example, a polysilicon film) 110 having a film thickness that does not transmit ultraviolet light (for example, 50 nm or more) is formed with the first opening 120 and An interlayer insulating film 108 is formed so as to be embedded in the second opening 121. Here, the light shielding film 110 does not need to completely embed the insides of the openings 120 and 121, and may only cover the inner walls of the openings 120 and 121 as long as the film thickness is necessary for light shielding. Thereafter, a resist mask 111 having an opening corresponding to the first opening (bit line contact plug formation region) 120 is formed.

  Next, as shown in FIGS. 5A to 5D, the resist mask 111 is used as a mask to selectively remove the light shielding film 110 embedded in the first opening 120, and then the first mask A conductive film 112 is formed on the interlayer insulating film 108 with the light shielding film 110 interposed therebetween so as to fill the opening 120. Thereafter, the conductive film 112 formed on the interlayer insulating film 108 is polished by a CMP (Chemical Mechanical Polishing) method until the light shielding film 110 is exposed, so that the bit line contact embedded in the first opening 120 is obtained. Plug 112 is formed.

  Here, by using the light-shielding film 110 as a polishing stopper, variations in the film thickness of the interlayer insulating film 108 due to the in-plane polishing rate difference can be suppressed. Further, by using the light shielding film 110 as a stopper, overpolishing is possible and the bit line contact plugs 112 can be separated from each other by dishing.

  In the nonvolatile semiconductor memory device formed by the above method, the UV light generated in the wiring process is applied to the memory cell by forming the light shielding film 110 above the memory cell and on the side near the bit line contact plug 112. An intrusion can be prevented and a highly reliable nonvolatile semiconductor memory device can be realized.

  In addition, the first opening 120 for embedding the bit line contact plug 112 and the second opening 121 for embedding the light-shielding film 110 are formed in the interlayer insulating film 108 at the same time, so that a lithography misalignment is not considered. Since the bit line contact plug 112 and the light shielding film 110 can be formed in the interlayer insulating film 108, a more miniaturized nonvolatile semiconductor memory device can be manufactured by a simple method.

  In the present embodiment, the light shielding film 110 may be made of the same material as the conductive film forming the bit line contact plug 112. In this case, the steps shown in FIGS. 5A to 5D are not necessary, but are separately formed between the first opening 120 and the second opening 121 and on the interlayer insulating film 108. It is necessary to electrically separate the bit line contact plug 112 and the light shielding film 110 by removing at least a part of the light shielding film 110 using, for example, cutting.

  In the present embodiment, the second opening 121 in which the light shielding film 110 is embedded is preferably formed in parallel to the word line 104. Thereby, UV light that enters the memory cell from the side near the bit line contact plug can be effectively blocked. Further, by forming the second opening 121 in the vicinity of the word line contact plug in parallel with the bit line 103, UV light entering the memory cell from the side in the vicinity of the word line contact plug can also be blocked. As a result, UV light entering from four sides of the memory cell can be completely blocked.

  In addition, in the nonvolatile semiconductor memory device formed by using the manufacturing method of this embodiment, a part of the light shielding film 110 formed on the interlayer insulating film 108 is in the vicinity of the bit line contact plug 112 and the bit line contact plug. 112 is formed so as to extend from the surface of the interlayer insulating film 108 so as to be in contact with the dummy word line 105 adjacent to 112, and the upper surface of the bit line contact plug 112 coincides with the surface of the interlayer insulating film 108. There is a structural feature in that the distance between the dummy word lines 105 adjacent to the bit line contact plug 112 is wider than the distance between the other adjacent word lines 104 in the memory cell.

(Second Embodiment)
In the first embodiment, a part of the light shielding film 110 formed on the interlayer insulating film 108 is exposed from the surface of the interlayer insulating film 108 so as to be in contact with the dummy word line 105 in the vicinity of the bit line contact plug 112. Although it is formed extending in the film, it may be formed so as to be in contact with the semiconductor substrate 100 in the vicinity of the dummy word line 105.

  A method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described below with reference to FIGS. In each figure, (a) is a plan view of a memory cell near the bit line contact plug, (b) is a cross-sectional view taken along line BB ′ of (a), and (c) is a cross-sectional view of (a). Sectional drawing in CC 'line, (d) has each shown sectional drawing in the DD' line of (a). Detailed description of the same steps as those in the first embodiment will be omitted.

  First, as shown in FIGS. 6A to 6D, a gate insulating film (ONO film) 101, a bit line 103, a word line 104 (not shown), a dummy word line 105, a bit line oxidation are formed on a semiconductor substrate 100. The film 106 and the buried insulating film 107 are formed by the same method as in the first embodiment. Note that the interval between adjacent dummy word lines 105 is wider than that in the first embodiment.

  Next, as shown in FIGS. 7A to 7D, an interlayer insulating film 108 is formed on the entire surface of the substrate 100, and a resist mask having a predetermined region opened thereon is formed thereon as in the first embodiment. 109 is formed.

  Next, as shown in FIGS. 8A to 8D, the interlayer insulating film 108 is removed by etching using the resist mask 109 as a mask, and the first insulating layer 108 reaches the bit line 103. The opening 120 and the second opening 121 that reaches the semiconductor substrate 100 (bit line 103) in the vicinity of the first opening 120 are formed at the same time.

  Next, as illustrated in FIGS. 9A to 9D, the light shielding film 110 is formed on the interlayer insulating film 108 so as to be embedded in the first opening 120 and the second opening 121. Note that the light shielding film 110 having a thickness necessary for light shielding may be formed so as to cover the inner walls of the openings 120 and 121. Thereafter, a resist mask 111 having an opening corresponding to the first opening 120 is formed.

  Next, as shown in FIGS. 10A to 10D, the resist mask 111 is used as a mask to selectively remove the light-shielding film 110 embedded in the first opening 120, and then the first mask A bit line contact plug 112 in which a conductive material is embedded is formed in the opening 120. Note that the method of filling the bit line contact plug 112 in the first opening 120 can be performed by the method described in the first embodiment.

  In the present embodiment, the light shielding film 110 may be made of the same material as the conductive film forming the bit line contact plug 112. In this case, the steps shown in FIGS. 10A to 10D are not necessary, but are separately formed between the first opening 120 and the second opening 121 and on the interlayer insulating film 108. It is necessary to electrically separate the bit line contact plug 112 and the light shielding film 110 by removing at least a part of the light shielding film 110 using, for example, cutting.

  In the present embodiment, the second opening 121 is formed so as to reach not the dummy word line 105 but the semiconductor substrate 100 in the vicinity of the dummy word line 105, thereby taking into account misalignment with the dummy word line. Instead, the second opening 121 can be formed. In addition, it is possible to avoid the factor that the second opening 121 is formed by stepping off the dummy word line 105 and the shape of the second opening 121 becomes unstable.

  As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course various modifications are possible. For example, in the above embodiment, the polysilicon film is exemplified as the light shielding film, but an insulating film may be used in addition to the conductive film. In the above embodiment, the description has been given of the memory cell including the trapping gate insulating film. However, as long as the writing of the memory cell is controlled by injecting electrons, the memory of another structure is used. The configuration of the present invention can also be applied to a cell.

  ADVANTAGE OF THE INVENTION According to this invention, the Vt fluctuation | variation resulting from the UV light which generate | occur | produces in the manufacturing process of a semiconductor memory device can be prevented, and a highly reliable non-volatile semiconductor memory device and its manufacturing method can be provided.

(A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 1st Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 1st Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 1st Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 1st Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 2nd Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 2nd Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 2nd Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 2nd Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 2nd Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the non-volatile semiconductor memory device in the 2nd Embodiment of this invention. It is the figure which showed the general structure of the memory cell which has the conventional trap property gate insulating film. It is sectional drawing which showed the structure of the bit-line contact plug vicinity of the conventional semiconductor memory device. (A)-(d) is process sectional drawing which showed the manufacturing method of the conventional semiconductor memory device. It is sectional drawing which showed the structure of the other conventional semiconductor memory device.

Explanation of symbols

100 Semiconductor substrate 101 Element isolation film 102 Gate insulating film (ONO film)
103 bit line 104 word line 105 dummy word line 106 bit line oxide film 107 buried insulating film 108 interlayer insulating film 109, 111 resist mask 110 light shielding film 112 bit line contact plug 120 first opening 121 second opening

Claims (12)

A plurality of bit lines made of diffusion layers formed on a semiconductor substrate, a trapping gate insulating film formed between adjacent bit lines, and a word line formed on the gate insulating film A method of manufacturing a nonvolatile semiconductor memory device including a memory cell,
Forming an interlayer insulating film on the memory cell;
A first opening reaching the bit line and a second opening reaching the word line adjacent to the first opening or the semiconductor substrate in the vicinity of the word line are simultaneously formed in the interlayer insulating film. Forming step (b);
A step (c) of forming a light shielding film in the second opening and on the interlayer insulating film;
Forming a bit line contact plug in which a conductive film is embedded in the first opening (d),
In the step (c), the light shielding film formed on the interlayer insulating film is formed in a region covering at least the memory cell. In the step (c), the light shielding film is also formed in the first opening continuously with the light shielding film formed on the interlayer insulating film,
The step (d)
A step (d1) of selectively removing the light shielding film formed in the first opening;
The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising a step (d2) of embedding the conductive film in the first opening after the step (d1). The light shielding film is made of the same material as the conductive film,
In the step (c), the light shielding film is also formed in the first opening continuously with the light shielding film formed on the interlayer insulating film,
In the step (d), the bit line contact plug is formed between the first opening and the second opening and includes at least a part of the light shielding film formed on the interlayer insulating film. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is formed so as to be electrically separated from the light shielding film by being removed. The step (d2)
Forming the conductive film in the first opening and on the interlayer insulating film via the light shielding film;
The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, further comprising: polishing the conductive film formed on the interlayer insulating film until the light shielding film is exposed.   2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the word line to which the light shielding film formed in the second opening is connected is a dummy word line that is not used for data retention.   2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein in the step (c), the light shielding film is formed to be embedded in the second opening.   2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein in the step (b), the second opening is formed in parallel to the word line. A plurality of bit lines made of diffusion layers formed on a semiconductor substrate, a trapping gate insulating film formed between adjacent bit lines, and a word line formed on the gate insulating film In a nonvolatile semiconductor memory device including a memory cell,
An interlayer insulating film is formed on the memory cell;
A bit line contact plug connected to the bit line is formed in the interlayer insulating film,
A light shielding film is formed in a region covering at least the memory cell on the interlayer insulating film;
A portion of the light shielding film formed on the interlayer insulating film is in contact with the word line adjacent to the bit line contact plug or the semiconductor substrate in the vicinity of the word line in the vicinity of the bit line contact plug. It is formed extending from the surface of the interlayer insulating film into the film,
The nonvolatile semiconductor memory device, wherein an upper surface of the bit line contact plug coincides with a surface of the interlayer insulating film.   The nonvolatile semiconductor memory device according to claim 8, wherein a part of the light shielding film formed to extend in the interlayer insulating film is formed in parallel to the word line.   The nonvolatile semiconductor memory device according to claim 8, wherein the word line that is in contact with a part of the light shielding film is a dummy word line that is not used for data retention.   The nonvolatile semiconductor memory device according to claim 8, wherein the bit line contact plug and the light shielding film are made of the same material.   9. The nonvolatile semiconductor memory device according to claim 8, wherein an interval between word lines adjacent to the bit line contact plug is wider than an interval between other adjacent word lines in the memory cell.

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