JP2009069768A - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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JP2009069768A
JP2009069768A JP2007240836A JP2007240836A JP2009069768A JP 2009069768 A JP2009069768 A JP 2009069768A JP 2007240836 A JP2007240836 A JP 2007240836A JP 2007240836 A JP2007240836 A JP 2007240836A JP 2009069768 A JP2009069768 A JP 2009069768A
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signal line
liquid crystal
scanning
display device
crystal display
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Takahiko Abe
孝彦 阿部
Katsuhiko Inada
克彦 稲田
Hideyuki Takahashi
英幸 高橋
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Japan Display Central Inc
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Toshiba Matsushita Display Technology Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device in which display unevenness is scarcely produced. <P>SOLUTION: The display unevenness is made to be scarcely produced by providing a plurality of pixel electrodes, pixel transistors, signal lines, scanning lines, a counter substrate, and a liquid crystal layer, arranged on a display area with a shape of a polygon with five or more angles or with a circular shape on an array substrate, intersecting all signal lines X and all scanning lines Y together to uniformize capacitance of each scanning line Y and to scarcely produce delay time difference of scanning voltages. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、液晶表示装置に関し、詳しくは表示ムラを発生しにくくする技術に関する。   The present invention relates to a liquid crystal display device, and more particularly to a technique for making display unevenness difficult to occur.

近年では、表示形態の多様化より、円形の表示エリアをもつ液晶表示装置が多く利用されるようになった。   In recent years, liquid crystal display devices having a circular display area have been widely used due to diversification of display forms.

図４は、かかる液晶表示装置の概略的な平面図である。   FIG. 4 is a schematic plan view of such a liquid crystal display device.

この液晶表示装置では、アレイ基板１上の複数の画素電極Ｐが円形に配置されて表示エリアを構成している。   In this liquid crystal display device, a plurality of pixel electrodes P on the array substrate 1 are arranged in a circle to form a display area.

駆動回路２から配線部６を介してデジタルデータが信号線駆動回路３に送信され、信号線駆動回路３から信号線Ｘに映像信号が供給される。走査線駆動回路４が走査線Ｙを駆動すると、図示しない画素トランジスタがオンし、映像信号が画素電極Ｐに書き込まれる。一方、対向電極（図示せず）には、例えば、一定の電位が与えられる。   Digital data is transmitted from the drive circuit 2 to the signal line drive circuit 3 via the wiring portion 6, and a video signal is supplied from the signal line drive circuit 3 to the signal line X. When the scanning line driving circuit 4 drives the scanning line Y, a pixel transistor (not shown) is turned on, and a video signal is written to the pixel electrode P. On the other hand, for example, a constant potential is applied to the counter electrode (not shown).

これにより、画素電極Ｐと、対向電極の間に電位差が生じ、この電位差により液晶層（図示せず）内の光の透過率が設定される。   Thereby, a potential difference is generated between the pixel electrode P and the counter electrode, and the light transmittance in the liquid crystal layer (not shown) is set by this potential difference.

また、例えば、バックライト光源（図示せず）を出射した光が液晶層を通り出射する。この光は、液晶層内の光の透過率に応じた光量をもち、こうして、画像が表示される。   Further, for example, light emitted from a backlight light source (not shown) is emitted through the liquid crystal layer. This light has a light amount corresponding to the light transmittance in the liquid crystal layer, and thus an image is displayed.

図４に示すように、円形の表示エリアの中央付近を直線的に貫く信号線Ｘ（信号線Ｘａなど）により映像信号を書き込まれる画素電極Ｐの数よりも、表示エリアの周縁部付近に回り込む信号線Ｘ（信号線Ｘｂなど）により映像信号を書き込まれる画素電極Ｐの数の方が少ない。そのため、表示エリアの中央付近の信号線Ｘの終端位置の垂直走査方向における座標と表示エリアの周縁部付近の信号線Ｘの終端位置の垂直走査方向における座標が相違する。終端位置は保護ダイオードＤで終端されている。   As shown in FIG. 4, the number of pixel electrodes P to which a video signal is written by a signal line X (signal line Xa or the like) linearly penetrating near the center of the circular display area goes around the periphery of the display area. The number of pixel electrodes P to which video signals are written by the signal lines X (signal lines Xb, etc.) is smaller. Therefore, the coordinates in the vertical scanning direction of the terminal position of the signal line X near the center of the display area are different from the coordinates in the vertical scanning direction of the terminal position of the signal line X near the peripheral edge of the display area. The termination position is terminated by a protection diode D.

垂直走査方向における座標の相違のため、全ての信号線Ｘに交差する走査線（走査線Ｙａなど）と、一部の信号線Ｘにだけ交差する走査線（走査線Ｙｂなど）ができる。走査線は、信号線Ｘとの交差箇所に容量を有するので、全ての信号線に交差する走査線の容量よりも一部の信号線にだけ交差する走査線の容量の方が少ない。   Due to the difference in coordinates in the vertical scanning direction, scanning lines that intersect all the signal lines X (such as scanning lines Ya) and scanning lines that intersect only a part of the signal lines X (such as scanning lines Yb) are formed. Since the scanning line has a capacitance at the intersection with the signal line X, the capacitance of the scanning line that intersects only a part of the signal lines is smaller than the capacitance of the scanning line that intersects all the signal lines.

走査線Ｙの容量の差異により、走査電圧の遅延時間の差異が生じる。そのため、表示ムラが見える可能性がある。   Due to the difference in the capacitance of the scanning line Y, a difference in the delay time of the scanning voltage occurs. Therefore, display unevenness may be visible.

また、図５に示すように、画素電極Ｐと信号線Ｘの間には容量ｃｐ１、ｃｐ２が生じる。よって、映像信号が書き込まれる画素電極Ｐの数が多い信号線Ｘの容量よりも、映像信号が書き込まれる画素電極Ｐの数が少ない信号線Ｘの容量の方が少ない。つまり、表示エリアの中央付近を直線的に貫く信号線Ｘ（信号線Ｘａなど）の容量よりも、表示エリアの周縁部付近に回り込む信号線Ｘ（信号線Ｘｂなど）の容量の方が小さい。これも、表示ムラの原因になる。   Further, as shown in FIG. 5, capacitances cp1 and cp2 are generated between the pixel electrode P and the signal line X. Therefore, the capacity of the signal line X having a small number of pixel electrodes P to which video signals are written is smaller than the capacity of the signal line X having a large number of pixel electrodes P to which video signals are written. That is, the capacity of the signal line X (such as the signal line Xb) that wraps around the periphery of the display area is smaller than the capacity of the signal line X (such as the signal line Xa) that linearly passes through the vicinity of the center of the display area. This also causes display unevenness.

なお、Ｙは走査線、ＣＳは補助容量線、Ｑは画素トランジスタ、Ｃは画素電極Ｐと補助容量線ＣＳの間の容量、ｃｐ３は画素電極Ｐと対向電極との間の容量、ｃｐ４は信号線Ｘと大地間の容量である。   Y is a scanning line, CS is an auxiliary capacitance line, Q is a pixel transistor, C is a capacitance between the pixel electrode P and the auxiliary capacitance line CS, cp3 is a capacitance between the pixel electrode P and the counter electrode, and cp4 is a signal. It is the capacity between line X and the ground.

また、表示エリアの中央付近を直線的に貫く信号線Ｘ（信号線Ｘａなど）の長さよりも、表示エリアの周縁部付近に回り込む信号線Ｘ（信号線Ｘｂなど）の長さの方が長い。よって、前者の信号線Ｘの抵抗値よりも、後者の信号線Ｘの抵抗値の方が大きい。これも、表示ムラの原因になる。   Further, the length of the signal line X (such as the signal line Xb) that wraps around the periphery of the display area is longer than the length of the signal line X (such as the signal line Xa) that linearly passes through the vicinity of the center of the display area. . Therefore, the resistance value of the latter signal line X is larger than the resistance value of the former signal line X. This also causes display unevenness.

この出願の発明に関連する先行技術文献情報としては次のものがある。
特開２００６−２７６３５９号公報 Prior art document information related to the invention of this application includes the following.
JP 2006-276359 A

本発明は、上記の課題に鑑みてなされたものであり、その目的とするところは、表示ムラを発生しにくくできる液晶表示装置を提供することにある。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device that can hardly cause display unevenness.

上記の課題を解決するために、第１の本発明に係る液晶表示装置は、アレイ基板上において５以上の角を有する多角形または円形の表示エリアに配置された複数の画素電極と、前記各画素電極に対して設けられた画素トランジスタと、垂直走査方向に並ぶ前記各画素電極に対して設けられた信号線と、水平走査方向に並ぶ前記各画素電極に対して設けられた走査線と、前記アレイ基板と対向配置された対向基板と、前記アレイ基板と対向基板との間に挟持された液晶層と、を備え、全ての前記信号線と全ての前記走査線とが交差することを特徴とする。   In order to solve the above problems, a liquid crystal display device according to a first aspect of the present invention includes a plurality of pixel electrodes arranged in a polygonal or circular display area having five or more corners on an array substrate, A pixel transistor provided for a pixel electrode, a signal line provided for each pixel electrode arranged in a vertical scanning direction, a scanning line provided for each pixel electrode arranged in a horizontal scanning direction, A counter substrate disposed opposite to the array substrate; and a liquid crystal layer sandwiched between the array substrate and the counter substrate, wherein all the signal lines and all the scanning lines intersect. And

第１の本発明によれば、全ての信号線と全ての走査線とが交差することで、各走査線の容量の均一化が図られ、走査電圧の遅延時間の差異が生じににくくなり、よって、表示ムラを発生しにくくすることができる。   According to the first aspect of the present invention, since all the signal lines and all the scanning lines intersect with each other, the capacitance of each scanning line is made uniform, and the difference in the delay time of the scanning voltage is less likely to occur. Therefore, display unevenness can be made difficult to occur.

第２の本発明に係る液晶表示装置は、前記信号線は、前記画素電極に隣り合う部分と当該画素電極に隣り合わない部分とを有し、前者の前記部分は、後者の前記部分の幅よりも短い幅を有する部分を含むことを特徴とする。   In the liquid crystal display device according to the second aspect of the present invention, the signal line has a portion adjacent to the pixel electrode and a portion not adjacent to the pixel electrode, and the former portion is the width of the latter portion. And a portion having a shorter width.

第２の本発明によれば、画素電極に隣り合う信号線の部分が、画素電極に隣り合わない信号線の部分の幅よりも短い幅の部分を含むことで、当該短い部分の長さによって、各信号線の容量および抵抗値の均一化を図ることができ、そうすることによって、表示ムラを発生しにくくすることができる。   According to the second aspect of the present invention, the portion of the signal line adjacent to the pixel electrode includes a portion having a width shorter than the width of the portion of the signal line not adjacent to the pixel electrode. The capacitance and resistance value of each signal line can be made uniform, so that display unevenness can be made difficult to occur.

第３の本発明に係る液晶表示装置は、前記信号線の長さが長いほど当該信号線における前記短い幅を有する部分の長さが短いことを特徴とする。   The liquid crystal display device according to a third aspect of the present invention is characterized in that the longer the signal line is, the shorter the portion of the signal line having the short width is.

第３の本発明によれば、信号線の長さが長いほど当該信号線における短い幅を有する部分の長さが短いことで、各信号線の容量および抵抗値の均一化を図ることができ、表示ムラを発生しにくくすることができる。   According to the third aspect of the present invention, the longer the length of the signal line, the shorter the length of the portion having the shorter width in the signal line, so that the capacitance and resistance value of each signal line can be made uniform. , Display unevenness can be made difficult to occur.

第４の本発明に係る液晶表示装置は、前者の前記部分に対し、後者の前記部分の幅を有する遮光部材が対向配置されていることを特徴とする。   The liquid crystal display device according to a fourth aspect of the present invention is characterized in that a light-shielding member having a width of the latter part is disposed opposite to the former part.

第４の本発明によれば、画素電極に隣り合う信号線の部分に対し、画素電極に隣り合わない信号線の部分の幅を有する遮光部材が対向配置されていることで、信号線における短い幅を有する部分を設けた影響がなくなり、光漏れを防止することができる。   According to the fourth aspect of the present invention, the light shielding member having the width of the signal line portion not adjacent to the pixel electrode is disposed opposite to the signal line portion adjacent to the pixel electrode, so that the signal line is short. The influence of providing a portion having a width is eliminated, and light leakage can be prevented.

本発明に係る液晶表示装置よれば、全ての信号線と全ての走査線とが交差することで、各走査線の容量の均一化が図られ、走査電圧の遅延時間の差異が生じににくくなり、よって、表示ムラを発生しにくくすることができる。   According to the liquid crystal display device of the present invention, since all the signal lines and all the scanning lines intersect, the capacitance of each scanning line is made uniform, and the difference in the scanning voltage delay time hardly occurs. Therefore, display unevenness can be made difficult to occur.

以下、本発明の実施の形態を図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、一実施の形態に係る液晶表示装置の概略的な平面図である。   FIG. 1 is a schematic plan view of a liquid crystal display device according to an embodiment.

図１に示すように、液晶表示装置は、アレイ基板１と、液晶層および液晶層を挟んでアレイ基板１に対向する対向基板（共に図示せず）を備える。この対向基板には、図示しない対向電極が設けられている。   As shown in FIG. 1, the liquid crystal display device includes an array substrate 1 and a counter substrate (both not shown) facing the array substrate 1 with the liquid crystal layer and the liquid crystal layer interposed therebetween. The counter substrate is provided with a counter electrode (not shown).

アレイ基板１には、複数の画素電極Ｐ、複数の信号線Ｘ、複数の走査線Ｙ、複数の補助容量線および画素トランジスタ（図１では共に図示せず）、駆動回路２、信号線駆動回路３、２分割された走査線駆動回路４、終端回路５および配線部６が形成されている。   The array substrate 1 includes a plurality of pixel electrodes P, a plurality of signal lines X, a plurality of scanning lines Y, a plurality of auxiliary capacitance lines and pixel transistors (both not shown in FIG. 1), a drive circuit 2, and a signal line drive circuit. 3, the scanning line driving circuit 4 divided into two parts, the termination circuit 5 and the wiring part 6 are formed.

画素電極Ｐは円形に配置されて表示エリアを構成している。画素電極Ｐは、例えば、ＩＴＯ（Indium Tin Oxide:酸化インジウムスズ）などで形成される。   The pixel electrodes P are arranged in a circle to form a display area. The pixel electrode P is made of, for example, ITO (Indium Tin Oxide).

信号線Ｘは、垂直走査方向に並ぶ各画素電極Ｐに対して設けられている。走査線Ｙは、水平走査方向に並ぶ各画素電極Ｐに対して設けられている。全ての信号線Ｘと全ての走査線Ｙとが交差している。   The signal line X is provided for each pixel electrode P arranged in the vertical scanning direction. The scanning line Y is provided for each pixel electrode P arranged in the horizontal scanning direction. All signal lines X and all scanning lines Y intersect.

円形の表示エリアの中央付近を直線的に貫く信号線Ｘ（信号線Ｘａなど）はもちろん、表示エリアの周縁部付近に回り込む信号線Ｘ（信号線Ｘｂなど）も全ての走査線Ｙに交差している。信号線Ｘは信号線駆動回路３に接続され、走査線Ｙは走査線駆動回路４に接続されている。   Not only the signal line X (signal line Xa, etc.) linearly passing through the center of the circular display area, but also the signal line X (signal line Xb, etc.) that wraps around the periphery of the display area intersects all scanning lines Y. ing. The signal line X is connected to the signal line driving circuit 3, and the scanning line Y is connected to the scanning line driving circuit 4.

配線部６は、信号線駆動回路３と駆動回路２を接続している。終端回路５は、各信号線Ｘの終端位置を保護ダイオード（図示せず）で終端している。   The wiring unit 6 connects the signal line drive circuit 3 and the drive circuit 2. The termination circuit 5 terminates the termination position of each signal line X with a protection diode (not shown).

図２は、信号線Ｘと走査線Ｙの交差箇所における回路図である。   FIG. 2 is a circuit diagram at the intersection of the signal line X and the scanning line Y.

画素トランジスタＱは、例えばＴＦＴ（Thin Film Transistor)であり、信号線Ｘに、画素トランジスタＱのソース電極、走査線Ｙに画素トランジスタＱのゲート電極、画素電極Ｐに画素トランジスタＱのドレイン電極がそれぞれ接続されている。   The pixel transistor Q is, for example, a TFT (Thin Film Transistor), and the signal line X includes the source electrode of the pixel transistor Q, the scanning line Y includes the gate electrode of the pixel transistor Q, and the pixel electrode P includes the drain electrode of the pixel transistor Q. It is connected.

走査線Ｙに沿って配置された補助容量線ＣＳと画素電極Ｐとで補助容量Ｃが構成されている。   A storage capacitor C is configured by the storage capacitor line CS and the pixel electrode P arranged along the scanning line Y.

また、図示しないが、例えば、全ての画素電極Ｐに対向する対向電極が対向基板に形成されている。   Although not shown, for example, a counter electrode facing all the pixel electrodes P is formed on the counter substrate.

画素電極Ｐと対向電極の間の液晶層により液晶容量ＣＬが構成されている。   A liquid crystal capacitor CL is constituted by the liquid crystal layer between the pixel electrode P and the counter electrode.

図３は、画素電極Ｐに隣り合う信号線Ｘの部分とその近傍における平面図と該図のＡＡ’線断面図を示す図である。   FIG. 3 is a diagram showing a portion of the signal line X adjacent to the pixel electrode P, a plan view in the vicinity thereof, and a cross-sectional view taken along the line AA ′ of FIG.

信号線Ｘは、画素電極Ｐに隣り合う部分つまり、画素電極Ｐの長さＬｐと同じ長さをもつ部分と、画素電極Ｐに隣り合わない部分とを有する。画素電極Ｐに隣り合う部分は、画素電極Ｐに隣り合わない部分の幅Ｗよりも短い幅ＷＰを有する部分を含む。   The signal line X has a portion adjacent to the pixel electrode P, that is, a portion having the same length as the length Lp of the pixel electrode P, and a portion not adjacent to the pixel electrode P. The portion adjacent to the pixel electrode P includes a portion having a width WP shorter than the width W of the portion not adjacent to the pixel electrode P.

また、図示しないが、信号線Ｘの長さが長いほど該信号線Ｘにおける幅ＷＰの部分の長さＬが短い。   Although not shown, the length L of the width WP portion of the signal line X is shorter as the length of the signal line X is longer.

また、画素電極Ｐに隣り合う信号線Ｘの部分に対し、画素電極Ｐに隣り合わない信号線Ｘの部分の幅Ｗを有する遮光部材Ｍが対向配置されている。   Further, a light shielding member M having a width W of a portion of the signal line X not adjacent to the pixel electrode P is disposed opposite to the portion of the signal line X adjacent to the pixel electrode P.

液晶表示装置では、以下のように表示がなされる。   In the liquid crystal display device, display is performed as follows.

駆動回路２から配線部６を介してデジタルデータが信号線駆動回路３に送信され、信号線駆動回路３から信号線Ｘに映像信号が供給される。走査線駆動回路４が走査線Ｙを駆動すると、画素トランジスタＱがオンし、映像信号が画素電極Ｐに書き込まれる。   Digital data is transmitted from the drive circuit 2 to the signal line drive circuit 3 via the wiring portion 6, and a video signal is supplied from the signal line drive circuit 3 to the signal line X. When the scanning line driving circuit 4 drives the scanning line Y, the pixel transistor Q is turned on, and the video signal is written to the pixel electrode P.

一方、対向電極には、例えば、一定の電位が与えられる。   On the other hand, for example, a constant potential is applied to the counter electrode.

これにより、画素電極Ｐと、対向電極の間に電位差が生じ、この電位差により液晶層内の光の透過率が設定される。   Thereby, a potential difference is generated between the pixel electrode P and the counter electrode, and the light transmittance in the liquid crystal layer is set by the potential difference.

また、例えば、アレイ基板１の背面側に設置されるバックライト光源（図示せず）を出射した光が、液晶層を通り、対向基板の前面側から出射する。この光は、液晶層内の光の透過率に応じた光量をもち、こうして、画像が表示される。   Further, for example, light emitted from a backlight light source (not shown) installed on the back side of the array substrate 1 passes through the liquid crystal layer and is emitted from the front side of the counter substrate. This light has a light amount corresponding to the light transmittance in the liquid crystal layer, and thus an image is displayed.

そして、画像表示にあっては、以下のように表示ムラを発生しにくくすることができる。   In image display, display unevenness can be made difficult to occur as follows.

まず、全ての信号線Ｘと全ての走査線Ｙとが交差することで、各走査線Ｙの容量の均一化が図られ、走査電圧の遅延時間の差異が生じににくくなり、よって、表示ムラを発生しにくくすることができる。   First, since all the signal lines X and all the scanning lines Y cross each other, the capacitance of each scanning line Y is made uniform, and the difference in the delay time of the scanning voltage becomes difficult to occur. Can be made difficult to occur.

また、画素電極Ｐに隣り合う信号線Ｘの部分に、画素電極Ｐに隣り合わない信号線Ｘの部分の幅Ｗよりも短い幅ＷＰの部分を設けたのだが、表示エリアの中央付近を直線的に貫く信号線Ｘ（信号線Ｘａなど）における幅ＷＰの部分の長さＬを、表示エリアの周縁部付近に回り込む信号線Ｘ（信号線Ｘｂなど）における幅ＷＰの部分の長さＬよりも長くする。つまり、信号線Ｘの長さが長いほど当該信号線Ｘにおける幅ＷＰの部分の長さを短くする。   In addition, a portion of the signal line X adjacent to the pixel electrode P is provided with a portion having a width WP shorter than the width W of the portion of the signal line X not adjacent to the pixel electrode P. The length L of the width WP portion of the signal line X (such as the signal line Xa) that penetrates the signal line X is larger than the length L of the width WP portion of the signal line X (such as the signal line Xb) that goes around the periphery of the display area. Also make it longer. That is, the longer the length of the signal line X, the shorter the length of the width WP portion in the signal line X.

これにより、表示エリアの中央付近の信号線Ｘにより映像信号が書き込まれる画素電極Ｐの数よりも、表示エリアの周縁部付近の信号線Ｘにより映像信号が書き込まれる画素電極Ｐの数の方が少なくなっても、表示エリアの中央付近の信号線Ｘ（信号線Ｘａなど）の容量と表示エリアの周縁部付近の信号線（信号線Ｘｂなど）の容量を同等にすることができる。つまり、各信号線Ｘの容量の均一化が図られ、表示ムラを発生しにくくすることができる。   Thus, the number of pixel electrodes P to which video signals are written by the signal lines X near the periphery of the display area is greater than the number of pixel electrodes P to which video signals are written by the signal lines X near the center of the display area. Even if the number is reduced, the capacity of the signal line X (such as the signal line Xa) near the center of the display area can be made equal to the capacity of the signal line (such as the signal line Xb) near the periphery of the display area. That is, the capacity of each signal line X can be made uniform, and display unevenness can be made difficult to occur.

表示エリアの中央付近の信号線Ｘは、幅ＷＰの部分の長さＬを長くすることで容量が小さくなり、一方、表示エリアの周縁部付近の信号線Ｘでは、画素電極Ｐの数の方が少ないことで容量が小さくなり、その結果、容量が均一化されるのである。   The capacity of the signal line X near the center of the display area is reduced by increasing the length L of the width WP. On the other hand, in the signal line X near the periphery of the display area, the number of pixel electrodes P is smaller. If the amount is small, the capacity is reduced, and as a result, the capacity is made uniform.

また、信号線Ｘに幅ＷＰの部分を設けない場合には、表示エリアの中央付近の信号線Ｘの抵抗値よりも表示エリアの周縁部付近の信号線Ｘの抵抗値は大きかった。本実施の形態では、信号線Ｘに幅ＷＰの部分を設け、この幅ＷＰの長さＬを各信号線で調節して、信号線Ｘの長さが長いほど当該信号線Ｘにおける幅ＷＰの部分の長さを短くすることにより、表示エリアの中央付近の信号線Ｘ（信号線Ｘａなど）の抵抗値を、表示エリアの周縁部付近の信号線Ｘ（信号線Ｘｂなど）の抵抗値と同等にすることができる。つまり、各信号線Ｘの抵抗値の均一化が図られ、表示ムラを発生しにくくすることができる。   Further, when the signal line X was not provided with the width WP, the resistance value of the signal line X near the periphery of the display area was larger than the resistance value of the signal line X near the center of the display area. In the present embodiment, the signal line X is provided with a portion having a width WP, and the length L of the width WP is adjusted by each signal line. The longer the length of the signal line X, the greater the width WP of the signal line X. By reducing the length of the portion, the resistance value of the signal line X (signal line Xa, etc.) near the center of the display area is changed from the resistance value of the signal line X (signal line Xb, etc.) near the periphery of the display area. Can be equivalent. That is, the resistance value of each signal line X can be made uniform, and display unevenness can be made difficult to occur.

また、仮に遮光部材Ｍが設けられていないと、画素電極Ｐに隣り合わない信号線Ｘの部分の幅Ｗよりも短い幅ＷＰを有する信号線Ｘの部分を設けたことに起因して、例えば、アレイ基板１の背面に配置されるバックライトからの光がアレイ基板１の前面側に多く透過してしまうことがある。つまり、光漏れを起こすことがある。   Further, if the light shielding member M is not provided, the signal line X having a width WP shorter than the width W of the signal line X that is not adjacent to the pixel electrode P is provided. A large amount of light from the backlight disposed on the back surface of the array substrate 1 may be transmitted to the front surface side of the array substrate 1. That is, light leakage may occur.

しかし、この光漏れを防止すべく、遮光部材Ｍを設けたことで、信号線Ｘにおける短い幅ＷＰを有する部分を設けた影響がなくなり、光漏れを防止することができる。   However, by providing the light shielding member M to prevent this light leakage, the influence of providing the portion having the short width WP in the signal line X is eliminated, and the light leakage can be prevented.

なお、本実施の形態では、複数の画素電極を円形の表示エリアに配置したが、複数の画素電極を５以上の角を有する多角形の表示エリアに配置した場合であっても同様の作用効果が得られる。   In the present embodiment, a plurality of pixel electrodes are arranged in a circular display area. However, the same effect can be obtained even when a plurality of pixel electrodes are arranged in a polygonal display area having five or more corners. Is obtained.

一実施の形態に係る液晶表示装置の概略的な平面図である。1 is a schematic plan view of a liquid crystal display device according to an embodiment. 信号線Ｘと走査線Ｙの交差箇所における回路図である。3 is a circuit diagram at a crossing point of a signal line X and a scanning line Y. FIG. 画素電極Ｐに隣り合う信号線Ｘの部分とその近傍における平面図と該図のＡＡ’線断面図を示す図である。FIG. 2 is a diagram illustrating a portion of a signal line X adjacent to a pixel electrode P, a plan view in the vicinity thereof, and a cross-sectional view taken along the line AA ′ of FIG. 従来の円形の表示エリアをもつ液晶表示装置の概略的な平面図である。It is a schematic plan view of a conventional liquid crystal display device having a circular display area. 画素の等価回路を示す回路図である。It is a circuit diagram which shows the equivalent circuit of a pixel.

符号の説明Explanation of symbols

１…アレイ基板
３…信号線駆動回路
４…走査線駆動回路
５…終端回路
６…配線部
Ｃ…補助容量
ＣＬ…液晶容量
ＣＳ…補助容量線
Ｄ…保護ダイオード
Ｍ…遮光部材
Ｐ…画素電極
Ｑ…画素トランジスタ
Ｘ、Ｘａ、Ｘｂ…信号線
Ｙ、Ｙａ、Ｙｂ…走査線 DESCRIPTION OF SYMBOLS 1 ... Array substrate 3 ... Signal line drive circuit 4 ... Scanning line drive circuit 5 ... Termination circuit 6 ... Wiring part C ... Auxiliary capacity CL ... Liquid crystal capacity CS ... Auxiliary capacity line D ... Protection diode M ... Light shielding member P ... Pixel electrode Q ... Pixel transistors X, Xa, Xb ... Signal lines Y, Ya, Yb ... Scanning lines

Claims (4)

アレイ基板上において５以上の角を有する多角形または円形の表示エリアに配置された複数の画素電極と、
前記各画素電極に対して設けられた画素トランジスタと、
垂直走査方向に並ぶ前記各画素電極に対して設けられた信号線と、
水平走査方向に並ぶ前記各画素電極に対して設けられた走査線と、
前記アレイ基板と対向配置された対向基板と、
前記アレイ基板と対向基板との間に挟持された液晶層と、
を備え、
全ての前記信号線と全ての前記走査線とが交差する
ことを特徴とする液晶表示装置。 A plurality of pixel electrodes arranged in a polygonal or circular display area having five or more corners on the array substrate;
A pixel transistor provided for each of the pixel electrodes;
A signal line provided for each of the pixel electrodes arranged in the vertical scanning direction;
A scanning line provided for each of the pixel electrodes arranged in the horizontal scanning direction;
A counter substrate disposed opposite to the array substrate;
A liquid crystal layer sandwiched between the array substrate and the counter substrate;
With
All the signal lines and all the scanning lines intersect. A liquid crystal display device, wherein: 前記信号線は、前記画素電極に隣り合う部分と当該画素電極に隣り合わない部分とを有し、前者の前記部分は、後者の前記部分の幅よりも短い幅を有する部分を含むことを特徴とする請求項１記載の液晶表示装置。   The signal line has a portion adjacent to the pixel electrode and a portion not adjacent to the pixel electrode, and the former portion includes a portion having a width shorter than that of the latter portion. The liquid crystal display device according to claim 1. 前記信号線の長さが長いほど当該信号線における前記短い幅を有する部分の長さが短いことを特徴とする請求項２記載の液晶表示装置。   3. The liquid crystal display device according to claim 2, wherein the length of the signal line is shorter as the length of the signal line is longer. 前者の前記部分に対し、後者の前記部分の幅を有する遮光部材が対向配置されていることを特徴とする請求項２または３記載の液晶表示装置。   4. The liquid crystal display device according to claim 2, wherein a light shielding member having a width of the latter part is disposed opposite to the former part.
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