JP2009054695A - Circuit wiring board and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit wiring board that improves thermal-cycle resistance of a contact interface part between a conductive via and a conductive layer especially in a multilayer wiring board, thus achieving high connection reliability, and also to provide its manufacturing method. <P>SOLUTION: The circuit wiring board has an insulating substrate 2a, a via hole VH2 formed such that it runs through the insulating substrate, a conductive via 2d formed by filling a conductive paste into the via hole, and conductive layers 1b and 2b for circuit wiring that are arranged on both sides of the insulating substrate and respectively connected to each end surface of the conductive via, wherein at least one of the two conductive layers has a concave portion C formed in an inter-layer contact part 2bc corresponding to the via hole. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a circuit wiring board and a method for manufacturing the circuit wiring board, and more particularly to a circuit wiring board capable of obtaining high connection reliability between a conductive via for interlayer connection and a wiring conductive layer in a multilayer wiring board and a method for manufacturing the circuit wiring board.

  In recent years, various digital electronic devices such as mobile phones and notebook computers have been rapidly reduced in size, weight, and functionality. Since it is desired to reduce the wiring distance between the various electronic components mounted on these electronic devices as much as possible, the wiring board on which electronic components are mounted has progressed in the direction of high-density wiring and high multi-layers. There is a growing trend to adopt laminated wiring board technology such as wiring boards.

  The following prior art 1 and prior art 2 are known as specific examples of the prior art relating to this type of multilayer wiring board.

<Prior Art 1>: (See Patent Document 1 as an example)
IVH (Interstitial Via Hole) formed by laminating a plurality of wiring board materials having a conductive pattern formed on the surface of the film-like insulator and forming a desired positional relationship on each of the film-like insulators for each conductive pattern interlayer connection A technology that fills with conductive paste (conductive via). According to this IVH utilization technique, interlayer connection can be made at an arbitrary position of each wiring board material, and each conductive via provided in each wiring board material can also be arranged in a vertically stacked state. Because of the high degree of freedom of wiring and compatibility with high-density wiring, it is being actively developed as a next-generation mounting board.

<Prior Art 2>: (See Patent Document 2 as an example)
In the same field as prior art 1, the contact surface of the conductive pattern contacting the end surface of the conductive via is roughened for the purpose of reducing the connection resistance between the conductive via and the conductive pattern by filling the conductive paste and improving the heat resistance reliability. To adjust the relationship between the surface roughness and the diameter of the conductive powder used in the conductive paste.

  By the way, in order to evaluate the connection reliability of the electrical interlayer connection of the multilayer wiring board, a thermal shock test is performed as one method. In this test, the change in circuit resistance value is measured by alternately exposing a multilayer wiring board to a low temperature-high temperature environment. During such a low temperature-high temperature cycle, each wiring board material including the film-like insulator repeatedly expands and contracts, so that stress concentrates on the contact interface between the conductive paste (conductive via) and the conductive pattern. As a result, particularly in the vicinity of the contact interface of the conductive paste, stress deterioration may cause disconnection due to interface peeling or a significant increase in connection resistance value, resulting in failure of the thermal shock test.

In any of the multilayer wiring boards of the prior arts 1 and 2, the contact interface between the conductive paste end face and the conductive pattern inner surface in the via hole, which is the most important part particularly for interlayer connection, has a film insulator around it. The contact interface with the conductive pattern is in the same plane. Therefore, in each of the conventional technologies, when the thermal shock test as described above is performed, it is difficult to avoid the concentration of shear stress due to the low temperature-high temperature cycle at the contact interface between the end surface of the conductive paste and the inner surface of the conductive pattern. There is a problem that the heat cycle resistance and connection reliability of the interlayer contact interface portion are lowered.
JP 2000-38464 A JP 2001-24328 A

  The present invention solves the above-mentioned conventional problems, and in particular, improves the thermal cycle resistance of the interlayer contact interface portion between the conductive via and the conductive layer for wiring in the multilayer wiring board and obtains its high connection reliability. An object of the present invention is to provide a circuit wiring board that can be used and a manufacturing method thereof.

  The circuit wiring board of the present invention according to claim 1 includes an insulating substrate, a via hole formed through the insulating substrate, a conductive via formed by filling the via hole with a conductive paste, and the insulation Circuit wiring conductive layers disposed on both sides of the substrate and connected to both end surfaces of the conductive via, respectively, at least one of the two conductive layers being formed in an interlayer contact portion corresponding to the via hole It has a recessed part.

  The present invention according to claim 2 is a circuit wiring board formed by laminating a plurality of wiring board materials including at least one wiring board material having conductive vias for interlayer connection, wherein the wiring board having the conductive vias is provided. The plate material is disposed on at least one surface of the insulating substrate, the via hole formed through the insulating substrate, the conductive via formed by filling the via hole with a conductive paste, and the conductive material. And a conductive layer for circuit wiring connected to the end face of the via, wherein the conductive layer has a recess formed in an interlayer contact portion corresponding to the via hole.

  According to a third aspect of the present invention, in the circuit wiring board according to the first or second aspect, the contact interface between the bottom surface of the concave portion of the conductive layer and the end face of the conductive via is the same as the conductive layer around it. It is deviated from the contact interface with the insulating substrate in the thickness direction of the insulating substrate.

  According to a fourth aspect of the present invention, in the circuit wiring board according to any one of the first to third aspects, the concave portion has a thickness t of the conductive layer and a depth of the concave portion. When d, the depth d is formed in a relationship of 0.5 μm ≦ d ≦ (t−1) μm.

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a circuit wiring board according to the present invention, comprising: forming a wiring conductive layer on at least one surface of an insulating substrate; Forming a via hole exposing the layer, and forming a recess in an interlayer contact portion of the wiring conductive layer, wherein the via hole and the recess are formed by laser irradiation on the insulating substrate and the wiring conductive layer. It is formed by continuous operation processing.

  According to the circuit wiring board of the present invention, since at least one of the conductive layers for circuit wiring respectively disposed on both surfaces of the insulating substrate has the recess corresponding to the via hole, In testing and the like, in particular, the thermal cycle resistance of the contact interface portion between the conductive via and the conductive layer can be improved, and the high connection reliability can be obtained.

  Further, according to the method for manufacturing a circuit wiring board of the present invention, the via hole and the recess can be easily formed by continuous operation processing by laser irradiation, so that the circuit wiring board can be easily manufactured and the manufacturing cost can be improved. It is possible to produce an effect that.

  Hereinafter, an embodiment of a circuit wiring board and a manufacturing method thereof according to the present invention will be described with reference to FIGS. Here, FIG. 1A is a partially cutaway sectional view showing an embodiment of a circuit wiring board according to the present invention, FIG. 1B is a partially enlarged sectional view of FIG. FIG. 3 is a cross-sectional view by process showing a part of the circuit wiring board shown in FIG. 1 in order to explain one embodiment of the method for manufacturing a circuit wiring board according to the present invention.

  First, an embodiment of the circuit wiring board shown in FIG. 1 will be described. The first wiring board material 1 is here located in the lowermost layer, and is a film-like first insulating board 1a, and its The first conductive layer 1b for wiring formed with a desired circuit wiring pattern is provided on one surface (upper surface).

  The second wiring board material 2 laminated on the first wiring board material 1 is a film-like second insulating substrate 2a and a second wiring for wiring having a desired pattern shape formed on one surface (upper surface) thereof. A conductive layer 2b, an adhesive layer 2c provided on the other surface (lower surface) of the second insulating substrate 2a, and a plurality (two locations in the figure) of via holes provided through the second insulating substrate 2a and the adhesive layer 2c. VH2 and conductive vias 2d made of conductive paste filled in the via holes VH2 are provided.

  The second conductive layer 2b has an interlayer contact portion 2bc in a portion (region) where the interlayer connection is planned, and the interlayer contact portion 2bc has a positional relationship corresponding to the via hole VH2 and the conductive via 2d. is there. The interlayer contact portion 2bc is formed with a recess C that opens to the via hole VH2 side, and the internal space of the recess C communicates with the cylindrical space of the via hole VH2 to form a common cylindrical space. ing.

  The shape of the concave portion C is recessed into a shape having a flat circular bottom portion and a cylindrical portion rising at the periphery thereof so as to form a cylindrical space following the cylindrical via hole VH2, for example. The position is shifted so as to move away from the contact interface between the upper surface of the third insulating substrate 3a and the lower surface of the third conductive layer 3b in the thickness direction opposite to the via hole VH2.

  The via hole VH2 and the recess C are formed by, for example, laser irradiation. The laser irradiation in the first step forms a via hole VH2 that drills in the direction of the second conductive layer 2b from the adhesive layer 2c side with a laser output of 30 kHz and 0.09 W, for example, and reaches the lower surface of the interlayer contact portion 2bc. In the subsequent laser irradiation in the second step, the output is increased to 30 kHz and 0.80 W, for example, and the recess C is formed by cutting the lower surface of the interlayer contact portion 2bc. As described above, the via hole VH2 and the concave portion C can be easily formed by continuous operation processing only by changing the laser output.

  Therefore, the conductive via 2d is formed by filling the cylindrical space with the via hole VH2 and the concave portion C with the conductive paste, and one end portion (upper end) of the conductive via 2d is a concave portion of the interlayer contact portion 2bc of the second conductive layer 2b. C is connected to the inner surface. The other end (lower end) of the conductive via 2 d is connected to the upper surface of the first conductive layer 1 b of the first wiring board material 1.

  The third wiring board material 3 laminated on the second wiring board material 2 is, like the second wiring board material 2, a film-like third insulating substrate 3a, and wiring for one surface (upper surface) thereof. A third conductive layer 3b, an adhesive layer 3c on the other surface (lower surface) of the third insulating substrate 3a, a plurality (two in the figure) of via holes VH3 penetrating the second insulating substrate 2a and the adhesive layer 2c, A conductive via 3d made of a conductive paste filled in the via hole VH3 is provided.

  By the way, the structure of the portion related to the interlayer connection means of the third wiring board material 3 will be described with reference to FIG. 1B. The third conductive layer 3b is a portion (region) where the interlayer connection is planned. ) Have an interlayer contact portion 3bc in a positional relationship corresponding to the via hole VH3 and the conductive via 3d. The interlayer contact portion 3bc is formed with a recess C that opens to the via hole VH3 side, and the internal space of the recess C communicates with the cylindrical space of the via hole VH3 to form a common cylindrical space. ing.

  The concave portion C formed in the interlayer contact portion 3bc has a shape having a flat circular bottom surface portion and a cylindrical portion rising on the periphery thereof, like the concave portion C formed in the interlayer contact portion 2bc of the second conductive layer 2b. The bottom surface of the recess C is recessed from the contact interface between the upper surface of the third insulating substrate 3a and the lower surface of the third conductive layer 3b in the thickness direction away from the via hole VH3. The position is deviated. The configuration of the third wiring board material 3 will be described in more detail with reference to the process diagrams shown in FIG. 2A to FIG.

  Then, the laminated circuit wiring board is stacked by aligning the first to third wiring board materials 1 to 3 in this order, and thermally cured by, for example, batch heating or pressing in vacuum or reduced pressure. Each wiring board material is bonded and integrated by 2c and 3c.

  Further, the lower end surface of the conductive via 2d of the second wiring board material 2 is on the upper surface of the interlayer contact portion 1bc of the first conductive layer 1b of the first wiring board material 1, and the conductive via 3d of the third wiring board material 3 is formed. The lower end surface is connected to the upper surface of the interlayer contact portion 2bc of the second conductive layer 2b of the second wiring board material 2, whereby the interlayer connection by the conductive vias 2d and 3d is achieved.

  By the way, as for the said 1st-3rd wiring board materials 1-3, as a starting material, the base material for copper board | substrates with a single-sided copper foil as shown to Fig.2 (a copper foil thickness of 12 micrometers and polyimide resin thickness) A product type MC12-25-00CEM) manufactured by Nippon Steel Chemical Co., Ltd. having a thickness of 25 μm is used.

  According to such an embodiment, one end portions (upper end portions) of the respective conductive vias 2d and 3d provided in the second and third wiring board materials 2 and 3 are formed on the second and third conductive layers 2b. 3b is in close contact with the bottom surface and the side surface of each recess C. Therefore, the contact area between the conductive vias 2d and 3d and the inner surface of the concave portion C of the conductive layers 2b and 3b is larger than that in the prior art, and an interlayer connection configuration with reduced contact resistance and connection resistance can be obtained. .

  1B, the contact interface between the bottom surface of the recess C formed in the third conductive layer 3b and one end surface (upper end surface) of the conductive via 3d is the third insulating substrate. 3a and the third conductive layer 3b are offset from the contact interface corresponding to the depth d of the recess C, so that concentration of shear stress due to the low temperature-high temperature cycle in the thermal shock test is avoided. Therefore, the heat cycle resistance and connection reliability of the interlayer contact interface portion are improved. In FIG. 1B, the thickness t of the third conductive layer 3b is expressed as the material thickness of the copper foil, and the depth d of the concave portion C is expressed as the dimension from the opening end surface to the bottom surface. Yes.

  By the way, as indicated by a broken line in FIG. 1B, the same concave portion CX is formed on the upper surface of the second conductive layer 2b, and the lower end portion of the conductive via 3d connected to the third conductive layer 3b is The inner surface of the recess CX may be brought into close contact with each other, and in this case, the interlayer connection resistance can be further reduced.

  In the laminated circuit wiring board according to this embodiment, the second and third wiring board materials 2 and 3 constituting two wiring board materials having conductive vias on the first wiring board material 1 having no conductive vias. However, the number of wiring board materials having conductive vias may be one or three or more. That is, at least one wiring board material having conductive vias may be laminated on an arbitrary wiring board material.

  Moreover, although the said 1st wiring board material 1 is made into the single-sided wiring board structure, it is good also as a double-sided wiring board structure. And when the said 1st wiring board material 1 is made into the double-sided wiring board structure, the other side formed similarly to the said 2nd and 3rd wiring board materials 2 and 3 on the opposite surface of the said 1st wiring board material 1 A wiring board material may be laminated. In this case, the first wiring board material 1 can be provided with a conductive via or used as a core board.

  An embodiment of the method for manufacturing the laminated circuit wiring board will be described with reference to FIG. First, the manufacturing process of the third wiring board 3 shown in FIGS. 2A to 2F will be described. As shown in FIG. 2A, for example, a film-like third insulating substrate made of polyimide resin. A substrate X for a wiring board material with a single-sided copper foil provided with a metal conductive layer 3B made of, for example, copper foil on one surface (upper surface) of 3a is prepared as a starting material. Here, product type name MC12-25-00CEM manufactured by Nippon Steel Chemical Co., Ltd. having a copper foil thickness of 12 μm and a polyimide resin thickness of 25 μm was used as the substrate X for wiring board material.

  Next, in the step of FIG. 2B, the metal conductive layer 3B is etched by a subtractive method to form a third conductive layer 3b for wiring having a circuit wiring pattern on the upper surface of the third insulating substrate 3a. To do.

  In the step of FIG. 2C, an adhesive layer having a thickness of, for example, 25 μm is formed by bonding, for example, an epoxy adhesive to the other surface (lower surface or back surface) of the third insulating substrate 3a by heating and pressing in vacuum. 3c is formed. As the epoxy adhesive, for example, product type name SAFD 25 μm manufactured by Nikkan Kogyo Co., Ltd. was used.

  In the step of FIG. 2D, the via hole VH3 penetrating both the third insulating substrate 3a and the adhesive layer 3c in a superposed and bonded state is formed as a cylindrical through hole having a diameter of 100 μm, for example. The via hole VH3 is formed by, for example, drilling in the direction from the adhesive layer 3c toward the third conductive layer with an output of 30 kHz and 0.09 W as a first step using a UV-YAG laser. The perforation depth is the same as the total thickness of the third insulating substrate 3a and the adhesive layer 3c, and the depth is such that the interlayer contact portion 3bc of the third conductive layer 3b is just exposed in the via hole VH3. The Therefore, as a result, the via hole VH3 has a shape in which one end is closed by the third conductive layer 3b and the other end is opened, and has a so-called bottomed opening shape.

  Next, in the process of FIG. 2E, as a second step subsequent to the first step of the UV-YAG laser, the laser output is increased and exposed to the via hole VH3 with outputs of 30 kHz and 0.80 W. Further, the recess C is formed by cutting the surface of the interlayer contact portion 3bc of the third conductive layer 3b.

  The concave portion C is recessed into a shape having a flat circular bottom surface portion and a cylindrical portion rising on the periphery thereof so as to form a common cylindrical space following the via hole VH3. The position is deviated from the contact interface between the upper surface of the third insulating substrate 3a and the lower surface of the third conductive layer 3b so as to move away from the via hole VH3 in the thickness direction. Further, the depth d of the concave portion C is within a range of 0 to 11 μm by controlling the number of irradiation pulses because the cutting amount of the third conductive layer 3b (copper foil) is substantially proportional to the number of laser irradiation pulses. Is controlled. After this process, cleaning is performed, for example, by plasma smearing.

  Thereafter, in the step of FIG. 2 (f), the via hole VH3 constituting the common cylindrical space and the recess C are filled with a conductive paste by, for example, screen printing, thereby filling the interlayer space. A cylindrical conductive via 3d for connection is formed. The third wiring board material is manufactured through such a process. The conductive via 3d has one end face (upper end face) having a wide area over the bottom surface and the peripheral wall surface of the recess C of the interlayer contact portion 3bc. The other end face is exposed outside the via hole VH3 so as to be connected to the conductive layer of another wiring board material. Accordingly, the contact interface between the bottom surface of the recess C of the interlayer contact portion 3bc of the third conductive layer 3b and the upper end surface of the conductive via 3d is relative to the contact interface between the third insulating substrate 3a and the third conductive layer 3b. It is deviated above the surface of the third insulating substrate 3a.

  As will be described later, in order to increase the connection strength when a plurality of wiring board materials are stacked and interlayer connection is made with each conductive via, the surface of the adhesive layer 3c is slightly increased by increasing the column height of the conductive via 3d. The column height may be adjusted to protrude from the wall. In that case, for example, in the process of FIG. 2 (c), the process after FIG. 2 (d) is carried out with a resin film (not shown) having a desired thickness provided on the lower surface of the adhesive layer 3c. After filling the conductive paste of (f), the resin film is peeled off. Although not shown after the resin film is peeled off, the lower end of the conductive via 3d protrudes from the lower surface of the adhesive layer 3c by the thickness of the resin film.

  By the way, the conductive paste is obtained by mixing a thermosetting resin adhesive with particles or powders of a high conductive metal such as silver or copper and a low melting point metal such as tin. A metal material to be mixed is selected so as to form an alloy with the conductive layer 3b (copper foil) to obtain good electrical conduction. As the conductive paste, a thermosetting resin adhesive mixed with particles or powders of highly conductive metals such as silver and copper may be used. However, as described above, tin that easily diffuses into copper is further added. Mixing can promote alloying. In the process up to the step shown in FIG. 2F, the conductive paste 3d and the adhesive layer 3c are in an uncured or semi-cured state.

  2G, first, in addition to the third wiring board material 3, a first wiring board material 1 and a second wiring board material 2 are prepared, and these first to third wiring board materials 1 to 3 are prepared. Are sequentially stacked in this order. Since the first wiring board material 1 is located in the lowermost layer, in this example, the first wiring board material 1 is patterned with a desired circuit wiring pattern on the upper surface of the first insulating board 1a without providing an adhesive layer or a conductive via. The first conductive layer 1b is provided. Of course, an adhesive layer or a conductive via may be provided as necessary.

  The second wiring board material 2 is formed on the inner surface of the second insulating substrate 2a, the second conductive layer 2b for wiring having a desired pattern formed on the upper surface thereof, and the interlayer contact portion 2bc of the second conductive layer 2b. A concave portion C, a via hole VH2 penetratingly formed corresponding to the interlayer contact portion 2bc, and a second conductive via 2d made of a conductive paste filled in a common space extending from the via hole VH2 to the concave portion C are provided. .

  In addition, the second wiring board material 2 is uniquely designed mainly with respect to the pattern shape of the second conductive layer 2b and the formation position of the second conductive via 2d as compared with the third wiring board material 3. It is manufactured through the same steps as those shown in FIGS. 2 (a) to 2 (f). Further, here, the members corresponding to each other of the first to third wiring board members 1 to 3 are made of the same material.

  In the process of FIG. 2 (h), the first to third wiring board materials 1 to 3 laminated in alignment with each other as described above are collectively heated and pressed in a vacuum or reduced pressure to obtain a laminated wiring. A substrate is produced. In the heating press, the lower end surface of the second conductive via 2d is on the upper surface of the interlayer contact portion of the first conductive layer 1b, and the lower end surface of the third conductive via 3d is on the upper surface of the interlayer contact portion 2bc of the second conductive layer 2b. In the pressed state, the conductive vias 2d and 3d made of a heat-cured conductive paste achieve interlayer connection. In the heating press, the adhesive layers 2c and 3c are also thermally cured to bond and integrate the wiring board materials 1-3.

  Next, a heat resistance reliability test applied to the multilayer wiring board manufactured according to such an embodiment will be described. As an evaluation pattern, a daisy chain circuit in which 100 vias were connected in series was used to measure the resistance value before and after the test and calculate the resistance change rate. Then, as a result of conducting a high temperature standing test for 500 hours under a temperature condition of 150 ° C., the resistance change rate was 10% or less which is an allowable value. Incidentally, according to the prior art of Patent Document 2, the resistance change rate of 10% or less can be maintained for about 100 hours at a temperature condition of 150 ° C., and the resistance change rate increases within a considerably short time, and can be put to practical use. Absent.

  Similarly, the resistance change rate was 10% or less, which is an allowable value, in the result of performing the heat treatment at 260 ° C. for 10 seconds for 3 cycles after leaving for 195 hours at 30 ° C.-60% RH as the solder heat resistance test. Incidentally, the resistance change rate of 10% or less can be maintained in the prior art of Patent Document 2 for about 10 seconds after immersion in the soldering iron, and the resistance change rate increases in a very short time.

  Further, with the solder heat resistance test as a pretreatment, a thermal shock test (low temperature condition: 9 minutes at a temperature of −25 ° C., high temperature condition; 9 minutes at a temperature of + 125 ° C.) is performed over 3000 low temperature-high temperature cycles. The results as shown in 3 were obtained. FIG. 3 shows a recess depth d (μm) for a plurality of types of wiring boards in which various recess depths d (μm) are formed on the conductive layer (copper foil) having a thickness t of 12 μm. The relationship between the number of low temperature-high temperature cycles and the resistance value change rate (%) is shown.

  That is, at the recess depth d = 0 (no recess), the resistance value suddenly increased in less than 1000 cycles, and then a disconnection failure occurred. After this test, the cross-section of the via hole portion of the wiring board with poor disconnection was observed, and as shown in FIG. 4 (a), the wiring conductive layer (copper foil) B on the insulating substrate A and the conductive paste. Space E was observed at the interface with D due to the peeling of the paste. When the recess depth is d ≧ 0.5 μm, the increase in resistance value is remarkably suppressed, and the resistance value change rate is maintained at 20% or less which is an allowable range even when the low temperature-high temperature cycle is about 1000 cycles. When the recess depth d = 1.0 μm, the resistance value change rate is maintained at 20% or less even at about 2000 cycles, and when the recess depth d = 2.0 μm, the resistance value change rate is still 20% or less even after 3000 cycles. Maintained.

  As shown in FIG. 4B, when the concave portion depth d is brought close to the thickness of 12 μm of the conductive layer (copper foil) and the concave portion depth d reaches a depth exceeding 11 μm. The thickness of the recess bottom wall BC, which becomes the interlayer connection portion of the wiring conductive layer (copper foil) B on the insulating substrate A, was too thin, and the recess bottom wall BC was damaged and peeled to cause disconnection failure. At this time, the upper end of the conductive paste D expands the filling range so as to push away the recess bottom wall BC, but the internal pressing force of the paste D decreases with the breakage of the recess bottom wall BC, and the unit in the paste D The density of the conductive particles per volume cannot be increased, and the internal resistance may not be reduced.

  FIG. 5 is a graph showing the resistance value change rate% with respect to the recess depth d (μm). In order to obtain the resistance value change rate% of 20% or less of the allowable range, the recess depth d is 0.5 μm. As described above, it is desired to be in the range of t-1 μm or less. In other words, the formation of the concave portion can reliably exhibit the effects of the invention by adjusting the depth within the range of 0.5 μm ≦ d ≦ (t−1) μm.

  Next, with reference to FIG. 6, another embodiment related to the recess C (see FIG. 1B) formed in the interlayer connection portion of the wiring conductive layer in the multilayer wiring board of the embodiment will be described. explain.

  That is, the concave portion CZ formed in the interlayer contact portion 3bc of the wiring conductive layer 3bz has, for example, a two-step bottom shape of a plurality of steps. In this case, since the bottom surface of the two steps of the recess CZ is displaced from the contact interface between the conductive layer 3bz and the insulating substrate 3a in a direction perpendicular to the surface, the concentration of shear stress in the thermal cycle is increased. Can be avoided. Further, since the depth at the peripheral edge of the recess CZ is shallow and the conductive layer 3bz remains thick, and the area of the thin recess central portion of the conductive layer 3bz is reduced, the conductive layer corresponding to the recess CZ The strength of the portion is maintained, and problems such as breakage of the conductive layer and poor disconnection as shown in FIG. 4B can be avoided.

  Further, the recesses C and CZ can have various shapes such as an ellipse, a rectangle, and a rhombus as well as a circle when viewed in plan.

  By the way, each of the wiring board materials 1 to 3 is formed of a flexible wiring board (FPC) using the polyimide resin or a liquid crystal polymer instead of the polyimide resin or the insulating boards 1a to 3a or a prepreg such as a glass epoxy resin. It can be formed by the rigid wiring board (RPC) used in 3a.

  As the adhesive layers 2c and 3c, various resin adhesives such as polyimide and olefin can be used in addition to epoxy.

  Moreover, as the insulating substrates 1a to 3a, for example, insulating base materials provided with an adhesive function by impregnating a fibrous insulating base material with an adhesive may be used. In this case, the adhesive layers 2c and 3c can be omitted, and the adhesive application step or the adhesive film sticking step can be omitted. Further, the adhesive layers 2c and 3c may be formed by applying an adhesive to an insulating substrate instead of adhering an adhesive film. Therefore, as a technique for adhering a plurality of wiring board materials, any of the above-mentioned adhesive impregnation, adhesion film adhesion, and adhesive application may be used. In the present invention, it can be said that it is an insulating substrate having an adhesive function on at least one surface.

  In addition, the formation of the via hole shown in the step of FIG. 2D can use a CO2 gas laser or an excimer laser in addition to the UV-YAG laser, depending on the type of the base material of each of the wiring board materials 1 to 3. It is. For the formation of the via hole shown in the step of FIG. 2E, it is preferable to use UV-YAG or excimer laser. Further, as means for forming the recess C, the conductive layer (copper foil) is protected by a masking film, and then the conductive layer (copper copper) serving as the bottom of the via holes VH2 and VH3 by a chemical etching solution such as an iron chloride solution is used. A method of etching the interlayer connection portions 2bc and 3bc of the foil) can also be applied.

  As described in the above embodiment, the wiring substrate materials 1 to 3 are laminated and integrated by layering each wiring board material one by one by the same method in addition to the batch lamination method by batch heating press. It is also possible to carry out by various sequential lamination methods.

It is sectional drawing for demonstrating the laminated wiring board which concerns on one Embodiment of this invention, (a) is the partially notched sectional view, (b) is the partially expanded sectional view of (a). It is a figure for demonstrating the manufacturing method of the multilayer wiring board in FIG. 1 which concerns on one Embodiment of this invention, (a)-(h) is sectional drawing according to a manufacturing process. It is a graph which shows the thermal shock test result of the multilayer wiring board which concerns on one Embodiment of this invention. It is principal part sectional drawing for demonstrating the interlayer connection state in the relationship between the thickness t of the wiring conductive layer of the laminated wiring board which concerns on one Embodiment of this invention, and the recessed part depth d. It is a graph which shows the resistance value change rate in the relationship between the thickness t of the conductive layer for wiring of the laminated wiring board which concerns on one Embodiment of this invention, and the recessed part depth d. It is sectional drawing which shows other embodiment of the recessed part provided in the conductive layer for wiring of the multilayer wiring board of this invention.

Explanation of symbols

1-3 1st-3rd wiring board base materials 1a-3a, A Insulation board 1b-3b, 3by, 3bz Conductive layer 1bc-3bc, BC Interlayer contact part 2c, 3c Adhesive layer 2d, 3d, D Conductive via (conductive Sex paste)
C, CX, CZ Recessed VH, VH2, VH3 Via hole

Claims (5)

  An insulating substrate, a via hole formed through the insulating substrate, a conductive via formed by filling the via hole with a conductive paste, and disposed on both sides of the insulating substrate, on both end surfaces of the conductive via A circuit wiring board comprising: a conductive layer for circuit wiring connected to each other, wherein at least one of the two conductive layers has a recess formed in an interlayer contact portion corresponding to the via hole.   A circuit wiring board formed by laminating a plurality of wiring board materials including at least one wiring board material having conductive vias for interlayer connection, wherein the wiring board material having conductive vias includes an insulating substrate and the insulating substrate. A circuit board connected to an end face of the conductive via disposed on at least one surface of the insulating substrate, a via hole formed by penetrating through the conductive substrate, a conductive via formed by filling the via hole with a conductive paste, and A laminated circuit wiring board, wherein the conductive layer has a recess formed in an interlayer contact portion corresponding to the via hole.   The contact interface between the bottom surface of the concave portion of the conductive layer and the end surface of the conductive via is deviated in the thickness direction of the insulating substrate from the contact interface between the conductive layer and the insulating substrate around it. The circuit wiring board according to claim 1 or 2.   The recess is formed such that the depth d is 0.5 μm ≦ d ≦ (t−1) μm, where t is the thickness of the conductive layer and d is the depth of the recess. The circuit wiring board according to any one of claims 1 to 3, wherein the circuit wiring board is any one of claims 1 to 3.   Forming a conductive layer for wiring on at least one surface of the insulating substrate; forming a via hole penetrating an interlayer connection scheduled portion of the insulating substrate to expose the conductive layer for wiring; and Forming a recess in the interlayer contact portion, and forming the via hole and the recess is formed by continuous operation processing by laser irradiation on the insulating substrate and the conductive layer for wiring. Method.

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