JP2009054621A - Mulilayer wiring board - Google Patents

Mulilayer wiring board Download PDF

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JP2009054621A
JP2009054621A JP2007217041A JP2007217041A JP2009054621A JP 2009054621 A JP2009054621 A JP 2009054621A JP 2007217041 A JP2007217041 A JP 2007217041A JP 2007217041 A JP2007217041 A JP 2007217041A JP 2009054621 A JP2009054621 A JP 2009054621A
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layer
substrate
resin base
mpa
resin
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Toru Okazaki
亨 岡崎
Hideo Suzuki
秀生 鈴木
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Panasonic Corp
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Panasonic Corp
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Priority to CN2008101459974A priority patent/CN101374391B/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board capable of reducing its warpage in reflow soldering even if a space for forming a dummy pattern is not enough. <P>SOLUTION: The multilayer wiring board 100 includes first to nth wiring layers made of a copper wiring 101 and a resin 103, and resin layer first to (n-1)th layers made of a reinforced fiber bundle 102 and a resin 103. The wiring board 100 has a structure in which at least one of the resin base material layers is allowed to have an equivalent longitudinal elastic modulus and an equivalent linear expansion coefficient different from those of the other layers, the sum of bending moment at a unit temperature change as a drive force of warpage in reflow soldering is smaller than a value C (MPa×mm<SP>2</SP>×°C<SP>-1</SP>) determined by the limit amount of board warpage capable of mounting an electronic component to be mounted on the board. Thus, the warpage of the board can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、電子部品を実装する、2層以上の配線層からなる多層配線基板に関するものである。   The present invention relates to a multilayer wiring board composed of two or more wiring layers on which electronic components are mounted.

多層配線基板は、複雑な電子回路を高密度に構成して、その上に種々の電子部品を高密度に実装することを目的とした、銅と樹脂で構成される配線層と、樹脂と強化繊維束で構成される樹脂基材層とを交互に重ね合わせた構造の電子機器用部材であり、様々なデジタル機器、モバイル機器に多用されている。   The multilayer wiring board is composed of copper and resin, and is reinforced with a resin layer for the purpose of constructing complex electronic circuits with high density and mounting various electronic components on it with high density. This is a member for electronic devices having a structure in which resin base material layers composed of fiber bundles are alternately stacked, and is widely used in various digital devices and mobile devices.

まずは、一般的な多層配線基板の構造について説明する。図6は、n層の配線層とその層間に(n−1)層の樹脂基材層をもつ従来の多層配線基板200(以下、基板200と記す)の構成を示した図である。この基板200は、図6にも示したように一般に配線層104(銅配線101と樹脂103で構成)と樹脂基材層105(強化繊維束102と樹脂103で構成)で形成されている。この基板200は、リフローはんだ付け工程において、リフローベルトあるいはリフローパレットに、実装部品とともに配置され、常温から220℃以上に昇温してはんだ付けされ、その後再び常温に降温される。このとき基板200には、配線層104を構成する銅と樹脂との含有量で決まる2種類の係数、つまり各々の配線層104の平均的な剛性を示す等価縦弾性係数と、単位温度変化に対する平均的な膨張率を示す等価線膨張係数との差により生じる曲げモーメントが駆動力となって反りが生じる。このリフローはんだ付け工程時の基板の反りが生じたままの状態で電子部品を実装すると、電子部品と基板との間の接続信頼性を著しく低下させることとなり、このことが業界の品質問題として指摘されている。   First, the structure of a general multilayer wiring board will be described. FIG. 6 is a diagram showing a configuration of a conventional multilayer wiring substrate 200 (hereinafter referred to as a substrate 200) having n wiring layers and (n-1) resin base material layers between the n wiring layers. As shown in FIG. 6, the substrate 200 is generally formed of a wiring layer 104 (consisting of copper wiring 101 and resin 103) and a resin base layer 105 (comprising reinforcing fiber bundle 102 and resin 103). In the reflow soldering process, the substrate 200 is placed on a reflow belt or a reflow pallet together with the mounted components, heated from room temperature to 220 ° C. or higher and soldered, and then lowered to room temperature again. At this time, the substrate 200 has two types of coefficients determined by the contents of copper and resin constituting the wiring layer 104, that is, an equivalent longitudinal elastic coefficient indicating the average rigidity of each wiring layer 104, and a unit temperature change. The bending moment generated by the difference from the equivalent linear expansion coefficient indicating the average expansion coefficient becomes a driving force and warpage occurs. If an electronic component is mounted with the substrate warped during the reflow soldering process, the connection reliability between the electronic component and the substrate will be significantly reduced, which is pointed out as an industry quality problem. Has been.

以下、リフローはんだ付けをはじめとする熱負荷時における基板反りの駆動力である曲げモーメントについて説明する。   Hereinafter, the bending moment, which is the driving force for the substrate warpage during a thermal load such as reflow soldering, will be described.

図6において、基板200の一方の端面から数えてk番目の配線層(配線層第k層)の厚さをtk(mm)、基板200の積層方向の中点FCから配線層第k層の積層方向の中点fk基板200面内のある方向とその方向に直交する座標軸をx軸、y軸と定義する。次に、配線層第k層の銅と樹脂との含有量で決まり、x軸方向およびy軸方向における平均的な剛性を示す等価縦弾性係数をekx(MPa)、eky(MPa)、単位温度変化に対する平均的な膨張率を示す等価線膨張係数をakx(℃-1)、aky(℃-1)とする。 In FIG. 6, the thickness of the kth wiring layer (wiring layer kth layer) counted from one end face of the substrate 200 is t k (mm), and the wiring layer kth layer from the midpoint FC in the stacking direction of the substrate 200. A direction in the plane of the midpoint fk substrate 200 in the stacking direction and coordinate axes orthogonal to the direction are defined as an x-axis and a y-axis. Next, it is determined by the content of copper and resin in the kth layer of the wiring layer, and the equivalent longitudinal elastic modulus indicating the average stiffness in the x-axis direction and the y-axis direction is expressed by e kx (MPa), e ky (MPa), An equivalent linear expansion coefficient indicating an average expansion coefficient with respect to a unit temperature change is defined as a kx (° C. −1 ) and a ky (° C. −1 ).

従来の基板200では、樹脂基材層の各層において、等価縦弾性係数と等価線膨張係数に差がない種類のものを使用することが一般的であり、こうした基板200では、樹脂基材層105における曲げモーメントは発生しない。   In the conventional substrate 200, it is common to use a type of resin base material layer in which there is no difference between the equivalent longitudinal elastic modulus and the equivalent linear expansion coefficient. In such a substrate 200, the resin base material layer 105 is used. No bending moment occurs at.

したがって、熱負荷時の基板反りの駆動力は、配線層104の各層における残銅率の違いによって生じる曲げモーメントのみで表される。配線層104において生じるx軸方向、y軸方向の単位温度変化時の曲げモーメントをそれぞれMx数4)、(数5)に表す。   Therefore, the driving force of the substrate warp at the time of thermal load is expressed only by the bending moment generated by the difference in the remaining copper ratio in each layer of the wiring layer 104. The bending moments when the unit temperature changes in the x-axis direction and the y-axis direction generated in the wiring layer 104 are expressed by Mx number 4) and (number 5), respectively.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

また、基板200へ電子部品を実装できるようにするためには、次の(数6)、(数7)に示すように、前記曲げモーメントMx(MPa・mm2・℃-1)、My(MPa・mm2・℃-1)を、電子部品を実装できる限界の基板反り量によって決まる値C(MPa・mm2・℃-1)より小さくする必要がある。 Further, in order to make it possible to mount an electronic component on the substrate 200, as shown in the following (Equation 6) and (Equation 7), the bending moment M x (MPa · mm 2 · ° C. −1 ), M y a (MPa · mm 2 · ℃ -1 ), needs to be smaller than a value determined C (MPa · mm 2 · ℃ -1) by the substrate warpage limit that can mount electronic components.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

なお、上記の値C(MPa・mm2・℃-1)は、実験により経験的に得られるものである。例えば、基板の各配線層における残銅率が異なるために、リフローはんだ付け時の反り量が異なる複数種の基板に対して、同一の電子部品を実装した時、基板面内の長さs(mm)の範囲において、基板の反り量がd(mm)より大きい場合は電子部品の実装不良が生じ、前記反り量がd(mm)以下の場合は前記電子部品の実装不良が生じなかったとする。このとき、基板の平均的な剛性を示す等価縦弾性係数をE(MPa)、基板の断面の変形のしやすさを示す断面二次モーメントをI(mm3),基板に電子部品を接合する時のはんだ付け前後における温度変化量をΔT(℃)とすると、上記の値C(MPa・mm2・℃-1)は、

Figure 2009054621
と表される。 The above value C (MPa · mm 2 · ° C. −1 ) is obtained empirically by experiments. For example, when the same electronic component is mounted on a plurality of types of substrates having different warpage amounts during reflow soldering because the remaining copper ratio in each wiring layer of the substrate is different, the length s ( In the range of mm), when the amount of warpage of the substrate is larger than d (mm), mounting failure of the electronic component occurs, and when the amount of warping is less than d (mm), the mounting failure of the electronic component does not occur. . At this time, the equivalent longitudinal elastic modulus indicating the average rigidity of the substrate is E (MPa), the secondary moment of inertia indicating the ease of deformation of the cross section of the substrate is I (mm 3 ), and the electronic component is bonded to the substrate. Assuming that the amount of temperature change before and after soldering is ΔT (° C.), the value C (MPa · mm 2 · ° C. −1 ) is
Figure 2009054621
It is expressed.

従来は、各配線層における残銅率の差に起因する曲げモーメントの発生による基板の反りを抑えるため、特許文献1に示すように、多層配線基板200の配線層104に、電子回路を構成する本来の銅配線ではないダミーパターン106を形成し、残銅率を配線層の各層ともできる限り一律になるよう構成する対策がとられていた。
特開2000−151035号公報(第2−3頁、図1)
Conventionally, as shown in Patent Document 1, an electronic circuit is configured in the wiring layer 104 of the multilayer wiring board 200 in order to suppress the warpage of the board due to the generation of a bending moment due to the difference in the remaining copper ratio in each wiring layer. Measures have been taken to form a dummy pattern 106 that is not the original copper wiring and to make the remaining copper ratio as uniform as possible in each layer of the wiring layer.
Japanese Unexamined Patent Publication No. 2000-151035 (page 2-3, FIG. 1)

しかしながら、特に高密度な電子回路が要求される小型電子機器用の基板に対しては、配線層にダミーパターンを設ける十分なスペースを確保することができず、多層配線基板の反りを低減することが困難であるという課題を有していた。   However, it is not possible to secure a sufficient space for providing a dummy pattern in the wiring layer for a substrate for a small electronic device that requires a particularly high-density electronic circuit, thereby reducing the warpage of the multilayer wiring substrate. Had the problem of being difficult.

本発明は、従来の課題を解決するもので、配線層にダミーパターンを設けるスペースが無い場合でも、反りが低減できる多層配線基板を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring board capable of reducing warpage even when there is no space for providing a dummy pattern in a wiring layer.

上記課題を解決するために、本願の第1請求項に記載の多層配線基板(基板)は、配線層と樹脂基材層が交互に積層され、かつ積層方向の最上面と最下面が前記配線層であり、かつ複数の前記樹脂基材層のうち少なくとも一層の材料が異なる前記樹脂基材層で構成された多層配線基板(以下、基板と記す)であって、次の(数1)と(数2)を満たすものであり、リフローはんだ付けにおける基板反りを低減する。   In order to solve the above-mentioned problem, a multilayer wiring board (substrate) according to the first claim of the present application has a wiring layer and a resin base material layer alternately stacked, and the uppermost surface and the lowermost surface in the stacking direction are the wirings. A multilayer wiring board (hereinafter, referred to as a board) composed of the resin base material layers that are different in at least one layer of the plurality of resin base material layers, and the following (Equation 1): (Equation 2) is satisfied, and substrate warpage in reflow soldering is reduced.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

k(mm):前記基板の一方の端面から数えてk番目の配線層(配線層第k層)の厚さ
k(mm):前記基板の積層方向の中点FCから前記配線層第k層の積層方向の中点fkまでの距離
k(mm):前記基板の一方の端面から数えてk番目の樹脂基材層(樹脂基材層第k層)の厚さ
k(mm):前記中点FCから前記樹脂基材層第k層の積層方向の中点Fkまでの距離
C(MPa・mm2・℃-1):前記基板に電子部品を実装できる限界の基板反り量によって決まる値
kx(MPa)、eky(MPa):前記配線層第k層の銅と樹脂との含有量で決まり、x軸方向およびy軸方向の平均的な剛性を示す等価縦弾性係数
kx(℃-1)、aky(℃-1):前記配線層第k層の銅と樹脂との含有量で決まり、x軸方向およびy軸方向の単位温度変化に対する平均的な膨張率を示す等価線膨張係数
kx(MPa)、Eky(MPa):前記樹脂基材層第k層の樹脂と強化繊維束との含有量で決まる、x軸方向およびy軸方向の等価縦弾性係数
kx(℃-1)、Aky(℃-1):前記樹脂基材層第k層の樹脂と強化繊維束との含有量で決まる、x軸方向およびy軸方向の等価線膨張係数
(前記基板の積層方向と直交する面における直交するx軸およびy軸)
t k (mm): the thickness r k (mm) of the kth wiring layer (wiring layer k-th layer) counted from one end face of the substrate: the wiring layer number from the midpoint FC in the stacking direction of the substrate Distance T k (mm) to the middle point f k in the stacking direction of the k layer: the thickness R k of the k-th resin base layer (resin base layer k-th layer) counted from one end face of the substrate mm): the distance from the midpoint FC to the midpoint F k in the stacking direction of said resin base layer first k layer C (MPa · mm 2 · ℃ -1): substrate limit that can mount electronic components on the substrate Values e kx (MPa) and e ky (MPa) determined by the amount of warpage: Equivalent longitudinal length determined by the content of copper and resin in the kth layer of the wiring layer and indicating average stiffness in the x-axis direction and the y-axis direction Elastic modulus a kx (° C. −1 ), a ky (° C. −1 ): determined by the content of copper and resin in the kth layer of the wiring layer, and the unit of x axis direction and y axis direction. Equivalent linear expansion coefficients E kx (MPa) and E ky (MPa) indicating an average expansion coefficient with respect to the temperature change: x axis determined by the contents of the resin and the reinforcing fiber bundle in the kth layer of the resin base material layer Direction and y-axis direction equivalent longitudinal elastic modulus A kx (° C. −1 ), A ky (° C. −1 ): x axis direction determined by the content of the resin and the reinforcing fiber bundle in the kth layer of the resin base material layer And the equivalent linear expansion coefficient in the y-axis direction (the x-axis and the y-axis orthogonal to each other in the plane orthogonal to the stacking direction of the substrates)

また本願の第2請求項に記載の多層配線基板(基板)は、値C(MPa・mm2・℃-1)は、次の(数3)を満たすものである。 In the multilayer wiring board (substrate) according to the second claim of the present application, the value C (MPa · mm 2 · ° C. −1 ) satisfies the following (Equation 3).

Figure 2009054621
l(mm):前記基板に実装される最大寸法を備えた電子部品の最大寸法
h(mm):前記電子部品と前記基板とを接合するはんだの高さ
E(MPa):前記基板の平均的な剛性を示す等価縦弾性係数
I(mm3):前記基板の断面の変形のしやすさを示す断面二次モーメント
ΔT(℃):電子部品のはんだ付け前後の前記基板の温度変化量
Figure 2009054621
l (mm): Maximum dimension h (mm) of an electronic component having the maximum dimension mounted on the substrate: Solder height E (MPa) for joining the electronic component and the substrate: Average of the substrate Equivalent longitudinal elastic modulus I (mm 3 ) indicating the rigidity: cross-sectional secondary moment ΔT (° C.) indicating the ease of deformation of the cross-section of the substrate: temperature change amount of the substrate before and after soldering of the electronic component

この数式3にて、種々の実装実験により限界の基板反り量を経験的に導くことなく値C(MPa・mm2・℃-1)を求めることが可能となる。 With this mathematical formula 3, it is possible to obtain the value C (MPa · mm 2 · ° C. −1 ) through various mounting experiments without empirically deducing the limit amount of substrate warpage.

以上のように、本発明の多層配線基板(基板)は、樹脂基材層に複数の異なる等価縦弾性係数と等価線膨張係数を持たせて、配線層と樹脂基材層に関する単位温度変化時の曲げモーメントを、前記基板に電子部品を実装できる限界の基板反り量によって決まる値より小さくすることによって、リフローはんだ付けにおける基板反りを低減する効果を有するものである。   As described above, the multilayer wiring board (substrate) of the present invention has a resin base material layer having a plurality of different equivalent longitudinal elastic modulus and equivalent linear expansion coefficient, and changes the unit temperature of the wiring layer and the resin base material layer. By making the bending moment less than a value determined by the limit amount of substrate warp that allows electronic components to be mounted on the substrate, there is an effect of reducing the substrate warp in reflow soldering.

以下、本発明の実施の形態1について、図1と図2を参照しながら説明する。   Hereinafter, Embodiment 1 of the present invention will be described with reference to FIG. 1 and FIG.

(実施の形態1)
図1は、本発明の実施の形態1における多層配線基板100の構成を示した図である。多層配線基板100(以下、基板100と記す)は、下部から順に配線層1、2、…、nまでのn層の配線層を有し、各配線層の間に、下部から順に樹脂基材層1、2、…、(n −1)までの(n −1)層の樹脂基材層を有するものである。また、基板100において、配線層104は銅配線101と樹脂103で形成され、樹脂基材層105は強化繊維束102と樹脂103で形成される。
(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a multilayer wiring board 100 according to Embodiment 1 of the present invention. The multilayer wiring substrate 100 (hereinafter referred to as the substrate 100) has n wiring layers from wiring layers 1, 2,..., N in order from the bottom, and a resin base material in order from the bottom between the wiring layers. Layers 1, 2, ..., (n-1) up to (n-1) resin base material layers are provided. In the substrate 100, the wiring layer 104 is formed of the copper wiring 101 and the resin 103, and the resin base material layer 105 is formed of the reinforcing fiber bundle 102 and the resin 103.

ここで、基板100の一方の端面から数えてk番目の配線層(配線層第k層)の厚さをtk(mm)、基板100の積層方向の中点FCから配線層第k層の積層方向の中点fkまでの距離をrk(mm)、基板100の一方の端面から数えてk番目の樹脂基材層(樹脂基材層第k層)の厚さをTk(mm)、中点FCから樹脂基材層第k層の厚さ方向の中央に位置する中央面Fkまでの距離をRk(mm)とする。 Here, the thickness of the k-th wiring layer (wiring layer k-th layer) counted from one end face of the substrate 100 is t k (mm), and the wiring layer k-th layer from the midpoint FC in the stacking direction of the substrate 100 is set. The distance to the middle point f k in the stacking direction is r k (mm), and the thickness of the k-th resin base layer (resin base layer k-th layer) counted from one end face of the substrate 100 is T k (mm). ), And the distance from the midpoint FC to the center plane F k located at the center in the thickness direction of the resin base material layer k-th layer is R k (mm).

次に、図2(a)は、配線層104の構成を示した図であり、具体的には基板100の一方の端面から数えてk番目の配線層104(配線層第k層)を1層抜き出したものである。図2(b)は、樹脂基材層105の構成を示した図であり、具体的には基板100の一方の端面から数えてk番目の樹脂基材層105(樹脂基材層第k層)を1層抜き出したものである。なお図1では、樹脂基材層第1層の繊維束配向角度と樹脂基材層第2層の繊維束含有率を、他の樹脂基材層第3層〜第(n −1)層と異なるものにし、樹脂基材層第1層と樹脂基材層第2層の等価縦弾性係数と等価線膨張係数が樹脂基材層第3層〜第(n −1)層のそれらと異なる状態を示している。   Next, FIG. 2A is a diagram showing the configuration of the wiring layer 104. Specifically, the k-th wiring layer 104 (wiring layer k-th layer) counted from one end face of the substrate 100 is 1. The layer is extracted. FIG. 2B is a diagram showing the configuration of the resin base material layer 105, specifically, the k-th resin base material layer 105 (resin base material layer k-th layer counted from one end face of the substrate 100). ) Is extracted. In addition, in FIG. 1, the fiber bundle orientation angle of the resin base material layer first layer and the fiber bundle content of the resin base material layer second layer are represented by the other resin base material layer third layer to the (n-1) layer. Different states in which the equivalent longitudinal elastic modulus and the equivalent linear expansion coefficient of the resin base material layer first layer and the resin base material layer second layer are different from those of the resin base material layer third to (n-1) layers. Is shown.

基板面(基板の積層方向と直交する面)内のある方向をx軸、そのx軸に直交する基板面内の座標軸をy軸と定義し、図2(a)において、樹脂103の縦弾性係数をEPP(MPa)、線膨張係数をAPP(℃-1)、銅配線101の縦弾性係数をeCu(MPa)、線膨張係数をaCu(℃-1)、配線層第k層の残銅率をVCuk、配線角度をqk(°)とすると、配線層第k層 におけるx軸,y軸に対する等価縦弾性係数ekx(MPa)、eky(MPa)と等価線膨張係数akx(℃-1)、aky(℃-1)はそれぞれ以下の式で表される。 A certain direction in the substrate surface (surface orthogonal to the substrate stacking direction) is defined as the x axis, and a coordinate axis in the substrate surface orthogonal to the x axis is defined as the y axis. In FIG. The coefficient is E PP (MPa), the linear expansion coefficient is A PP (° C. −1 ), the longitudinal elastic modulus of the copper wiring 101 is e Cu (MPa), the linear expansion coefficient is a Cu (° C. −1 ), and the wiring layer number k When the remaining copper ratio of the layer is V Cuk and the wiring angle is q k (°), the equivalent longitudinal elastic modulus e kx (MPa) and e ky (MPa) with respect to the x-axis and y-axis in the wiring layer k-th layer The expansion coefficients a kx (° C. −1 ) and a ky (° C. −1 ) are respectively expressed by the following equations.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

また、図2(b)において、樹脂103の縦弾性係数をEPP(MPa)、線膨張係数をAPP(℃-1)、強化繊維束102の縦弾性係数をEF (MPa)、線膨張係数をAF(℃-1)、樹脂基材層第k層の繊維束含有率をVFk、繊維束配向角度をQk(°)とすると、樹脂基材層第k層 におけるx軸,y軸に対する等価縦弾性係数Ekx(MPa)、Eky(MPa)と等価線膨張係数Akx(℃-1)、Aky(℃-1)はそれぞれ以下の式で表される。 2B, the longitudinal elastic modulus of the resin 103 is E PP (MPa), the linear expansion coefficient is A PP (° C. −1 ), the longitudinal elastic modulus of the reinforcing fiber bundle 102 is E F (MPa), Assuming that the expansion coefficient is A F (° C. −1 ), the fiber bundle content of the resin base layer k-th layer is V Fk , and the fiber bundle orientation angle is Q k (°), the x axis in the resin base layer k-th layer , Y-axis equivalent longitudinal elastic modulus E kx (MPa), E ky (MPa) and equivalent linear expansion coefficient A kx (° C. −1 ), A ky (° C. −1 ) are respectively expressed by the following equations.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

前述の図6に示す従来の多層配線基板200は、(数13)〜(数16)に示した各樹脂基材層105の等価縦弾性係数と等価線膨張係数に差がなく種類が同じであった。したがって、前記(数4)、(数5)に示す各配線層104における残銅率の違いに起因する単位温度変化時の曲げモーメントMx(MPa・mm2・℃-1)、My(MPa・mm2・℃-1)について、(数6)、(数7)を満たすためには、ダミーパターンの設置による電気回路設計の変更により、各配線層104における残銅率の差を小さくする必要があった。 The conventional multilayer wiring board 200 shown in FIG. 6 described above has the same type with no difference in the equivalent longitudinal elastic modulus and equivalent linear expansion coefficient of each resin base material layer 105 shown in (Equation 13) to (Equation 16). there were. Accordingly, the (number 4), (5) when the unit temperature change due to the difference in copper remaining rate in each wiring layer 104 shown in bending moment M x (MPa · mm 2 · ℃ -1), M y ( for MPa · mm 2 · ℃ -1) , in order to satisfy the equation (6), (7) is by changing the electric circuit design according to the installation of the dummy pattern, reduce the difference between the residual copper rate of the wiring layers 104 There was a need to do.

一方、本発明の基板100は、前記値C(MPa・mm2・℃-1)に対し、樹脂基材層105のうち、少なくとも1層について、繊維束含有率あるいは繊維束配向角度もしくは両者を、他の樹脂基材層105のそれらと異なるものにして、複数種の等価縦弾性係数と等価線膨張係数を有する基板を構成し、かつ、x軸,y軸の各方向について、(数1)、(数2)を満たすものである。 On the other hand, the substrate 100 of the present invention has the fiber bundle content rate or the fiber bundle orientation angle or both for at least one of the resin base layers 105 with respect to the value C (MPa · mm 2 · ° C. −1 ). Different from those of the other resin base material layers 105, a substrate having a plurality of types of equivalent longitudinal elastic modulus and equivalent linear expansion coefficient is formed, and for each of the x-axis and y-axis directions, ) And (Equation 2) are satisfied.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

(数1)、(数2)は、それぞれx軸、y軸に関する、各配線層104と各樹脂基材層105における単位温度変化時の曲げモーメントの和(左辺)と前記値C(右辺)の関係を示す式であり、左辺第1項に示す各配線層104における残銅率の違いに起因する単位温度変化時の曲げモーメントに対し、左辺第2項に示す各樹脂基材層105の等価縦弾性係数と等価線膨張係数の違いに起因する単位温度変化時の曲げモーメントにて打ち消す働きをすることで、(数1)、(数2)を成立させる。これにより、電気回路設計の変更によって(数1)、(数2)の左辺第1項の大きさを小さくさせる必要なく、前記曲げモーメントの総和を小さくさせることができ、簡便に基板の反りを低減する。   (Equation 1) and (Equation 2) are the sum (left side) of the bending moment at the time of unit temperature change in each wiring layer 104 and each resin base layer 105 and the value C (right side) with respect to the x-axis and y-axis, respectively. The relationship between the resin base material layers 105 shown in the second term on the left side with respect to the bending moment when the unit temperature changes due to the difference in the remaining copper ratio in each wiring layer 104 shown in the first term on the left side. (Equation 1) and (Equation 2) are established by canceling out the bending moment when the unit temperature changes due to the difference between the equivalent longitudinal elastic modulus and the equivalent linear expansion coefficient. This makes it possible to reduce the total sum of the bending moments without the need to reduce the size of the first term on the left side of (Equation 1) and (Equation 2) by changing the electrical circuit design. To reduce.

以下に実施の形態1を実現する設計方法の一例を、図4を参照しながら説明する。図4は、本発明の実施の形態1を実現する設計方法の一例を示すフローチャートである。発明目標とする前記値をC1(MPa・mm2・℃-1)とする場合、(数1)、(数2)は以下の等式で表される。 Hereinafter, an example of a design method for realizing the first embodiment will be described with reference to FIG. FIG. 4 is a flowchart showing an example of a design method for realizing the first embodiment of the present invention. When the above-mentioned value targeted for the invention is C 1 (MPa · mm 2 · ° C. −1 ), (Expression 1) and (Expression 2) are expressed by the following equations.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

まず、基板10の設計データを含む基板CAD(Computer Aided Design)から,各配線層の残銅率を抽出する(ステップS1)。   First, the remaining copper ratio of each wiring layer is extracted from a substrate CAD (Computer Aided Design) including design data of the substrate 10 (step S1).

次に、基板CADのx軸,y軸の定義に従い、各配線層の配線方向を判断する(ステップS2)。   Next, the wiring direction of each wiring layer is determined according to the definition of the x-axis and y-axis of the substrate CAD (step S2).

(数9)〜(数12)に示す配線層104の等価縦弾性係数と等価線膨張係数の計算式に、銅配線101と樹脂103の縦弾性係数と線膨張係数、ならびに前記各配線層104の残銅率と配線方向を代入する(ステップS3)。   In the equations for calculating the equivalent longitudinal elastic modulus and equivalent linear expansion coefficient of the wiring layer 104 shown in (Equation 9) to (Equation 12), the longitudinal elastic modulus and the linear expansion coefficient of the copper wiring 101 and the resin 103, and the wiring layers 104. The remaining copper ratio and the wiring direction are substituted (step S3).

次に、(数17)、(数18)に上記で求めた各配線層104の等価縦弾性係数と等価線膨張係数を代入する。このとき、(数17)、(数18)の左辺第1項はともに定数となる。(数17)の左辺第1項を定数Kx1、(数18)の左辺第1項をKy1とする(ステップS4)。 Next, the equivalent longitudinal elastic modulus and the equivalent linear expansion coefficient of each wiring layer 104 obtained above are substituted into (Equation 17) and (Equation 18). At this time, both the first terms on the left side of (Equation 17) and (Equation 18) are constants. The first term on the left side of (Equation 17) is a constant K x1 , and the first term on the left side of ( Equation 18) is K y1 (step S4).

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

樹脂基材層第1層に着目し、(数19)、(数20)を満たすよう、樹脂基材層第1層の繊維束含有率,繊維束配向角度を求めることを考える。(数13)〜(数16)に示す樹脂基材層105の等価縦弾性係数と等価線膨張係数の計算式に、k=2〜(n−1)層の各樹脂基材層105に関する強化繊維束102と樹脂103の縦弾性係数と線膨張係数、ならびに繊維束含有率と繊維束配向角度を代入して計算し(ステップS5)、前記樹脂基材層第1層の厚さT1と前記中点FCから前記樹脂基材層第1層の中点F1までの距離R1とともに(数19)、(数20)に代入すると、(数17)、(数18)は以下のように表される。 Focusing on the first layer of the resin base material layer, consider obtaining the fiber bundle content and the fiber bundle orientation angle of the first layer of the resin base material layer so as to satisfy (Equation 19) and (Equation 20). Reinforcement of the resin base material layer 105 of k = 2 to (n−1) layers in the calculation formulas of the equivalent longitudinal elastic modulus and the equivalent linear expansion coefficient of the resin base material layer 105 shown in (Expression 13) to (Expression 16). The longitudinal elastic modulus and linear expansion coefficient of the fiber bundle 102 and the resin 103, and the fiber bundle content and the fiber bundle orientation angle are substituted and calculated (step S5), and the thickness T 1 of the first layer of the resin base material layer is calculated. Substituting into (Equation 19) and (Equation 20) together with the distance R 1 from the midpoint FC to the midpoint F 1 of the first layer of the resin base material layer, (Equation 17) and (Equation 18) are as follows: It is expressed in

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

ここで、Kx2、Kx3、Ky2、Ky3はそれぞれ、上記の代入計算により算出された定数項である。(数13)〜(数16)より、(数21)、(数22)はともにQ1(°)とVF1を変数にもつ関数式となる。 Here, K x2 , K x3 , K y2 , and K y3 are constant terms calculated by the above substitution calculation. From (Equation 13) to (Equation 16), (Equation 21) and (Equation 22) are both functional expressions having Q 1 (°) and V F1 as variables.

(数21)、(数22)をQ1(°)とVF1に関する連立方程式として解くことにより、(数17)、(数18)を満足する樹脂基材層第1層の繊維束配向角度Q1(°)と繊維束含有率VF1を求めることができる(ステップS6)。本設計方法によれば、基板製造前に、基板CADの設計データを元に実施の形態1を実現する樹脂基材層105の構成を求めることができるため、基板100の試作を繰返し、逐次反り量を評価して設計しなおす必要が無い。 By solving (Equation 21) and (Equation 22) as simultaneous equations concerning Q 1 (°) and V F1 , the fiber bundle orientation angle of the first layer of the resin base material layer satisfying (Equation 17) and (Equation 18) Q 1 (°) and the fiber bundle content V F1 can be obtained (step S6). According to this design method, since the configuration of the resin base material layer 105 that realizes the first embodiment can be obtained based on the design data of the substrate CAD before the substrate is manufactured, the prototype of the substrate 100 is repeated and warped sequentially. There is no need to evaluate and redesign the quantity.

次に、多層配線基板100の樹脂基材層105において、ある1層を他の層と種類が異なるものにすることにより基板の反りが低減する効果の一例を、数値解析シミュレーションにて確認した。図5(a)は、従来の多層配線基板の数理解析シミュレーション結果を示した図であり、図5(b)は、本発明の実施の形態1における多層配線基板の数理解析シミュレーション結果を示した図である。   Next, in the resin base material layer 105 of the multilayer wiring substrate 100, an example of the effect of reducing the warpage of the substrate by making one layer different from the other layer was confirmed by numerical analysis simulation. FIG. 5A is a diagram showing a mathematical analysis simulation result of a conventional multilayer wiring board, and FIG. 5B is a mathematical analysis simulation result of the multilayer wiring board according to Embodiment 1 of the present invention. FIG.

まず、銅配線の縦弾性係数を50000(MPa)、線膨張係数を17×10-6(℃-1)、樹脂の縦弾性係数を8000(MPa)、線膨張係数を60×10-6(℃-1)、強化繊維束の縦弾性係数を70000(MPa)、線膨張係数を5×10-6(℃-1)とする多層配線基板を使い、リフローはんだ付け時の反りシミュレーションを行った結果を示す。図5(a)は、従来構成の多層配線基板であり、配線層の残銅率が基板下面から数えて20%、20%、25%、50%と異なっているのに対し、樹脂基材層の繊維束含有率は全層とも同じ種類のものである。 First, the longitudinal elastic modulus of the copper wiring is 50000 (MPa), the linear expansion coefficient is 17 × 10 −6 (° C. −1 ), the longitudinal elastic modulus of the resin is 8000 (MPa), and the linear expansion coefficient is 60 × 10 −6 ( ° C. -1), 70000 a longitudinal elastic modulus of the reinforcing fiber bundle (MPa), using a multilayer wiring board to the linear expansion coefficient of 5 × 10 -6 (℃ -1) , was warpage simulation during reflow soldering Results are shown. FIG. 5A shows a multilayer wiring board having a conventional configuration, in which the remaining copper ratio of the wiring layer is different from 20%, 20%, 25%, and 50% when counted from the lower surface of the board, whereas the resin base material is shown. The fiber bundle content of the layers is the same for all layers.

一方、図5(b)は、配線層の残銅率が基板下面から数えて20%、20%、25%、50%と異なっているのに対し、基板下面から数えて1番目の樹脂基材層のみ、繊維束含有率を他の樹脂基材層のそれと比べて40%少なく構成した多層配線基板である。図5(a)、(b)の下側は、シミュレーション結果における反り形状を図化したものであるが、図5(a)では、0.283(mm)の反り量を呈しているのに対し、図5(b)は、0.056(mm)の反り量を呈しており、本発明により約80%の反りが低減されていることがわかる。   On the other hand, FIG. 5B shows that the remaining copper ratio of the wiring layer is different from 20%, 20%, 25%, and 50% when counted from the lower surface of the substrate, whereas the first resin group counted from the lower surface of the substrate. Only the material layer is a multilayer wiring board in which the fiber bundle content is 40% less than that of the other resin base material layers. The lower side of FIGS. 5A and 5B is a graph of the warped shape in the simulation results. In FIG. 5A, the warp amount is 0.283 (mm). On the other hand, FIG. 5B shows a warpage amount of 0.056 (mm), and it can be seen that the warpage of about 80% is reduced by the present invention.

ここで、図5(a)の構成を前述の(数1)、(数2)の左辺にあてはめて計算すると次式の(数23)、(数24)の結果となる。   Here, when the calculation shown in FIG. 5A is applied to the left side of the above-described (Equation 1) and (Equation 2), the following equations (Equation 23) and (Equation 24) are obtained.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

同様に、図5(b)の構成を同じ式で計算すると(数25)、(数26)の結果となる。   Similarly, when the configuration of FIG. 5B is calculated by the same formula, the results of (Equation 25) and (Equation 26) are obtained.

Figure 2009054621
Figure 2009054621

Figure 2009054621
Figure 2009054621

本例における前記値Cは1.03×10-5(MPa・mm2・℃-1)であることが経験的にわかっている。これより、図5(a)の構成では(数1)、(数2)を満たさないが、図5(b)の構成では同式を満たし、本発明の多層配線基板100により電子部品の実装ができることがわかる。 The value C in this example is empirically known to be 1.03 × 10 −5 (MPa · mm 2 · ° C. −1 ). 5 (a) does not satisfy (Equation 1) and (Equation 2), but the configuration of FIG. 5 (b) satisfies the same equation, and the multilayer wiring board 100 of the present invention mounts electronic components. You can see that

なお、ここでは述べなかったが、樹脂基材層の少なくとも1層について、繊維束配向角度を変えることによって等価縦弾性係数と等価線膨張係数を変更し、(数1)、(数2)を満足する構成にした基板もリフロー時の基板反り量が低減されることは明らかである。   Although not described here, for at least one of the resin base layers, the equivalent longitudinal elastic modulus and the equivalent linear expansion coefficient are changed by changing the fiber bundle orientation angle, and (Equation 1) and (Equation 2) are changed. It is clear that the substrate warpage at the time of reflow is also reduced in the substrate having a satisfactory configuration.

(実施の形態2)
次に本発明の実施の形態2について、図3を参照しながら説明する。図3は、多層配線基板とそれに実装される電子部品の形状との関係を示した図であり、前記基板100とそれに実装される最大寸法を備えた電子部品107の最大寸法l(mm),前記電子部品と前記基板100とを接合するはんだ108の高さをh(mm)との関係を示している。
(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing the relationship between the multilayer wiring board and the shape of the electronic component mounted thereon, and the maximum dimension l (mm) of the substrate 100 and the electronic component 107 having the maximum dimension mounted thereon, The relationship between the height of the solder 108 for joining the electronic component and the substrate 100 to h (mm) is shown.

ここで、リフローはんだ付け時の基板100の反りにより、部品の最大寸法l(mm)の間ではんだ高さh(mm)を越える反りが生じれば、電子部品と多層配線基板の間の接続信頼性が著しく低下することが知られている。前記最大寸法l(mm)の間ではんだ高さh(mm)の反りが生じるときの多層配線基板の曲率半径をRa(mm)とすると、三平方の定理より、

Figure 2009054621
が導かれる。一方、はり理論式より、単位温度変化時の曲げモーメントN(MPa・mm2・℃-1)が生じる場合の曲率半径Rb(mm)は、前記基板の平均的な剛性を示す等価縦弾性係数をE(MPa)、前記基板の断面の変形のしやすさを示す断面二次モーメントをI(mm3)、温度変化量をΔT(℃)とするとき、
Figure 2009054621
と表される。曲率半径Ra(mm)とRb(mm)は同じものを表すことから、両者を等式で結ぶことにより、
Figure 2009054621
が成立する。前述の(数7)の左辺に示す配線層と樹脂基材層に関する曲げモーメントが(数22)に示すモーメントN(MPa・mm2・℃-1)より大きければ、前記基板は、前記最大寸法l(mm)の間ではんだ高さh(mm)を越える反りを生じることを示すため、請求項1記載の値C(MPa・mm2・℃-1)を、
Figure 2009054621
となる構成とすることで、電子部品と基板の間の接続信頼性を保つことができるまで基板反りを低減することができる。本実施の形態2によれば、従来実施されてきたように、複数種の基板を用いた種々の実験を行う必要なく、簡便に前記値C(MPa・mm2・℃-1)を求めることが可能となる。 If warpage exceeding the solder height h (mm) occurs between the maximum dimensions l (mm) of the component due to warpage of the substrate 100 during reflow soldering, the connection between the electronic component and the multilayer wiring board It is known that reliability is significantly reduced. When the curvature radius of the multilayer wiring board when the warp of the solder height h (mm) occurs between the maximum dimensions l (mm) is R a (mm),
Figure 2009054621
Is guided. On the other hand, the radius of curvature R b (mm) when the bending moment N (MPa · mm 2 · ° C. −1 ) at the time of unit temperature change is calculated from the beam theory equation is equivalent longitudinal elasticity indicating the average rigidity of the substrate. When the coefficient is E (MPa), the cross-sectional secondary moment indicating the ease of deformation of the cross-section of the substrate is I (mm 3 ), and the temperature change is ΔT (° C.),
Figure 2009054621
It is expressed. Since the radii of curvature R a (mm) and R b (mm) represent the same thing,
Figure 2009054621
Is established. If the bending moment related to the wiring layer and the resin base material layer shown on the left side of (Expression 7) is larger than the moment N (MPa · mm 2 · ° C. −1 ) shown in (Expression 22), the substrate has the maximum dimension. In order to show that the warpage exceeding the solder height h (mm) occurs between 1 (mm), the value C (MPa · mm 2 · ° C. −1 ) according to claim 1 is
Figure 2009054621
With this configuration, it is possible to reduce substrate warpage until connection reliability between the electronic component and the substrate can be maintained. According to the second embodiment, the value C (MPa · mm 2 · ° C. −1 ) can be easily obtained without performing various experiments using a plurality of types of substrates, as conventionally performed. Is possible.

本発明の多層配線基板は、樹脂基材層に複数の異なる等価縦弾性係数と等価線膨張係数を持たせ、配線層と樹脂基材層に関する単位温度変化時の曲げモーメントを、前記多層配線基板に電子部品を実装できる限界の基板反り量によって決まる値より小さくすることにより、リフローはんだ付け時の基板反りを低減することができる効果を有し、携帯電子機器をはじめ、デジタルモバイル商品などの電子回路形成のために搭載される多層配線基板といった用途にも適用できる。   The multilayer wiring board of the present invention has a resin base layer having a plurality of different equivalent longitudinal elastic coefficients and equivalent linear expansion coefficients, and the bending moment at the time of unit temperature change with respect to the wiring layer and the resin base layer is determined by the multilayer wiring board. By making it smaller than the value determined by the limit of the amount of board warpage that can mount electronic components on the board, it has the effect of reducing board warpage during reflow soldering. It can also be applied to uses such as multilayer wiring boards mounted for circuit formation.

本発明の実施の形態1に関わる多層配線基板の構成を説明するための図The figure for demonstrating the structure of the multilayer wiring board in connection with Embodiment 1 of this invention. (a)配線層の構成を示した図、(b)樹脂基材層の構成を示した図(A) The figure which showed the structure of the wiring layer, (b) The figure which showed the structure of the resin base material layer 本発明の実施の形態2に関わる、多層配線基板とそれに実装される電子部品の形状との関係を示した図The figure which showed the relationship between the multilayer wiring board in connection with Embodiment 2 of this invention, and the shape of the electronic component mounted on it 本発明の実施の形態1を実現する設計方法の一例を示すフローチャートThe flowchart which shows an example of the design method which implement | achieves Embodiment 1 of this invention. (a)従来の多層配線基板の数理解析シミュレーション結果を示した図、(b)本発明の実施の形態1における多層配線基板の数理解析シミュレーション結果を示した図(A) The figure which showed the mathematical analysis simulation result of the conventional multilayer wiring board, (b) The figure which showed the mathematical analysis simulation result of the multilayer wiring board in Embodiment 1 of this invention 従来の多層配線基板の構成を示した図Diagram showing the configuration of a conventional multilayer wiring board

符号の説明Explanation of symbols

100 多層配線基板
101 銅配線
102 強化繊維束
103 樹脂
104 配線層
105 樹脂基材層
106 ダミーパターン
107 電子部品
108 はんだ
200 従来の多層配線基板
DESCRIPTION OF SYMBOLS 100 Multilayer wiring board 101 Copper wiring 102 Reinforcing fiber bundle 103 Resin 104 Wiring layer 105 Resin base layer 106 Dummy pattern 107 Electronic component 108 Solder 200 Conventional multilayer wiring board

Claims (2)

配線層と樹脂基材層が交互に積層され、かつ積層方向の最上面と最下面が前記配線層であり、かつ複数の前記樹脂基材層のうち少なくとも一層の材料が異なる前記樹脂基材層で構成された多層配線基板(以下、基板と記す)であって、次の(数1)と(数2)を満たすものであることを特徴とする多層配線基板。
Figure 2009054621
Figure 2009054621
k(mm):前記基板の一方の端面から数えてk番目の配線層(配線層第k層)の厚さ
k(mm):前記基板の積層方向の中点FCから前記配線層第k層の積層方向の中点fkまでの距離
k(mm):前記基板の一方の端面から数えてk番目の樹脂基材層(樹脂基材層第k層)の厚さ
k(mm):前記中点FCから前記樹脂基材層第k層の積層方向の中点Fkまでの距離C(MPa・mm2・℃-1):前記基板に電子部品を実装できる限界の基板反り量によって決まる値
kx(MPa)、eky(MPa):前記配線層第k層の銅と樹脂との含有量で決まり、x軸方向およびy軸方向の平均的な剛性を示す等価縦弾性係数
kx(℃-1)、aky(℃-1):前記配線層第k層の銅と樹脂との含有量で決まり、x軸方向およびy軸方向の単位温度変化に対する平均的な膨張率を示す等価線膨張係数
kx(MPa)、Eky(MPa):前記樹脂基材層第k層の樹脂と強化繊維束との含有量で決まる、x軸方向およびy軸方向の等価縦弾性係数
kx(℃-1)、Aky(℃-1):前記樹脂基材層第k層の樹脂と強化繊維束との含有量で決まる、x軸方向およびy軸方向の等価線膨張係数
(前記基板の積層方向と直交する面における直交するx軸およびy軸)
The resin base material layer in which the wiring layers and the resin base material layers are alternately laminated, the uppermost surface and the lowermost surface in the stacking direction are the wiring layers, and at least one material of the plurality of resin base material layers is different. A multilayer wiring board (hereinafter, referred to as a substrate) configured by the following (Formula 1) and (Formula 2):
Figure 2009054621
Figure 2009054621
t k (mm): the thickness r k (mm) of the kth wiring layer (wiring layer k-th layer) counted from one end face of the substrate: the wiring layer number from the midpoint FC in the stacking direction of the substrate Distance T k (mm) to the middle point f k in the stacking direction of the k layer: the thickness R k of the k-th resin base layer (resin base layer k-th layer) counted from one end face of the substrate mm): the distance from the midpoint FC to the midpoint F k in the stacking direction of said resin base layer first k layer C (MPa · mm 2 · ℃ -1): substrate limit that can mount electronic components on the substrate Values e kx (MPa) and e ky (MPa) determined by the amount of warpage: Equivalent longitudinal length determined by the content of copper and resin in the kth layer of the wiring layer and indicating average stiffness in the x-axis direction and the y-axis direction Elastic modulus a kx (° C. −1 ), a ky (° C. −1 ): determined by the content of copper and resin in the kth layer of the wiring layer, and the unit of x axis direction and y axis direction. Equivalent linear expansion coefficients E kx (MPa) and E ky (MPa) indicating an average expansion coefficient with respect to the temperature change: x axis determined by the contents of the resin and the reinforcing fiber bundle in the kth layer of the resin base material layer Direction and y-axis direction equivalent longitudinal elastic modulus A kx (° C. −1 ), A ky (° C. −1 ): x axis direction determined by the content of the resin and the reinforcing fiber bundle in the kth layer of the resin base material layer And the equivalent linear expansion coefficient in the y-axis direction (the x-axis and the y-axis orthogonal to each other in the plane orthogonal to the stacking direction of the substrates)
値C(MPa・mm2・℃-1)は、次の(数3)を満たすものであることを特徴とする請求項1に記載の多層配線基板。
Figure 2009054621
l(mm):前記基板に実装される最大寸法を備えた電子部品の最大寸法
h(mm):前記電子部品と前記基板とを接合するはんだの高さ
E(MPa):前記基板の平均的な剛性を示す等価縦弾性係数
I(mm3):前記基板の断面の変形のしやすさを示す断面二次モーメント
ΔT(℃):電子部品のはんだ付け前後の前記基板の温度変化量
The multilayer wiring board according to claim 1, wherein the value C (MPa · mm 2 · ° C. −1 ) satisfies the following (Equation 3).
Figure 2009054621
l (mm): Maximum dimension h (mm) of an electronic component having the maximum dimension mounted on the substrate: Solder height E (MPa) for joining the electronic component and the substrate: Average of the substrate Equivalent longitudinal elastic modulus I (mm 3 ) indicating the rigidity: cross-sectional secondary moment ΔT (° C.) indicating the ease of deformation of the cross-section of the substrate: temperature change amount of the substrate before and after soldering of the electronic component
JP2007217041A 2007-08-23 2007-08-23 Mulilayer wiring board Pending JP2009054621A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010272570A (en) * 2009-05-19 2010-12-02 Panasonic Corp Multilayer wiring board
KR101053141B1 (en) 2009-06-08 2011-08-02 서울과학기술대학교 산학협력단 Dummy pattern design method to suppress warpage of printed circuit board

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CN104302097B (en) * 2014-10-16 2017-07-21 深圳市华星光电技术有限公司 A kind of multilayer board
CN104470251A (en) * 2014-10-31 2015-03-25 镇江华印电路板有限公司 Manufacturing method of soft and hard combined board
JP6581886B2 (en) * 2015-11-24 2019-09-25 スタンレー電気株式会社 Semiconductor device

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TWI242398B (en) * 2000-06-14 2005-10-21 Matsushita Electric Ind Co Ltd Printed circuit board and method of manufacturing the same
KR20090030139A (en) * 2007-09-19 2009-03-24 삼성전기주식회사 Multi-layer printed circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010272570A (en) * 2009-05-19 2010-12-02 Panasonic Corp Multilayer wiring board
US8344260B2 (en) 2009-05-19 2013-01-01 Panasonic Corporation Multilayer wiring board
KR101053141B1 (en) 2009-06-08 2011-08-02 서울과학기술대학교 산학협력단 Dummy pattern design method to suppress warpage of printed circuit board

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