JP2011159870A - Design condition calculating device, optimizing method for warpage and stress of board, and optimization program for warpage and stress of board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To calculate design condition, when an electronic component is to be solder-bonded to the surface of a printed board. <P>SOLUTION: A design condition calculation device includes a data import section 21 for importing at least shape data and arranged data of the printed board and the electronic component sent from an input device 1; a model-generating section 22 for generating model data of the printed board, by adding material characteristic value to each of the data imported by the data import section 21; a warpage direction calculating section 23 for calculating the warpage direction of the printed board, based on the model data generated by the model generating section 22; a warpage stress calculating section 24 for calculating the warpage amount of the printed board and the stress of the solder bonded position, based on the model data generated by the model generating section 22; and an optimization section 25 for calculating designing conditions with which the balance between the warpage amount of the printed board calculated by the warpage calculating section 24 in the warpage direction of the printed board calculated by the warpage direction calculating section 23 and the stress of the solder bonded position can be maintained at an optimal balance. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a design condition calculation apparatus, a substrate warpage and stress optimization method, and a substrate warpage and stress optimization program. In particular, the present invention relates to a design condition calculation apparatus for calculating a design condition for soldering an electronic component to the surface of a printed circuit board, a method for optimizing the warpage and stress of the board, and a program for optimizing the warpage and stress of the board.

  In recent years, electronic devices are rapidly becoming lighter, thinner, shorter, and smaller. Accordingly, it is necessary to make the electronic component and the printed wiring board on which the electronic component is mounted thinner. However, as components and substrates become thinner, bending rigidity decreases, and an increase in warpage is a major issue. In addition, breaking and peeling due to stress are still a big problem even if it becomes thin.

  The problem of warpage and stress is a big problem for electronic devices. First, if warpage occurs above a threshold value in the reflow process, the printed wiring board and the electrodes of the electronic device are not electrically connected to each other by solder, or are joined in an incomplete state (unfused). If it is not completely connected, it can be found by electrical inspection after reflow, but there is a problem that the yield decreases. If it is not fused, it will be recalled after shipment, and the damage amount will be enormous. Furthermore, even if the connection is complete, if warping remains after reflow, it is difficult to incorporate the electronic device into the housing, and the yield is reduced here. In this way, warping is a major enemy for electronic devices that are remarkably thin. On the other hand, with regard to stress, the warpage of the printed wiring board will occur if it is corrected to be flat by a method called hot press, etc., and if the residual stress is generated in the solder part, the solder connection expected at the time of design There arises a problem that the lifetime is significantly shorter than the lifetime. As described above, for electronic devices, warping and stress are major issues that must be solved simultaneously.

  In order to solve these problems, it is necessary to find an optimum structure capable of suppressing the occurrence of warpage and reducing the stress. However, according to the studies conducted so far, there is a trade-off relationship between warpage and stress. When stress is reduced, warpage increases. Conversely, when warpage is reduced, stress (in this case, in-plane The result that stress is dominant) has been published in Non-Patent Document 1 and the like, and there was a problem that it was very difficult to reduce both at the same time. In such background technology, in order to predict and reduce warpage and stress at the design stage, attempts have been made to quantitatively and highly accurately predict warpage behavior when mounting electronic components on a printed circuit board. Related companies, universities, research institutes, and the like conduct research using a prediction technique based on simulation using a finite element method (FEM (Finite Element Method)) and multilayer beam theory. A system based on the multilayer beam theory of Patent Document 1 has been developed, and in Non-Patent Document 2, investigations have been made to obtain an optimal value of warpage using this system.

JP 2006-278803 A

J. Oda, “Evaluation of Stress and Deformation of Printed Circuit Boards by Multilayer Beam Theory”, Nippon Mechanics Journal. Volume A, Japan Society of Mechanical Engineers, July 25, 1993, Vol. 59, No. 563, p. 203-208 Ichiro Hirata, “Development of warpage stress calculation tool for multilayer substrate and investigation of cause of stress minimum value”, Electronics Packaging Conference Lecture Collection, Japan Institute of Electronics Packaging, April 20, 2005, Vol. 19, p. 93-94

  According to the warpage stress calculation tool for a multilayer substrate described in Non-Patent Document 2, the focus is on minimizing warpage, and the results of stress are also being studied. However, in Non-Patent Document 2, it has not yet been possible to optimize warpage and stress at the same time. Further, even in research using FEM, it is difficult to change the dimensions of a model in which elements are divided, and it is necessary to change the model repeatedly for optimization. Further, when theoretically examining the relationship between warpage and stress from the multi-layered beam theory, it is necessary to reduce the curvature of the substrate (increase the bending rigidity) to reduce the warp according to Equation (11) of Non-Patent Document 1. However, reducing the curvature results in an increase in stress, so the trade-off relationship between warpage and stress is fundamental due to the generation mechanism, and it may be difficult to reduce both at the same time. I can guess.

  In order to solve the above-described problem, according to the first aspect of the present invention, there is provided a design condition calculation system for calculating a design condition when soldering an electronic component to the surface of a printed circuit board, which is sent from an input device. Generate at least the shape data and arrangement data of the printed printed circuit board and the electronic components to be soldered to it, the data acquisition unit to be acquired, and the material characteristic value to each data acquired by the data acquisition unit to generate the model data of the printed circuit board A warp direction calculation unit that calculates a warp direction of the printed circuit board based on the model data generated by the model generation unit, and a warpage amount of the printed circuit board based on the model data generated by the model generation unit. The warp stress calculation unit that calculates the stress of the soldered portion and the warp response in the warp direction of the printed circuit board calculated by the warp direction calculation unit Comprising the amount of warpage of the printed circuit board calculator has calculated, the optimization unit balance between the stress point that is solder bonded to calculate design conditions that may be optimal balance.

  According to the second aspect of the present invention, the first step of designating a component to be examined among the printed wiring board and the electronic component to be soldered thereto, the second step of calculating the warping direction of the substrate, and the examination A third step of determining whether or not an electronic component designated as a target is disposed on the compression side of the substrate; a fourth step of calculating the substrate warpage and the stress of the solder portion; and the calculated maximum stress of the solder portion. Includes a fifth step of determining whether or not the calculated warpage of the substrate is within the threshold, and a seventh step of changing the model.

  According to the third aspect of the present invention, the step of calculating the board direction based on the shape data and the arrangement data of the printed wiring board and the electronic components soldered to the printed circuit board, and the warpage of the board and the solder portion based on the model data. Causing the computer to execute a step of calculating the stress and a step of optimizing based on the calculated result.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  As is clear from the above description, according to the present invention, the design condition can be calculated so that the balance between the warpage of the printed circuit board and the stress of the solder joint portion is optimal, and therefore there is a trade-off relationship. Regarding warpage and stress, by moving an electronic component that requires special attention to the solder connection life to the side where compressive stress is generated, the threshold of stress that affects the connection life is increased, and the warpage can be reduced by increasing the stress to some extent. As a result, it is possible to solve a decrease in yield and a decrease in connection life caused by warpage and stress.

  Further, according to the present invention, the multilayer beam theory is used without using the FEM which requires analysis time, and the design can be performed by using the equivalent elastic modulus, the equivalent thermal expansion coefficient, and the bimetal theory in the warping direction. The problem can be solved quickly at an early stage.

It is a block diagram which shows the 1st Embodiment of this invention. It is a detailed flowchart from the board | substrate curvature direction calculation to optimization of this invention. It is a block diagram which shows the structure of the program of this invention. It is explanatory drawing for producing a 2 layer board | substrate from a multilayer substrate.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 shows an example of a block configuration of the data processing device 2. The data processing device 2 includes a data capturing unit 21, a model generation unit 22, a warp direction calculation unit 23, a warp stress calculation unit 24, and an optimization unit 25.

  The data processing device 2 takes in the shape and arrangement data of the substrate or the electronic component from the input device 1 by the data take-in unit 21, and sets material characteristic values such as applied temperature, elastic modulus E, and thermal expansion coefficient α in the data in the material library or the like. Is selected by the model generation unit 22. Next, the warping direction calculation unit 23 calculates the warping direction of the model, and the optimization unit 25 calculates the amount of warping of the model board and the stress generated in the solder joint portion of the electronic component. Here, the warp direction calculation unit 23 calculates the multi-layer substrate as a bimetal, and the warp stress calculation unit 24 calculates the multi-layer beam theory. Furthermore, based on the calculated substrate warp direction, substrate warp amount, and solder part stress, design conditions (dimension, layer thickness, material characteristics, arrangement, etc.) that can optimize the warp and stress by the optimization unit 25 are calculated. The data processed by the data processing device 2 is stored in the storage device 3 and the result is output by the output device 4.

  Next, the second best mode of the present invention will be described in detail with reference to the drawings. Referring to FIG. 3, the second embodiment of the present invention includes an input device, a data processing device, a storage device, and an output device, as in the first embodiment of the present invention. The warpage direction, warpage amount, and stress calculation program 5 control the processing and operation of data read into the data processing device 2, and the processing results of each processing from the data processing device 2 are stored in the storage device 3. As described above, the data processing device 2 executes the same processing as the processing by the data processing device 2 in the first embodiment under the control of the warping direction and the warpage amount and the stress calculation program 5.

  Next, FIG. 2 shows a detailed flowchart from the warp direction calculation to optimization which is particularly important in the present invention. In the input model data, the process proceeds to a process A1 in which an electronic component that pays particular attention to the solder connection life is specified as an examination target, and the process proceeds to a process A2 in which the warping direction of the printed circuit board on which the electronic component is mounted is calculated. Next, it progresses to process A3 which judges whether the compressive stress has generate | occur | produced in the solder connection part of the component for examination. Here, the stress of the solder joint is not yet calculated, and the surface on which the target component is mounted is a recess (compression side) according to the later-described equivalent elastic modulus, equivalent thermal expansion coefficient, and bimetal warpage formula. Judge by no. If the result is NO, the process proceeds to step A7 for changing the model, and if it is on the compression side, the process proceeds to step A4 for calculating the warpage amount of the substrate and the stress value of the solder portion. Use theory. Next, the process proceeds to a process A5 for determining whether or not the solder part stress calculated in the process A4 is within the threshold value. If not, the process proceeds to the process A7 for changing the model. move on. In step A6 for determining whether the warpage of the substrate is within the threshold value, if not, the process proceeds to step A7 for changing the model, and if it is within the threshold value, the process is terminated.

ここでＥは等価弾性率、Ｅ１、Ｅ２、Ｅ３、はそれぞれ各層の弾性率、また、Ｖ１、Ｖ２、Ｖ３はそれぞれの層の体積である。このような方法を用いれば、多層のプリント配線基板であっても２層として扱うことができるようになるが、あくまでも等価な値であり、基板の反りの向きを短時間に求める目的で使用している。なお、熱膨張係数に対しても同様に等価熱膨張係数が求められる。 Here, an outline of the equivalent elastic modulus and bimetal theory used in step A2 for calculating the warping direction of the substrate will be described. In the printed wiring board, the bimetal type can be used by dividing the divided area into two in an arbitrary thickness direction, replacing each divided area with an equivalent elastic modulus, and considering each layer as one layer.

Here, E is the equivalent elastic modulus, E1, E2, and E3 are the elastic moduli of the respective layers, and V1, V2, and V3 are the volumes of the respective layers. If such a method is used, even a multilayer printed wiring board can be handled as two layers, but it is an equivalent value to the last, and is used for the purpose of obtaining the direction of warping of the board in a short time. ing. Similarly, an equivalent thermal expansion coefficient is obtained for the thermal expansion coefficient.

ここで、Ｅ１、Ｅ２はバイメタルのそれぞれの層の弾性率、ａ１、ａ２はそれぞれの層の厚さ、α１、α２はそれぞれの層の線膨張係数、Ｌはバイメタルの長さ、Ｔ０は初期温度、Ｔ１は最終温度、さらに、ρはプリント配線基板の曲率、Ｗはプリント配線基板のたわみである。図４においては、等価弾性率ＥをＥ１、破線Ａの下部の層３３はＥ２とすればよい。 Next, as bimetal theory, Timoshenko's theory is the strictest, and h = a1 + a2, m = a1 / a2, and n = E1 / E2.

Here, E1 and E2 are the elastic moduli of the respective layers of the bimetal, a1 and a2 are the thicknesses of the respective layers, α1 and α2 are the linear expansion coefficients of the respective layers, L is the length of the bimetal, and T0 is the initial temperature. , T1 is the final temperature, ρ is the curvature of the printed wiring board, and W is the deflection of the printed wiring board. In FIG. 4, the equivalent elastic modulus E may be E1, and the lower layer 33 of the broken line A may be E2.

Furthermore, an outline of the multilayer beam theory described in Non-Patent Document 1 will be described. Consider the case where the n-layer continuous beam is deformed. Think of the thickness of each layer as small as the radius of curvature,

Here, R1, R2,... Are curvature radii of each layer, and R is a representative curvature radius. In addition, the continuous condition of the strain on the bonding surface of the multilayer beam, and the balance formula of the axial force Pi and bending moment Mi generated in each layer are as follows:

Here, {ε} is a strain vector, {P} is an axial force vector, [K] is a stiffness matrix, and y is a neutral point (position of zero stress) in a multilayer beam, and the following relationship is established.

Further, ignoring the elongation of the multi-layer beam (L ′ = L) and letting the deflection generated in the n-layer beam be δ,

  Therefore, the deflection δ can be calculated by calculating the curvature R from the equation (5) and substituting it into the equation (10). By programming this matrix type equation, the warp of the multilayer substrate can be performed without performing the FEM simulation. It can be calculated in a short time, and the stress generated in each layer can be calculated from the displacement. However, when the number of layers increases, the calculation time is short compared with the analysis by FEM, but the burden on the analysis machine increases. One of the features of this patent is that it is equivalent at the stage of determining whether the electronic component under consideration is on the concave side (compressive stress side) or the convex side (tensile stress side) of the printed wiring board. The load on the machine can be greatly reduced by using the equation of elastic modulus, equivalent thermal expansion coefficient, and bimetal warpage.

  As the best mode for carrying out the invention, for example, when a solder layer connecting an electronic component and a printed wiring board is filled with a resin called an underfill for reinforcement, the elastic modulus changes. In such a case, optimization is performed even when a plurality of materials are used in the same layer by calculating the equivalent elastic modulus using Equation (1) for each material in the same layer. There is also an effect that can be done.

  Next, a first embodiment of the present invention will be described with reference to the drawings. This example corresponds to the first embodiment of the present invention. In this embodiment, a keyboard and a mouse are provided as the input device 1, a personal computer is provided as the data processing device 2, a magnetic disk storage device is provided as the storage device 3, and a display is provided as the output device 4. The data acquisition unit 21, the model generation unit 22, the warp direction calculation unit 23, the warp stress calculation unit 24, and the optimization unit 25 are configured. The data acquisition unit 21 captures the shape data and position data of the board, electronic component, and solder from the input device 1, and selects material characteristic values such as Young's modulus E and thermal expansion coefficient α from a material library or the like to generate a model. It is added by the part 22. Next, the calculation is performed by the unit 23 that calculates the warping direction by applying temperature to the substrate model, and the calculation is performed by the unit 24 that calculates the warpage amount of the substrate and the stress of the solder portion from the substrate, the electronic component, and the solder model. Here, the warp direction calculation unit 23 uses the equivalent elastic modulus, the equivalent thermal expansion coefficient, and the bimetal equation, and the warp stress calculation unit 24 calculates the warp amount and the stress using multilayer beam theory. Further, the optimization condition is calculated by the optimizing unit 25 so that the warp and the stress are the best for extending the life of the solder connection portion below the warp threshold from the calculated warp direction, warp amount and stress. The data processed by the data processing device 2 is stored in the storage device 3 and the result is output by the output device 4.

  Here, a method for calculating the warping direction of the substrate will be described in detail with reference to FIG. FIG. 4 shows an example of a three-layer model of 31, 32, and 33, which is a first layer, a second layer, and a third layer. Here, it is divided into two at an arbitrary thickness. In this example, it is divided at the portion of the broken line A. According to the bimetal equation (3), the thickness of the upper part of the broken line A is a1, the thickness of the lower part is a2, and the upper part is the first layer and the second layer. And that part of the third layer will be included. Further, the lower part of the broken line A is only the remaining part 1 layer of the third layer. In order to apply the bimetal equation (3) to this layer structure, it is necessary to consider the upper part of the line A as one layer, so the equation (1) of the equivalent elastic modulus is used. In this example, the equivalent elastic modulus at the upper part of the line A can be calculated as E1 in the bimetal equation (3), and the lower part can be calculated as E2. Further, the linear expansion coefficients α1 and α2 can also be calculated by the same method as the formula (1), that is, instead of the elastic moduli E1, E2, and E3 of each layer in the formula (1), the linear expansion coefficients α1, It can be calculated by adding α2 and α3.

  According to the present invention, in a design department where it is necessary to develop an electronic component or an electronic device in a short time, the warpage and stress generated when the electronic device is manufactured and mounted on a printed wiring board by reflow are designed. Predicted at the initial stage, it can be applied to applications such as a support tool for reducing warpage and taking measures for long life of solder joints.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

1 Input Device 2 Data Processing Device 3 Storage Device 4 Output Device 5 Warpage Direction Calculation Program and Warpage and Stress Calculation Program 21 Data Capture Unit 22 Model Generation Unit 23 Warpage Direction Calculation Unit 24 Warp Stress Calculation Unit 25 Optimization Unit 31 First Layer 32 Second layer 33 Third layer

Claims (4)

A design condition calculation system for calculating a design condition when soldering an electronic component to the surface of a printed circuit board,
A data fetching unit for fetching at least shape data and arrangement data of a printed circuit board sent from an input device and electronic components soldered thereto;
Adding a material characteristic value to each data captured by the data capturing unit, and generating a model data of the printed circuit board; and
Based on the model data generated by the model generation unit, a warp direction calculation unit that calculates the warp direction of the printed circuit board;
Based on the model data generated by the model generation unit, the amount of warpage of the printed circuit board, and a warp stress calculation unit that calculates the stress of the soldered portion,
The design condition that the balance between the warpage amount of the printed circuit board calculated by the warpage stress calculation unit in the warp direction of the printed circuit board calculated by the warp direction calculation unit and the stress of the soldered portion can be an optimal balance. A design condition calculation apparatus comprising: an optimization unit that calculates The design condition calculation apparatus according to claim 1, wherein the warpage direction calculation unit uses an equivalent elastic modulus equation, an equivalent thermal expansion coefficient equation, and a bimetal warpage equation as a method of calculating the warpage direction of the substrate. A first step of designating a component to be examined among printed circuit boards and electronic components to be soldered to the printed circuit board;
A second step of calculating a warping direction of the substrate;
A third step of determining whether or not the electronic component designated as the examination target is disposed on the compression side of the substrate;
A fourth step of calculating the substrate warpage and the stress of the solder part;
A fifth step of determining whether or not the calculated maximum stress of the solder portion is within a threshold;
A sixth step of determining whether the calculated substrate warpage is within a threshold;
A substrate warping and stress optimization method comprising: a seventh step of changing the model. Calculating the board direction based on the shape data and arrangement data of the printed wiring board and the electronic components soldered to the printed wiring board; and
Calculating the warpage of the substrate and the stress of the solder part based on the model data;
A program for optimizing warpage and stress of a substrate, which causes a computer to execute an optimization step based on the calculated result.

Images