JP2009049370A5 - - Google Patents
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- JP2009049370A5 JP2009049370A5 JP2008137063A JP2008137063A JP2009049370A5 JP 2009049370 A5 JP2009049370 A5 JP 2009049370A5 JP 2008137063 A JP2008137063 A JP 2008137063A JP 2008137063 A JP2008137063 A JP 2008137063A JP 2009049370 A5 JP2009049370 A5 JP 2009049370A5
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- JP
- Japan
- Prior art keywords
- layer wiring
- wiring
- semiconductor device
- upper layer
- lower layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Claims (11)
前記スタンダードセルに含まれる機能素子と、
前記機能素子に電気的に接続され、かつ下層配線および上層配線を有する電源線とを備え、
前記下層配線は互いに隣り合う前記スタンダードセルの境界に沿って前記境界上に延在する部分を有し、
前記上層配線が平面視において前記下層配線よりも前記スタンダードセルの内側に位置する部分を有し、
前記機能素子は前記上層配線を介して前記下層配線に電気的に接続されている、半導体装置。 A semiconductor device having a plurality of standard cells arranged,
A functional element included in the standard cell;
A power line electrically connected to the functional element and having a lower layer wiring and an upper layer wiring;
The lower layer wiring has a portion extending on the boundary along the boundary of the standard cells adjacent to each other,
The upper layer wiring has a portion located inside the standard cell than the lower layer wiring in plan view,
The semiconductor device, wherein the functional element is electrically connected to the lower layer wiring through the upper layer wiring.
前記信号線は、平面視において、前記機能素子および前記上層配線の接続部と前記下層配線の前記境界上を延在する部分との間に位置するように配置されている、請求項1に記載の半導体装置。 A signal line electrically connected to the functional element;
The said signal line is arrange | positioned so that it may be located between the connection part of the said functional element and the said upper layer wiring, and the part extended on the said boundary of the said lower layer wiring in planar view. Semiconductor device.
前記上層配線の前記境界上に延在する部分の線幅は、前記下層配線の前記境界上に延在する部分の線幅よりも大きい、請求項1〜4のいずれかに記載の半導体装置。 The upper layer wiring has a portion extending on the boundary along the boundary of the standard cell,
The semiconductor device according to claim 1, wherein a line width of a portion extending on the boundary of the upper layer wiring is larger than a line width of a portion extending on the boundary of the lower layer wiring.
前記スタンダードセルに含まれる機能素子と、
前記機能素子に電気的に接続され、かつ下層配線および上層配線を有する第1の電源線とを備え、
前記下層配線および前記上層配線のそれぞれは、互いに電気的に接続され、かつ互いに隣り合う前記スタンダードセルの境界に沿って前記境界上に延在する部分を有し、
前記上層配線が平面視において前記下層配線よりも太い線幅を有している、半導体装置。 A semiconductor device having a plurality of standard cells arranged,
A functional element included in the standard cell;
A first power line electrically connected to the functional element and having a lower layer wiring and an upper layer wiring;
Each of the lower layer wiring and the upper layer wiring has a portion that is electrically connected to each other and extends on the boundary along the boundary of the standard cells adjacent to each other.
The semiconductor device, wherein the upper layer wiring has a larger line width than the lower layer wiring in a plan view.
前記複数個の第1のビアホールは、前記機能素子を構成するトランジスタの配置ピッチと同じピッチで配置されている、請求項7に記載の半導体装置。 The lower layer wiring and the upper layer wiring are electrically connected by a plurality of first via holes,
The semiconductor device according to claim 7, wherein the plurality of first via holes are arranged at the same pitch as that of transistors constituting the functional element.
前記補強配線は平面視において前記上層配線と直交する方向に延在している、請求項7または8に記載の半導体装置。 The first power supply line has a reinforcing wiring formed in a layer above the upper wiring,
The semiconductor device according to claim 7, wherein the reinforcing wiring extends in a direction orthogonal to the upper layer wiring in a plan view.
前記層間絶縁層は、平面視において前記上層配線と前記補強配線とが交差する1つの交差部において、前記上層配線と前記補強配線とを電気的に接続するための複数個の第2のビアホールを有している、請求項9に記載の半導体装置。 Further comprising a layer insulating layer formed between the reinforcing line and the upper wiring,
Before SL layer insulating layer, in one cross section the upper layer wiring and said reinforcing wire intersect in a plan view, the upper wiring and the reinforcing wire and the electrically plurality of second for connecting The semiconductor device according to claim 9, comprising a via hole.
前記第1のスタンダードセルは、
前記下層配線および前記上層配線を有する前記第1の電源線と、
前記上層配線と同じ層上に延び、かつ平面視において前記下層配線および前記上層配線と同じ方向に延びる第1の信号線とを含み、
前記第2のスタンダードセルは、
前記下層配線と同じ層上に延びる配線層のみからなる第2の電源線と、
前記上層配線と同じ層上に延び、かつ平面視において前記配線層と直交する方向に延びる第2の信号線とを含む、請求項7〜10のいずれかに記載の半導体装置。 The plurality of standard cells include a first standard cell and a second standard cell,
The first standard cell is:
The first power supply line having the lower layer wiring and the upper layer wiring;
A first signal line extending on the same layer as the upper layer wiring and extending in the same direction as the lower layer wiring and the upper layer wiring in a plan view;
The second standard cell is
A second power line consisting only of a wiring layer extending on the same layer as the lower layer wiring;
The semiconductor device according to claim 7, further comprising: a second signal line that extends on the same layer as the upper layer wiring and extends in a direction orthogonal to the wiring layer in plan view.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008137063A JP5293939B2 (en) | 2007-07-25 | 2008-05-26 | Semiconductor device |
TW097126596A TWI437665B (en) | 2007-07-25 | 2008-07-14 | Semiconductor device |
US12/178,204 US8063415B2 (en) | 2007-07-25 | 2008-07-23 | Semiconductor device |
KR1020080072364A KR20090012136A (en) | 2007-07-25 | 2008-07-24 | Semiconductor device |
CN2008101769097A CN101388391B (en) | 2007-07-25 | 2008-07-25 | Semiconductor device |
US13/248,965 US8264011B2 (en) | 2007-07-25 | 2011-09-29 | Semiconductor device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007193580 | 2007-07-25 | ||
JP2007193580 | 2007-07-25 | ||
JP2008137063A JP5293939B2 (en) | 2007-07-25 | 2008-05-26 | Semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009049370A JP2009049370A (en) | 2009-03-05 |
JP2009049370A5 true JP2009049370A5 (en) | 2011-03-31 |
JP5293939B2 JP5293939B2 (en) | 2013-09-18 |
Family
ID=40477685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008137063A Expired - Fee Related JP5293939B2 (en) | 2007-07-25 | 2008-05-26 | Semiconductor device |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP5293939B2 (en) |
KR (1) | KR20090012136A (en) |
CN (1) | CN101388391B (en) |
TW (1) | TWI437665B (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5552775B2 (en) | 2009-08-28 | 2014-07-16 | ソニー株式会社 | Semiconductor integrated circuit |
JP5685457B2 (en) | 2010-04-02 | 2015-03-18 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
JPWO2013018589A1 (en) * | 2011-08-01 | 2015-03-05 | 国立大学法人電気通信大学 | Semiconductor integrated circuit device |
US8813016B1 (en) * | 2013-01-28 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company Limited | Multiple via connections using connectivity rings |
CN103546146B (en) * | 2013-09-24 | 2016-03-02 | 中国科学院微电子研究所 | Single-event transient pulse resistant CMOS circuit |
JP5776802B2 (en) * | 2014-02-14 | 2015-09-09 | ソニー株式会社 | Semiconductor integrated circuit |
US9653413B2 (en) * | 2014-06-18 | 2017-05-16 | Arm Limited | Power grid conductor placement within an integrated circuit |
US9454633B2 (en) * | 2014-06-18 | 2016-09-27 | Arm Limited | Via placement within an integrated circuit |
US11120190B2 (en) * | 2017-11-21 | 2021-09-14 | Advanced Micro Devices, Inc. | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
WO2020044438A1 (en) | 2018-08-28 | 2020-03-05 | 株式会社ソシオネクスト | Semiconductor integrated circuit device |
JP7307355B2 (en) * | 2018-09-28 | 2023-07-12 | 株式会社ソシオネクスト | Semiconductor integrated circuit device and semiconductor package structure |
WO2021192265A1 (en) * | 2020-03-27 | 2021-09-30 | 株式会社ソシオネクスト | Semiconductor integrated circuit device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5923060A (en) * | 1996-09-27 | 1999-07-13 | In-Chip Systems, Inc. | Reduced area gate array cell design based on shifted placement of alternate rows of cells |
JP3672788B2 (en) * | 2000-02-24 | 2005-07-20 | 松下電器産業株式会社 | Cell layout structure and layout design method of semiconductor device |
JP3718687B2 (en) * | 2002-07-09 | 2005-11-24 | 独立行政法人 宇宙航空研究開発機構 | Inverter, semiconductor logic circuit, static random access memory, and data latch circuit |
JP4820542B2 (en) * | 2004-09-30 | 2011-11-24 | パナソニック株式会社 | Semiconductor integrated circuit |
-
2008
- 2008-05-26 JP JP2008137063A patent/JP5293939B2/en not_active Expired - Fee Related
- 2008-07-14 TW TW097126596A patent/TWI437665B/en not_active IP Right Cessation
- 2008-07-24 KR KR1020080072364A patent/KR20090012136A/en not_active Application Discontinuation
- 2008-07-25 CN CN2008101769097A patent/CN101388391B/en active Active
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