JP2009049370A5 - - Google Patents

Claims (11)

A semiconductor device having a plurality of standard cells arranged,
A functional element included in the standard cell;
A power line electrically connected to the functional element and having a lower layer wiring and an upper layer wiring;
The lower layer wiring has a portion extending on the boundary along the boundary of the standard cells adjacent to each other,
The upper layer wiring has a portion located inside the standard cell than the lower layer wiring in plan view,
The semiconductor device, wherein the functional element is electrically connected to the lower layer wiring through the upper layer wiring. A signal line electrically connected to the functional element;
The said signal line is arrange | positioned so that it may be located between the connection part of the said functional element and the said upper layer wiring, and the part extended on the said boundary of the said lower layer wiring in planar view. Semiconductor device.   The semiconductor device according to claim 1, wherein the upper layer wiring and the lower layer wiring are connected in the standard cell in which the functional element is disposed.   The semiconductor device according to claim 1, wherein the upper layer wiring and the lower layer wiring are connected in the standard cell that does not include the functional element. Wherein disposed in said standard cell containing no functional element, and with the lower layer wiring to further electrically connected to fuse, a semiconductor device according to claim 4. The upper layer wiring has a portion extending on the boundary along the boundary of the standard cell,
The semiconductor device according to claim 1, wherein a line width of a portion extending on the boundary of the upper layer wiring is larger than a line width of a portion extending on the boundary of the lower layer wiring. A semiconductor device having a plurality of standard cells arranged,
A functional element included in the standard cell;
A first power line electrically connected to the functional element and having a lower layer wiring and an upper layer wiring;
Each of the lower layer wiring and the upper layer wiring has a portion that is electrically connected to each other and extends on the boundary along the boundary of the standard cells adjacent to each other.
The semiconductor device, wherein the upper layer wiring has a larger line width than the lower layer wiring in a plan view. The lower layer wiring and the upper layer wiring are electrically connected by a plurality of first via holes,
The semiconductor device according to claim 7, wherein the plurality of first via holes are arranged at the same pitch as that of transistors constituting the functional element. The first power supply line has a reinforcing wiring formed in a layer above the upper wiring,
The semiconductor device according to claim 7, wherein the reinforcing wiring extends in a direction orthogonal to the upper layer wiring in a plan view. Further comprising a layer insulating layer formed between the reinforcing line and the upper wiring,
Before SL layer insulating layer, in one cross section the upper layer wiring and said reinforcing wire intersect in a plan view, the upper wiring and the reinforcing wire and the electrically plurality of second for connecting The semiconductor device according to claim 9, comprising a via hole. The plurality of standard cells include a first standard cell and a second standard cell,
The first standard cell is:
The first power supply line having the lower layer wiring and the upper layer wiring;
A first signal line extending on the same layer as the upper layer wiring and extending in the same direction as the lower layer wiring and the upper layer wiring in a plan view;
The second standard cell is
A second power line consisting only of a wiring layer extending on the same layer as the lower layer wiring;
The semiconductor device according to claim 7, further comprising: a second signal line that extends on the same layer as the upper layer wiring and extends in a direction orthogonal to the wiring layer in plan view.