JP2009049273A - Method of manufacturing semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor apparatus provided with a full silicide gate electrode of a Ni base showing desired work function without making thermal budget large. <P>SOLUTION: A gate insulating film 2 is formed on an Si substrate 1. A polysilicon gate electrode layer 3 is formed on the gate insulating film 2. An Ni film 5 is formed over the polysilicon gate electrode layer 3 with a Co film 4 in-between. Then they are annealed to form the full silicide gate electrode 6 containing NiSi<SB>2</SB>which is Si-rich silicide. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a gate electrode is made of silicide.

  In recent years, development of metal gate technology that replaces polysilicon, which is a gate material of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), with metal has been accelerated for the purpose of improving the performance of semiconductor devices. Metal gate technology is a technology that greatly contributes to higher speed and higher functionality of semiconductor integrated circuits because gate depletion, which is a problem when using polysilicon gates, can be suppressed and gate sheet resistance can be greatly reduced. It is positioned as.

  A fully silicided gate is a kind of metal gate, and has a gate structure in which the entire gate electrode is silicided instead of silicidizing only the upper part of the source / drain and polysilicon gate electrode layers as in the prior art. . The material used for the full silicide gate is already used as a material for semiconductor processes such as cobalt (Co) and nickel (Ni), so it can be easily applied to existing production lines. It is attracting attention as a leading technology for next-generation CMOS (Complementary Metal Oxide Semiconductor).

  However, there are problems with process integration and work function control of the gate, and it has not been put into practical use at present. Among these, with regard to process integration, there are reports on a method using CMP (Chemical Mechanical Polishing), a method using a hard mask, and the like, and a solution path has become apparent.

On the other hand, with respect to the work function control of the gate, there is a problem of obtaining a work function equivalent to that in the case of using conventional polysilicon.
For example, Non-Patent Document 1 discloses that the composition of the silicide of an N-channel MOSFET (hereinafter abbreviated as NMOS) and a P-channel MOSFET (hereinafter abbreviated as PMOS) is changed by changing the film thickness of deposited Ni, and the work function is changed. A method for controlling the above has been proposed. According to Non-Patent Document 1, a silicon (Si) rich silicide such as nickel disilicide (NiSi ₂ ) is used in NMOS, and a Ni rich silicide such as dinickel silicide (Ni ₂ Si) or Ni ₃ Si is used in PMOS. Is desirable from the viewpoint of work function.

  The composition of nickel silicide depends on the amount of Ni deposited on the polysilicon and the formation temperature. According to Non-Patent Document 1, Ni-rich silicide advantageous for a PMOS gate electrode can be formed by increasing the Ni deposited film thickness and annealing in a temperature range of 450 to 550 ° C. On the other hand, Si-rich nickel silicide, which is advantageous for NMOS gate electrodes, can be formed by thinning the Ni deposition film thickness and annealing at a relatively high temperature of 650 ° C. or higher.

Conventionally, there has been a technique of annealing by sandwiching a cobalt (Co) layer between Ni and Si in order to prevent facets from entering along the silicon (111) surface and form uniform NiSi 2 (for example, , See Patent Document 1).
K. Takahashi et al., IEDM Tech. Dig., P. 91, 2004 JP 2002-343742 A

  In the conventional technology, when forming Si-rich nickel silicide suitable for an NMOS gate electrode, it is necessary to anneal at a high temperature of 650 ° C. or higher, so that there is a problem that the thermal budget becomes large, and Ni is not suitable for annealing. Aggregation tends to occur, and it is very difficult to form stable nickel silicide.

  The present invention has been made in view of the above points, and it is possible to manufacture a semiconductor device including a nickel-based full silicide gate electrode exhibiting a desired work function without increasing a thermal budget. An object is to provide a manufacturing method.

  The inventor forms a gate insulating film, a step of forming a polysilicon gate electrode layer on the gate insulating film, and a step of forming a nickel film on the polysilicon gate electrode layer through a cobalt film. And a step of forming a full silicide gate electrode containing nickel disilicide by annealing, and a method for manufacturing a semiconductor device.

  According to the above method, the nickel film is formed on the polysilicon gate electrode layer via the cobalt film, so that the full silicide gate electrode containing nickel disilicide is formed by annealing at a relatively low temperature.

  In the present invention, a nickel film is formed on a polysilicon gate electrode layer through a cobalt film, and thus a full silicide including nickel disilicide showing a work function suitable as an NMOS gate electrode in a relatively low temperature annealing process. A gate electrode can be formed. This eliminates the need to increase the thermal budget.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an outline of a method for manufacturing a semiconductor device of the present embodiment.
The method of manufacturing a semiconductor device according to the present embodiment relates to a MOSFET having a Ni-based full silicide gate electrode. FIG. 1 shows a schematic cross-sectional view in each process particularly when an NMOS gate is formed. Only the gate portion is shown.

First, as shown in FIG. 1A, a gate insulating film 2 is formed on a Si substrate 1. Thereafter, a polysilicon gate electrode layer 3 is formed (FIG. 1A). Subsequently, a thin Co film 4 is formed on the polysilicon gate electrode layer 3, and a Ni film 5 is formed thereon (FIG. 1B). The thicknesses of the polysilicon gate electrode layer 3 and the Ni film 5 are set so that the composition ratio of Si and Ni is approximately 2: 1. For example, if the thickness of the polysilicon gate electrode layer 3 is 50 nm, the thickness of the Ni film 5 is 15 nm. If the thickness of the polysilicon gate electrode layer 3 is 100 nm, the thickness of the Ni film 5 is When the thickness is 30 nm, the above composition ratio 2: 1 is satisfied. The laminated structure composed of the polysilicon gate electrode layer 3, the Co film 4 and the Ni film 5 is annealed and silicided to form a full silicide gate electrode 6 containing NiSi ₂ (FIG. 1). (C)).

Thus, when the thin Co film 4 is formed between the polysilicon gate electrode layer 3 and the Ni film 5, the Ni film 5 is directly formed on the polysilicon gate electrode layer 3 (650 ° C. or higher). The full silicide gate electrode 6 containing Si-rich NiSi ₂ suitable for the NMOS gate electrode can be formed by low-temperature (450 to 550 ° C.) annealing.

Hereinafter, the results of examining the composition of the nickel silicide formed by changing the thickness of the Co film 4 will be shown.
FIG. 2 shows the XRD (X-Ray Diffraction) measurement result when the deposited film thickness of cobalt is changed.

The vertical axis is intensity (AU), and the horizontal axis is θ / 2θ.
The sample preparation conditions used here are as follows.
First, the Si substrate 1 is oxidized to form a gate insulating film (oxide film) 2 having a thickness of 5 nm, and polysilicon is deposited to a thickness of 50 nm to form a polysilicon gate electrode layer 3. Thereafter, RTA (Rapid Thermal Annealing) is performed at 1000 ° C. for 10 seconds. This is a process assuming activation annealing of impurities. Subsequently, the surface of the polysilicon gate electrode layer 3 is pretreated with hydrofluoric acid to remove the natural oxide film, the Co film 4 and the Ni film 5 are continuously sputter deposited, and RTA is performed at 500 ° C. for 2 minutes. The Co film 4 is 0.8 nm, 1.6 nm, and 2.3 nm, and the Ni film 5 is constant at 15 nm.

As can be seen from FIG. 2, NiSi ₂ is formed after annealing at 500 ° C. Further, the NiSi ₂ composition ratio can be controlled by changing the thickness of the Co film 4. As shown in FIG. 2, when the Co film 4 is thinner, more NiSi ₂ is formed. It was found that when the Co film 4 is 0.8 nm, a peak due to nickel monosilicide (NiSi) is almost invisible, and the formed nickel silicide is almost composed of NiSi ₂ . That is, by setting the Co film 4 to approximately 1 nm or less, a full silicide gate electrode 6 made of nickel silicide containing NiSi ₂ as a main component can be obtained.

Thus, when the thin Co film 4 is formed between the polysilicon gate electrode layer 3 and the Ni film 5, the reason why NiSi ₂ can be obtained at a relatively low temperature has not been sufficiently elucidated. However, during annealing, cobalt silicide (CoSi ₂ ) with good crystallinity is formed first, and then Ni diffuses into the polysilicon through the CoSi ₂ crystal, so that NiSi ₂ is compared. It seems to be generated stably.

As described above, according to the manufacturing method of the semiconductor device of the present embodiment, the Ni film 5 is formed on the polysilicon gate electrode layer 3 with the Co film 4 interposed therebetween, so that the annealing process can be performed at a relatively low temperature. Nickel silicide containing NiSi ₂ showing a work function suitable as an NMOS gate electrode can be formed. Therefore, it is not necessary to increase the thermal budget.

Moreover, since the composition of the nickel silicide formed can be changed by changing the thickness of the Co film 4, the work function can be adjusted.
Next, taking the case of manufacturing a CMOS as an example, the method for manufacturing the semiconductor device of the present embodiment will be described in detail.

Note that the manufacturing conditions shown below are merely examples, and the present invention is not particularly limited thereto.
3 to 10 are schematic cross-sectional views in each step of the method for manufacturing the semiconductor device of the present embodiment.

  First, a process in which illustration up to FIG. 3 is omitted will be briefly described. First, for example, an element isolation region is formed in a predetermined region of a Si (100) P-type substrate 10 (hereinafter simply referred to as a Si substrate 10) by using a LOCOS (Local Oxidation of Silicon) method or an STI (Shallow Trench Isolation) method. Subsequently, donors or acceptors are implanted into the transistor formation regions of the respective polarities to form wells, and channel ion implantation for adjusting the threshold voltage Vth is performed to form channel regions.

  Thereafter, the surface of the Si substrate 10 is thermally oxidized to form a gate insulating film 11. As the gate insulating film 11, in addition to a thermal oxide film, an oxynitride film, a high-k insulating film, or the like can be used. Subsequently, a polysilicon gate electrode layer 12 is formed, for example, by 50 nm on the gate insulating film 11 using a CVD (Chemical Vapor Deposition) method or the like, and a silicon nitride (SiN) film 13 is formed thereon as a hard mask. For example, 50 nm is formed.

  Then, the three layers of the SiN film 13, the polysilicon gate electrode layer 12, and the gate insulating film 11 are processed by the photolithography technique and the etching technique, leaving the NMOS and PMOS gate electrode portions. As a result, as shown in FIG. 3, a patterned gate insulating film 11 and polysilicon gate electrode are formed on the Si substrate 10 in regions where NMOS and PMOS are formed (hereinafter referred to as NMOS formation region and PMOS formation region, respectively). A laminated structure including the layer 12 and the SiN film 13 is obtained.

  Thereafter, one of the NMOS formation region and the PMOS formation region, for example, the PMOS formation region is covered with a resist or the like, and ion implantation is performed on the NMOS formation region under a predetermined condition using the above-described stacked structure as a mask. Next, the other region, that is, in this case, the NMOS formation region is covered with a resist or the like, and ion implantation is performed on the PMOS formation region under a predetermined condition using the stacked structure as a mask. Thereafter, activation annealing is performed under predetermined conditions. As a result, as shown in FIG. 4, extension regions 14a and 14b are formed in the NMOS formation region and the PMOS formation region, respectively.

  When forming the extension regions 14a and 14b, a thin sidewall (not shown) may be formed on the side wall of the laminated structure serving as an ion implantation mask, and then ion implantation and activation annealing may be performed. . The activation annealing here may be performed collectively after the formation of the deep source / drain regions described below.

  Thereafter, a silicon oxide film is formed on the entire surface by CVD or the like, and anisotropic etching is performed to form sidewalls 15 on the side walls of the gate insulating film 11, the polysilicon gate electrode layer 12, and the SiN film 13. The lateral thickness of the sidewall 15 is, for example, 40 nm.

  The sidewall 15 may be formed using an insulating material other than the silicon oxide film. In addition, for example, a silicon oxide film is formed on the entire surface, and then a silicon nitride film is formed on the silicon oxide film. Then, anisotropic etching is performed to form a silicon oxide film on the inside and a silicon oxide film on the outside. A double-structure sidewall provided with a nitride film may be formed.

  Next, deep source / drain regions 16a and 16b are formed by implanting ions into the NMOS formation region and the PMOS formation region, respectively, using the sidewall 15 as a mask, and performing activation annealing. The structure shown in the schematic cross-sectional view of FIG. 4 is obtained through the steps up to here.

Next, a salicide process is performed on the source / drain regions 16a and 16b.
As a pretreatment, the natural oxide films in the source / drain regions 16a and 16b are removed with hydrofluoric acid or the like. Thereafter, for example, when Ni is sputter-deposited to about 20 nm and annealed at about 400 ° C., NiSi 17 is formed in the source / drain regions 16a and 16b. At this time, since the upper portion of the gate is covered with the SiN film 13 functioning as a hard mask, it is not silicided. Then, the structure shown in the cross-sectional schematic diagram of FIG. 5 is obtained by removing unreacted Ni with sulfuric acid as a post-treatment.

  In this example, Ni is used as an example of the silicide metal of the source / drain regions 16a and 16b. However, the present invention is not limited to this, and Co, tungsten (W), tantalum (Ta), titanium (Ti), platinum ( A metal such as Pt) may be substituted. The annealing temperature varies depending on the selected metal.

  Subsequently, a CMP stopper film 18 and a CMP film 19 are deposited as shown in FIG. As the CMP stopper film 18, a SiN film is used in the same manner as the hard mask of the gate. Further, a silicon oxide film is used for the CMP film 19.

  Thereafter, the CMP process is performed as shown in FIG. Furthermore, the structure as shown in FIG. 8 is obtained by removing the SiN film 13 remaining on the polysilicon gate electrode layer 12 using a chemical solution such as phosphoric acid.

As described above, it is suitable from the viewpoint of work function to use Si-rich nickel silicide such as NiSi _{2 for} NMOS and Ni-rich nickel silicide such as Ni ₂ Si and Ni ₃ Si for PMOS. .

Therefore, as shown in FIG. 9, the Co film 20 and the Ni film 21 are deposited in the NMOS formation region, and the Ni film 22 single layer is deposited in the PMOS formation region.
Specifically, in the state of FIG. 8, for example, the entire surface of the wafer is covered with an oxide film or the like, and only the NMOS formation region is first opened by the photolithography technique and the etching technique. In this state, Co and Ni are continuously sputter-deposited, whereby a laminated structure of the Co film 20 and the Ni film 21 can be formed. Similarly, a single-layer Ni film 22 can be formed by opening only the PMOS formation region using oxide film deposition, photolithography technique, and etching technique and then sputter depositing Ni.

The thickness of the Ni film 21 deposited in the NMOS formation region is 15 nm so that the composition ratio of Si and Ni satisfies 2: 1 because the thickness of the polysilicon gate electrode layer 12 is 50 nm. The film thickness of the Co film 20 is set to, for example, 0.8 nm because nickel silicide containing NiSi ₂ as a main component can be formed when the film thickness is about 1 nm or less from the result of the XRD measurement shown in FIG. Note that, by changing the thickness of the Co film 20, the composition of the nickel silicide formed can be changed as in the result of the XRD measurement in FIG.

On the other hand, since it is desirable to form nickel silicide containing Ni-rich Ni ₂ Si or the like at the gate of the PMOS formation region, the thickness of the deposited Ni film 22 is increased. For example, when the thickness of the polysilicon gate electrode layer 12 is 50 nm, the thickness is set to 30 nm to 200 nm. However, if it is too thick, Ni cannot be removed in the subsequent step of removing unreacted Ni, so it is appropriately selected.

Thereafter, an annealing process is performed at the same temperature, for example, 450 to 550 ° C., simultaneously with the NMOS formation region and the PMOS formation region. The annealing time is, for example, 10 seconds to 120 seconds in consideration of the annealing temperature and throughput. Thereby, in the NMOS formation region, the stacked structure of the polysilicon gate electrode layer 12, the Co film 20, and the Ni film 21 is silicided, and a full silicide gate electrode 23 made of nickel silicide containing NiSi ₂ as a main component is formed. . In the PMOS formation region, the stacked structure including the polysilicon gate electrode layer 12 and the Ni film 22 is silicided to form a full silicide gate electrode 24 formed of Ni-rich nickel silicide. Furthermore, the structure of FIG. 10 is obtained by removing unreacted metal with sulfuric acid or the like.

Thereafter, an interlayer insulating film, contacts, wirings and the like are formed according to a known method to complete the semiconductor device.
As described above, in the method of manufacturing a semiconductor device according to the present embodiment, when the Co film 20 is formed between the polysilicon gate electrode layer 12 and the nickel film 21 and annealing treatment for silicidation is performed, 450 to The Si-rich full silicide gate electrode 23 can be formed at a relatively low temperature of 550 ° C. This temperature range is substantially equal to the annealing temperature for silicidation of the gate on the PMOS formation region side. That is, the silicidation annealing process can be simultaneously performed in the NMOS formation region and the PMOS formation region, and a full silicide gate electrode having a different composition between the NMOS and the PMOS can be realized without increasing the thermal budget.

  In the above description, Ni is used for the silicidation of the gate, but a material such as Pt, W, Ta, Ti mixed with Ni may be used.

It is a figure which shows the outline | summary of the manufacturing method of the semiconductor device of this Embodiment. It is an XRD measurement result when changing the deposited film thickness of cobalt. It is a cross-sectional schematic diagram in each process of the manufacturing method of the semiconductor device of this Embodiment (the 1). It is a cross-sectional schematic diagram in each process of the manufacturing method of the semiconductor device of this Embodiment (the 2). It is a cross-sectional schematic diagram in each process of the manufacturing method of the semiconductor device of this Embodiment (the 3). It is a cross-sectional schematic diagram in each process of the manufacturing method of the semiconductor device of this Embodiment (the 4). It is a cross-sectional schematic diagram in each process of the manufacturing method of the semiconductor device of this Embodiment (the 5). It is a cross-sectional schematic diagram in each process of the manufacturing method of the semiconductor device of this Embodiment (the 6). It is a cross-sectional schematic diagram in each process of the manufacturing method of the semiconductor device of this Embodiment (the 7). It is a cross-sectional schematic diagram in each process of the manufacturing method of the semiconductor device of this Embodiment (the 8).

Explanation of symbols

1 Si substrate 2 Gate insulating film 3 Polysilicon gate electrode layer 4 Co film 5 Ni film 6 Full silicide gate electrode

Claims (5)

Forming a gate insulating film;
Forming a polysilicon gate electrode layer on the gate insulating film;
Forming a nickel film on the polysilicon gate electrode layer through a cobalt film;
Forming a full silicide gate electrode containing nickel disilicide by annealing; and
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the nickel film is deposited so that the composition ratio of silicon to nickel in the polysilicon gate electrode layer is approximately 2: 1 after the annealing.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the cobalt film has a thickness of about 1 nm or less.   4. The method of manufacturing a semiconductor device according to claim 1, wherein a composition ratio of the nickel disilicide is controlled by changing a film thickness of the cobalt film. 5.   The semiconductor device is a semiconductor device having an N-channel MOSFET and a P-channel MOSFET, and the annealing process is performed simultaneously at the same temperature for the N-channel MOSFET and the P-channel MOSFET. The method for manufacturing a semiconductor device according to claim 1.

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