JP4784734B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, high performance and high performance of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using a high dielectric constant material for a gate insulating film and a metal silicide material for a gate electrode. This is a technology related to reliability.

  In the development of advanced CMOS (complementary MOS) devices, where transistor miniaturization is progressing, degradation of drive current due to depletion of polycrystalline silicon (poly-Si) electrodes and increase in gate leakage current due to thinning of the gate insulating film It is a problem. In view of this, a composite technique for reducing gate leakage current by using a metal gate electrode to avoid depletion of the electrode and at the same time increasing the physical film thickness by using a high dielectric constant material for the gate insulating film has been studied.

  As materials used for the metal gate electrode, pure metals, metal nitrides, silicide materials, and the like have been studied. However, in any case, (1) when the metal gate electrode is formed, the gate insulating film is deteriorated. (2) It is necessary that the threshold voltage (Vth) of the N-type MOSFET and the P-type MOSFET can be set to an appropriate value.

  In order to realize a Vth of ± 0.5 eV or less with a CMOS transistor, a material with a work function of Si mid gap (4.6 eV) or less, preferably 4.4 eV or less is desirable for an N-type MOSFET, and work is desired for a P-type MOSFET. It is necessary to use a material having a function of a Si mid gap (4.6 eV) or more, preferably 4.8 eV or more for the gate electrode.

  As a means to realize these, a method (dual metal gate technology) is proposed in which Vth of a transistor is controlled by using different metals or alloys having different work functions for electrodes of N-type MOSFET and P-type MOSFET, respectively. Has been.

For example, in Non-Patent Document 1, the work functions of Ta and Ru formed on SiO ₂ are 4.15 eV and 4.95 eV, respectively, and a work function modulation of 0.8 eV is possible between the two electrodes. It is stated.

  However, in the dual metal gate technology, a metal layer made of different kinds of metals or alloys having different work functions needs to be separately formed on the substrate. Therefore, on the gate insulating film of either the P-type MOSFET or the N-type MOSFET. There is a process in which the metal layer deposited on the substrate is etched away, and the quality of the gate insulating film is deteriorated during the etching removal, resulting in a problem that the characteristics and reliability of the device are impaired.

  On the other hand, a technique related to a silicide gate electrode obtained by completely siliciding a poly-Si electrode pattern with Ni has recently attracted attention. The feature of this technique is that after performing a high temperature heat treatment for activating impurities in the source / drain diffusion region of the CMOS, the poly-Si electrode can be silicided by a salicide process. For this reason, the compatibility with the conventional CMOS process is high, and the film deposited on the gate insulating film does not need to be removed by etching unlike the dual metal gate technique, so that damage to the gate insulating film can be suppressed.

In Non-Patent Documents 2 and 3, in a MOSFET as shown in FIG. 2, a poly-Si electrode pattern in which SiO ₂ is used as a gate insulating film and impurities such as P and B are implanted as a gate electrode is completely formed of Ni. A technique is disclosed in which the work function of an electrode is modulated at a maximum of 0.5 eV by using a silicided Ni silicide electrode (P-doped NiSi, B-doped NiSi). The reference numerals in the figure are 1 for the silicon substrate, 2 for the element isolation region, 3a for the SiO ₂ film, 4 for the extension diffusion region, 5 for the source / drain diffusion region, 6 for the silicide layer, and 7 for the gate sidewall. , 9 is an interlayer insulating film, 11 is a P-doped NiSi electrode, and 12 is a B-doped NiSi electrode.

In Non-Patent Document 4, in a MOSFET using a HfSiON high dielectric constant film as a gate insulating film and using a fully silicided Ni silicide electrode as a gate electrode, the formation of a crystal phase is used to form Ni silicide. It is disclosed that by controlling the composition (phase controlled Ni full silicide technology), as shown in FIG. 3, it is possible to control a wide range of effective work functions of the transistor. At this time, Vth of ± 0.3 V can be realized by using Ni ₃ Si for PMOS and NiSi ₂ for NMOS.
International Electron Device Meeting Technical Digest 2002, p. 359 International Electron Device Meeting Technical Digest 2002, p. 247 International Electron Device Meeting Technical Digest 2003, p. 315 International Electron Device Meeting Technical Digest 2004, p. 91

The phase control Ni full silicide technology is expected as a technology for realizing a CMOS using a metal gate electrode and a high dielectric constant gate insulating film. However, there is a problem that fine adjustment of the effective work function is difficult with the above-described phase control Ni full silicide technology. Since the effective work function of Ni silicide on HfSiON corresponds to the composition of Ni silicide determined in a self-aligned manner by the formation of the crystal phase, it has a stepwise value corresponding to the crystal phase. According to Non-Patent Document 4, it is possible to stably form crystal phases of NiSi ₂ , NiSi, and Ni ₃ Si on HfSiON, and the effective work functions are 4.4, 4.5, and 4.8 eV, respectively. It is shown. Such a gradual change in effective work function is very useful in ensuring the stability of Vth if each value is consistent with the design of the device, while a wider range of devices. There is a problem that application to is difficult.

For example, in an LSTP (low stand-by power) device, the value of Vth needs to be set to ± 0.4 to 0.5V. The value of the effective work function at this time is optimally ± 0.1 to 0.15 V of the Si mid gap (Ei: 4.6 eV). Specifically, it is desirable to apply an electrode having an effective work function of 4.45 to 4.5 eV to an N-type MOSFET and an electrode having an effective work function of 4.7 to 4.75 eV to a P-type MOSFET. Further, in the non-doped channel SOI device, the effective work function of the gate electrode is optimally Si midgap (Ei: 4.6 eV). However, for example, the effective work functions of NiSi ₂ , NiSi and Ni ₃ Si on HfSiON are 4.4 eV, 4.5 eV and 4.8 eV, respectively. It is difficult to realize with controlled full silicide technology.

  Therefore, in addition to the conventional phase control full silicide technique, a technique capable of finely adjusting the effective work function is required. That is, an object of the present invention is to solve the above-described problems, to make it possible to apply the phase control full silicide technology to a wider range of devices, and to provide a semiconductor device having high performance and excellent reliability.

  The present invention includes the embodiments described in the following items.

(1) In a semiconductor device including a field effect transistor having a gate insulating film and a gate electrode provided on the gate insulating film on a silicon substrate,
The gate insulating film has a high dielectric constant insulating film made of metal oxide, metal silicate, or metal oxide or metal silicate into which nitrogen is introduced;
The gate electrode is provided on the lower layer side in contact with the high dielectric constant insulating film, and includes a first metal M1, a second metal M2 having a work function different from that of M1, and a first silicide made of silicon (Si). And a second layer region made of silicide containing M1 and Si provided on the upper layer side in contact with the first layer region.

(2) The first metal M1 is nickel (Ni), and the first layer region is made of silicide having a composition represented by Ni _x M2 _y Si _1-xy (x + y ≧ 0.55). 2. The semiconductor device according to item 1, wherein the layer region is made of silicide containing a Ni ₃ Si phase as a main component.

  (3) The semiconductor device according to item (2), wherein the field effect transistor is a P-channel transistor.

(4) A semiconductor device comprising a field effect transistor having a gate insulating film and a gate electrode provided on the gate insulating film on a silicon substrate,
The gate insulating film has a high dielectric constant insulating film made of metal oxide, metal silicate, or metal oxide or metal silicate into which nitrogen is introduced;
The gate electrode, the high dielectric constant provided on the lower side in contact with the insulating film includes a nickel metal M and silicon having a different work function (Ni) (Si), Ni x M y Si 1-xy (0 A first layer region having a composition represented by ≦ x <1, 0 <y <1, 0 <x + y <1), and Ni _z Si ₁₋ provided on the upper layer side in contact with the first layer region _a second layer region having a composition represented by _z (0 ≦ z <1),
The field effect transistor includes a P-channel transistor and an N-channel transistor having at least a second layer region having different compositions, and the P-channel transistor satisfies x + y ≧ 0.55 and z ≧ 0.55, and has an N-channel Type transistor, a semiconductor device satisfying x + y <0.55 and z <0.55.

(5) In the P-channel transistor, the second layer region of the gate electrode is made of silicide containing a Ni ₃ Si phase as a main component,
5. The semiconductor device according to claim 4, wherein the second channel region of the gate electrode of the N-channel transistor is made of silicide containing a NiSi phase or a NiSi ₂ phase as a main component.

  (6) The semiconductor device according to item 4 or 5, wherein the composition of the first layer region satisfies 0 <x <1, 0 <y ≦ 0.5.

(7) In the P-channel transistor, the second layer region of the gate electrode is made of silicide containing a Ni ₃ Si phase as a main component,
5. The N-channel transistor according to item 4, wherein the second layer region of the gate electrode contains Si as a main component, and the composition of the first layer region satisfies x = 0 and 0 <y ≦ 0.5. Semiconductor device.

(8) In the P-channel transistor, the second layer region of the gate electrode is made of silicide containing a NiSi phase as a main component,
5. The semiconductor according to claim 4, wherein the N-channel transistor includes a second layer region of a gate electrode thereof as a Si main component, and the composition of the first layer region satisfies x = 0 and 0 <y ≦ 0.5. apparatus.

  (9) The semiconductor device according to item 7 or 8, wherein the composition of the first layer region of the P-channel transistor satisfies 0 <x <1, 0 <y ≦ 0.5.

  (10) The semiconductor device according to any one of Items 1 to 9, wherein T1 <T2 when the thickness of the first layer region is T1 and the thickness of the second layer region is T2.

  (11) When the thickness of the first layer region is represented by T1 and the thickness of the second layer region is represented by T2, T1 <T2 and T1 ≦ 5 nm, Semiconductor device.

  (12) The semiconductor device according to any one of items 4 to 11, wherein the metal M is a metal capable of forming a refractory metal silicide having a melting point of 1100 ° C. or higher.

  (13) The semiconductor device according to any one of items 4 to 12, wherein the metal M is W, Mo, Ta, or Ti.

  (14) The semiconductor device according to any one of (1) to (13), wherein the high dielectric constant insulating film includes an insulating film containing Hf or Zr.

  (15) The semiconductor device according to (14), wherein the insulating film containing Hf or Zr is provided in a portion in contact with the gate electrode.

  (16) The semiconductor device according to any one of (1) to (15), wherein the gate insulating film has a stacked structure including a silicon oxide film or a silicon oxynitride film and a high dielectric constant insulating film containing Hf or Zr.

  (17) The semiconductor device according to any one of items 1 to 16, wherein an HfSiON film is used as the high dielectric constant insulating film.

(18) A method of manufacturing a semiconductor device according to item 1,
Forming a gate insulating film on the silicon substrate;
A metal-containing film containing the second metal M2 and silicon (Si) is formed on the gate insulating film, and an amorphous silicon film, a polycrystalline silicon film, or a silicon film made of both of them is formed on the metal-containing film. And a process of
Forming a gate pattern by processing the gate insulating film, the metal-containing film and the laminated film including the silicon film;
Forming a film of a first metal M1 on the gate pattern and performing a heat treatment to turn the entire gate pattern into a silicide of M1,
A method of manufacturing a semiconductor device, including a step of removing M1 that has not been silicided.

(19) A method of manufacturing a semiconductor device according to item 2,
Forming a gate insulating film on the silicon substrate;
A metal-containing film containing the second metal M2 and silicon (Si) is formed on the gate insulating film, and an amorphous silicon film, a polycrystalline silicon film, or a silicon film made of both of them is formed on the metal-containing film. And a process of
Forming a gate pattern by processing the gate insulating film, the metal-containing film and the laminated film including the silicon film;
A silicidation step of forming a nickel (Ni) film on the gate pattern and performing a heat treatment to turn the entire gate pattern into a silicide of Ni;
Removing Ni that has not been silicided,
In the silicidation step, the second layer region of the gate electrode contains Ni ₃ Si phase as a main component, and the composition of the first layer region is Ni _x M2 _y Si _1-xy (x + y ≧ 0.55). Thus, the manufacturing method of the semiconductor device which sets the thickness of the Ni film.

(20) The method of manufacturing a semiconductor device according to item 4,
Forming a gate insulating film on the silicon substrate;
Forming a metal-containing film containing metal M and silicon (Si) on the gate insulating film, and forming a silicon film made of an amorphous silicon film or a polycrystalline silicon film or both on the metal-containing film; ,
Forming a gate pattern by processing the gate insulating film, the metal-containing film and the laminated film including the silicon film;
A silicidation step of forming a nickel (Ni) film on the gate pattern and performing a heat treatment to turn the entire gate pattern into a silicide of Ni;
Removing Ni that has not been silicided,
In the silicidation step, the thickness of the Ni film on the P-channel region and the N-channel region so that the composition of the gate electrode of the P-channel transistor and the composition of the gate electrode of the N-channel transistor become the predetermined composition. Semiconductor device manufacturing method for setting the thickness of the Ni film.

(21) A method of manufacturing a semiconductor device according to item 5,
In the silicidation process, in the P channel region, the thickness of the Ni film is set so that the second layer region contains Ni ₃ Si phase as a main component and the composition of the first layer region satisfies x + y ≧ 0.55. In the N channel region, the thickness of the Ni film is set so that the second layer region is mainly composed of the NiSi phase or NiSi ₂ phase, and the composition of the first layer region satisfies x + y <0.55. The manufacturing method of the semiconductor device as described in any one of.

(22) A method for manufacturing a semiconductor device according to item 7,
In the silicidation process, in the P channel region, the thickness of the Ni film is set so that the second layer region contains Ni ₃ Si phase as a main component and the composition of the first layer region satisfies x + y ≧ 0.55. Item 21. In the N channel region, the second layer region contains Si as a main component, and the Ni layer is not provided so that the composition of the first layer region satisfies x = 0 and y ≦ 0.5. A method for manufacturing a semiconductor device.

(23) A method of manufacturing a semiconductor device according to item 8,
In the silicidation step, in the P channel region, the thickness of the Ni film is set so that the second layer region contains NiSi phase as a main component and the composition of the first layer region satisfies x + y ≧ 0.55, and N 21. The semiconductor device according to 20, wherein in the channel region, the second layer region includes Si as a main component, and the Ni film is not provided so that the composition of the first layer region satisfies x = 0 and y ≦ 0.5. Manufacturing method.

  (24) The method of manufacturing a semiconductor device as described in 19 above, wherein the ratio of the thickness t of the Ni film to the thickness T of the laminated film of the gate pattern is t / T ≧ 1.64.

(25) In the P channel region, the ratio of the thickness t1 of the Ni film and the thickness T of the stacked film of the gate pattern is t1 / T ≧ 1.64,
Item 22. The semiconductor device manufacturing according to Item 20 or 21, wherein in the N channel region, the ratio of the thickness t2 of the Ni film and the thickness T of the stacked film of the gate pattern is 0.28 ≦ t2 / T ≦ 0.95. Method.

  (26) In the silicidation step, after forming the first Ni film on the N channel region and the P channel region, forming a diffusion prevention film stable to Ni only on the N channel region, and then 26. The method of manufacturing a semiconductor device according to 20, 20, or 25, wherein a second Ni film is formed on the entire surface including the P channel region, and the thickness of the Ni film involved in silicidation is controlled.

  (27) In the above silicidation step, a diffusion prevention film stable to Ni is formed only on the N channel region, and then a Ni film is formed on the entire surface including the P channel region. Semiconductor device manufacturing method.

  (28) The method for manufacturing a semiconductor device according to item 26 or 27, wherein the diffusion prevention film is made of a material that can be selectively etched with respect to Ni silicide.

  (29) The method for manufacturing a semiconductor device according to item 26, 27 or 28, wherein the diffusion prevention film is made of a material mainly containing TiN or TaN.

  (30) The method for manufacturing a semiconductor device according to any one of items 18 to 29, wherein the heat treatment temperature in the silicidation step is a temperature that does not increase a resistance value of the metal silicide formed in the diffusion region of the transistor.

  According to the present invention, in a field effect transistor structure in which a gate electrode made of metal silicide is provided on a high dielectric constant insulating film, a wide effective work number control range can be obtained, and fine adjustment of an effective work function value can be obtained. Is possible. Thereby, a semiconductor device set to a desired threshold value can be provided.

  More specifically, a high dielectric constant gate insulating film (for example, HfSiON film) is used, and a silicide layer region including an effective work function adjusting metal M2 (for example, W) is formed on the lower layer side of the gate electrode in contact with the gate insulating film. In the structure in which the silicide layer of the metal M1 is formed, (1) the combination of M1 and M2, (2) the composition ratio of the silicide layer region including M2, and (3) the thickness of the silicide layer region including M2 The effective work function of the silicide gate electrode can be controlled by adjusting these three parameters.

  As a result, it is possible to provide a device having a metal gate electrode and a high dielectric constant gate insulating film that is highly consistent with conventional processes, easy to manufacture, and has high performance and excellent reliability.

  Embodiments of the present invention will be described below with reference to the drawings.

  The main feature of the present invention is that, in a field effect transistor structure in which a metal silicide gate electrode is formed on a gate insulating film, Si and a metal M1 are interposed between the gate insulating film and a silicide electrode layer made of a silicide of the metal M1. It has a silicide layer region (hereinafter referred to as “adjustment silicide layer” as appropriate) made of ternary silicide including the effective work function adjustment metal M2. The adjustment silicide layer is provided in contact with the gate insulating film and the upper silicide electrode layer. With such a structure, the effect of the conventional silicide technology can be obtained, and a transistor set to a desired effective work function can be provided. In particular, by using a high dielectric constant insulating film as the gate insulating film and using nickel (Ni) as the silicide metal M1, silicide technology (so-called phase control) that can control the composition in a self-aligned manner by using the formation of a crystal layer. It is possible to provide a high-performance and highly reliable transistor set to a desired effective work function while ensuring the stability of the effective work function obtained by the full silicide technology.

FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device of the present invention. In the figure, reference numerals are 1 for a silicon substrate, 2 for an element isolation region, 3a for a SiO ₂ film, 3b for a HfSiON film, 4 for an extension diffusion region, 5 for a source / drain diffusion region, 6 for a silicide layer, 7 Denotes a gate sidewall, 8 denotes a silicide electrode layer, 9 denotes an interlayer insulating film, and 10 denotes an adjustment silicide layer.

In the present embodiment, as shown in FIG. 1, a gate insulating film composed of an SiO ₂ film 3a and an HfSiON film 3b is formed on a silicon substrate 1 in a channel region of a transistor, and a silicide electrode layer 8 and an adjustment silicide are formed thereon. A gate electrode made of the layer 10 is formed.

  This gate electrode has a two-layer structure, and the upper layer portion of the gate electrode is composed of a metal silicide layer 8 whose crystal phase is controlled by the phase-controlled full silicide technique. The lower layer portion of the gate electrode in contact with the gate insulating film is the gate electrode. It comprises a metal of the same type as the silicide metal constituting the upper layer portion, an effective work function adjusting metal, and a ternary adjusting silicide layer 10 containing Si.

  When such a gate stacked structure is used, a high dielectric constant material is used as the gate insulating film, that is, a technique of forming the gate insulating film with a high dielectric constant material and a phase-controlled full silicide technique of the gate electrode. To use. This is because the phase control full silicide technology can control the effective work function in a wider range by using a high dielectric constant material for the gate insulating film (see Non-Patent Document 4).

The high dielectric constant material used for the gate insulating film in the present invention is a material having a relative dielectric constant larger than that of SiO ₂ (3.6), and is a metal in which metal oxide, metal silicate, and nitrogen are introduced. Examples thereof include metal silicates into which oxides and nitrogen are introduced. A high dielectric constant material into which nitrogen is introduced is preferable in that crystallization is suppressed and reliability is improved. The metal in the high dielectric constant material is preferably Hf or Zr from the viewpoint of heat resistance of the film and suppression of fixed charges in the film. As such a high dielectric constant material, a metal oxide containing Hf or Zr and Si, a metal oxynitride further containing nitrogen in the metal oxide is preferable, HfSiO, HfSiON is more preferable, and HfSiON is more preferable. .

  The gate insulating film in the present invention includes an insulating film (high dielectric constant insulating film) made of a high dielectric constant material, and is laminated on the high dielectric constant insulating film alone, or a silicon oxide film or a silicon oxynitride film. A laminated film including the high dielectric constant insulating film formed can be used.

  The high dielectric constant insulating film is preferably provided so as to be in contact with the gate electrode. The threshold voltage of the transistor can be controlled by a combination of the gate electrode and the high dielectric constant insulating film in contact with the gate electrode. At this time, in order to reduce the interface state at the interface between the silicon substrate and the gate insulating film and to reduce the influence of the fixed charge in the high dielectric constant insulating film, a silicon oxide film or A silicon oxynitride film may be provided.

  The high dielectric constant insulating film preferably has a molar ratio (atomic ratio) Mi / (Mi + Si) between a metal element Mi (for example, Hf) and Si in the film of 0.3 to 0.7. When this ratio is 0.3 or more, the leakage current flowing in the high dielectric constant insulating film during device operation can be effectively suppressed, and the power consumption can be more sufficiently reduced. On the other hand, when this ratio is 0.7 or less, the heat resistance of the high dielectric constant insulating film can be secured, the crystallization of the high dielectric constant insulating film during the device manufacturing process can be suppressed, and the performance as a gate insulating film is deteriorated. Can be suppressed.

  As the silicide metal constituting the gate electrode, a metal that forms silicide by the salicide technique can be used, and examples thereof include Ni, Ta, Pt, Co, Ti, Hf, V, Cr, Zr, and Nb. Among these, Ni is preferable. Ni can fully silicide the entire gate electrode at a relatively low temperature (in the range of 350 to 500 ° C.). Therefore, an increase in the resistance value of the metal silicide formed in the contact region of the source / drain diffusion region can be suppressed. Further, Ni can form both a crystal phase having a high Si concentration and a crystal phase having a high Ni concentration within such a temperature range. Furthermore, in the silicidation of silicon for forming the gate electrode, the NiSi composition of the electrode is determined in a self-aligning manner, the composition becomes stable, and process variations can be suppressed.

  The adjustment silicide layer provided on the lower side of the gate electrode in contact with the gate insulating film contains an effective work function adjusting metal in order to adjust the effective work function of the gate electrode. As the effective work function adjusting metal, when the effective work function of the gate electrode is desired to be shifted in the conduction band direction, a metal having a work function smaller than a metal (for example, Ni) used for full silicidation is adopted. On the other hand, when it is desired to shift in the valence band direction, a metal having a work function larger than that of the metal used for full silicidation (for example, Ni) is employed. The work function of the silicide depends on the work function of the metal contained in the silicide, and the work function of the ternary silicide containing two kinds of silicide metals and Si depends on the mixing ratio of the two kinds of metals. The metal can be selected on the basis. For example, the effective work function adjusting metal that shifts the effective work function of the gate electrode in the conduction band direction includes Ta, Ti, Hf, Zr, W, V, and the like. On the other hand, examples of the work function adjusting metal that shifts the effective work function of the gate electrode in the valence band direction include Pt, Co, Mo, Ni, Pd, Ru, Ir, and Re.

  The adjustment silicide layer is preferably made of a metal silicide layer having a melting point higher than that of the silicide layer provided thereon, and more preferably made of metal silicide having a melting point of 1100 ° C. or higher. When the silicide layer provided on the adjustment silicide layer is formed, diffusion of the effective work function adjustment metal is suppressed, and a desired adjustment silicide layer can be easily formed. As a metal for forming such a metal silicide layer, W, Mo, Ta, and Ti can be suitably used.

  In the composition of the ternary silicide constituting the adjustment silicide layer, the ratio of the effective work function adjustment metal is preferably 10 mol% (atomic%) or more, more preferably 20 mol% or more, and particularly preferably 30 mol% or more. . Within this range, the ternary silicide containing the effective work function adjusting metal is less likely to cause phase separation during the manufacturing process, resulting in a uniform composition, and as a result, variations in the threshold voltage Vth of the transistor can be suppressed. On the other hand, the proportion of the effective work function adjusting metal is preferably 50 mol% (atomic%) or less, more preferably 40 mol% or less, and particularly preferably 35 mol% or less. Within this range, the composition of the fully silicided metal (eg, Ni) in the ternary silicide is sufficiently maintained, and a sufficient control width of the effective work function can be secured.

Suitable adjusting silicide layer, a silicide made of nickel and the effective work function adjusting metal M and silicon in the P-type _{MOSFET, Ni x M y Si 1} -xy (0 ≦ x <1,0 <y <1 , 0 <x + y <1), preferably satisfies x + y ≧ 0.55, more preferably satisfies x + y> 0.6, and particularly preferably satisfies x + y> 0.7. . On the other hand, in the N-type MOSFET, a Ni _x M _y Si _1-xy has a composition represented by (0 ≦ x <1,0 <y <1,0 <x + y <1), x + y <0.55 It is preferable to satisfy. In the P-type MOSFET and the N-type MOSFET, the atomic ratio y of the effective work function adjusting metal M is preferably y ≧ 0.1, more preferably y ≧ 0.2, and y ≧ 0.3 as described above. Particularly preferred, y ≦ 0.5 is preferred, y ≦ 0.4 is more preferred, and y ≦ 0.35 is particularly preferred.

  The thickness of the adjusting silicide layer is preferably 5 nm or less, and more preferably 3 nm or less. The thickness of the adjustment silicide layer is the length of the region including the effective work function adjustment metal in the thickness direction (perpendicular to the substrate) (based on the interface between the adjustment silicide layer and the gate insulating film). . At the metal-semiconductor interface or metal-metal interface, the oozing of the wave function occurs. This amount of oozing out attenuates exponentially in proportion to the distance from the interface, and takes into account a negligible level at about 5 nm, considering the influence of roughness at the interface. Therefore, when the thickness of the adjusting silicide layer is 5 nm or less, the effective work function modulation effect of the gate electrode appears due to the oozing out effect of the wave function on the upper part of the electrode, and the effective amount of the gate electrode is changed by changing the oozing amount. The work function can be controlled. If the thickness of the adjusting silicide layer is 3 nm or less, the effect of seeing out the wave function from the upper part of the silicide electrode can be sufficiently obtained. If the thickness of the adjusting silicide layer is 3 nm or less, the burden of dry etching in the processing of the gate electrode can be reduced. The thickness of the adjusting silicide layer is preferably 1 nm or more, and more preferably 2 nm or more from the viewpoint of obtaining uniformity of thickness and sufficient effects.

The nickel silicide suitable for the silicide electrode layer on the adjustment silicide layer preferably has a composition represented by Ni _z Si _1-z (0.55 ≦ z <1) in the P-type MOSFET, and further 0 More preferably, 0.6 <z <0.8 is satisfied, and 0.7 <z <0.8 is particularly preferable. On the other hand, the N-type MOSFET preferably has a composition represented by Ni _z Si _1-z (0 <z <0.55), and more preferably satisfies 0.3 <z <0.55. It is particularly preferable that 0.3 <z <0.35 or 0.45 <z <0.55 is satisfied. That is, the silicide electrode layer of the P-type MOSFET is preferably made of silicide containing a Ni ₃ Si phase as a main component, and the silicide electrode layer of the N-type MOSFET is made of silicide containing a NiSi phase or a NiSi ₂ phase as a main component. It is preferable. The crystalline phase of nickel silicide is mainly classified into NiSi ₂ , NiSi, Ni ₃ Si ₂ , Ni ₂ Si, and Ni ₃ Si, and a mixture thereof can also be formed.

In this specification, “high dielectric constant” (High-k) is generally used to distinguish from an insulating film made of silicon dioxide (SiO ₂ ), which has been conventionally used as a gate insulating film. This means that the dielectric constant is generally higher than that of silicon dioxide, and the specific numerical values are not particularly limited.

  In this specification, the “effective work function” of the gate electrode is generally obtained from a flat band obtained by CV measurement between the gate insulating film and the gate electrode. It is affected by fixed charges in the film, dipoles formed at the interface, and Fermi level pinning. It is distinguished from the original “work function” of the material constituting the gate electrode.

  Hereinafter, embodiments of the present invention will be further described with reference to the drawings.

  4a to 4j are process cross-sectional views illustrating an embodiment of a method for manufacturing a MOSFET according to the present invention.

  First, as shown in FIG. 4a, an element isolation region 2 was formed on the surface region of the silicon substrate 1 by using STI (Shallow Trench Isolation) technology.

Subsequently, a gate insulating film 3 (SiO ₂ film 3a and HfSiON film 3b) was formed on the surface of the silicon substrate where the elements were separated. In the gate insulating film of this embodiment, the Hf concentration in the gate insulating film varies in the depth direction (perpendicular to the substrate), and the Hf concentration in the vicinity of the interface between the gate electrode and the gate insulating film is the highest. The concentration decreases toward the silicon substrate side, and the region of the HfSiON film 3b in which the average Hf molar ratio (atomic ratio) Hf / (Hf + Si) in the HfSiON film is 0.5, and the silicon substrate and the gate insulating film It is formed from a region of a silicon thermal oxide film (SiO ₂ film 3a) near the interface. Such a gate insulating film was formed as follows. First, a 1.9 nm thick silicon thermal oxide film was formed, and then a 0.5 nm thick hafnium (Hf) film was deposited by a long throw sputtering method. Next, a two-step heat treatment is performed in oxygen at 500 ° C. for 1 minute and then in nitrogen at 800 ° C. for 30 seconds, so that the SiO ₂ film 3a remains in a region in contact with the silicon substrate. An HfSiO film was formed by solid-phase diffusion into the oxide film. Thereafter, nitridation annealing was performed in an NH ₃ atmosphere at 900 ° C. for 10 minutes to obtain an HfSiON film 3b.

  Next, a tungsten silicide layer (W silicide layer) 10 was deposited on the HfSiON film 3b by a CVD (Chemical Vapor Deposition) method. The W silicide layer 10 has a melting point of 1100 ° C. or higher and a thickness of 3 nm. Further, the tungsten (W) content in the W silicide layer was set to a molar ratio (atomic ratio) W / Si = 1/2. Tungsten employed in this embodiment can shift the effective work function of the gate electrode in the conduction band direction.

  Next, a Si film 13 having a thickness of 10 nm is deposited on the W silicide layer 10 by sputtering, and then a polycrystalline silicon film (poly-Si film) 14 having a thickness of 80 nm and a silicon oxide film 15 having a thickness of 10 nm are formed. .

  Next, as shown in FIG. 4B, the laminated film on the silicon substrate was processed into a gate electrode pattern by using a lithography technique and an RIE (Reactive Ion Etching) technique. Subsequently, ion implantation was performed using the gate electrode pattern as a mask to form the extension diffusion region 4 in a self-aligning manner.

  Next, as shown in FIG. 4c, a silicon oxide film was deposited and then etched back to form gate sidewalls 7. Next, ion implantation was performed again, and then activation annealing was performed to form the source / drain diffusion regions 5.

  Next, as shown in FIG. 4d, a 20 nm thick metal film 23 was deposited on the entire surface by sputtering. Next, as shown in FIG. 4e, a silicide layer 6 having a thickness of about 40 nm was formed only in the source / drain diffusion region by the salicide technique using the gate electrode, the gate sidewall film and the element isolation region as a mask. In the present embodiment, a Ni monosilicide (NiSi) layer that can have the lowest contact resistance is formed as the silicide layer 6. A Co silicide layer or a Ti silicide layer may be formed instead of the Ni monosilicide layer.

  Next, as shown in FIG. 4f, an interlayer insulating film 9 made of a silicon oxide film was formed by a CVD (Chemical Vapor Deposition) method. Next, the surface of the interlayer insulating film 9 is flattened by a CMP (Chemical Mechanical Polishing) technique, and subsequently, as shown in FIG. 4G, the interlayer insulating film is etched back to form a poly-Si film 14 having a gate electrode pattern. Was exposed.

  Next, as shown in FIG. 4h, a first metal film 16 (Ni film) for siliciding the poly-Si film 14 of the gate electrode pattern was formed. The first metal film 16 was formed at room temperature by DC magnetron sputtering and the thickness was 55 nm. Since nickel (Ni) can be silicided at 500 ° C. or lower, the poly-Si film 14 is completely formed at a temperature at which the resistance value of the silicide layer 6 (NiSi layer) already formed in the source / drain diffusion region 5 does not increase any more. Can be silicided.

The thickness of the Ni film (first metal film 16) in this step is as follows: Ni, Si contained in the upper part of the gate electrode pattern (poly-Si film 14), and Si contained in the lower part of the gate electrode pattern (W silicide layer 10). And the composition of the lower part of the gate electrode becomes Ni _x W _y Si _1-xy (x + y <0.55), and the composition of the upper part of the gate electrode becomes Ni _z Si _1-z ( It is preferable to set the film thickness such that z <0.55). More preferably, the composition under the gate electrode is Ni _x W _y Si _1-xy (x + y <0.55), and the film thickness is set such that the upper part of the gate electrode contains a NiSi phase or a NiSi ₂ phase as a main component. To do.

  Next, a diffusion prevention layer 17 (TiN film) for preventing Ni diffusion was formed on the entire surface. The diffusion prevention layer was formed by reactive sputtering at 300 ° C. and the thickness was 20 nm. The diffusion prevention layer 17 is made of a material that can prevent diffusion of the metal for silicidation and is stable in the heat treatment step for siliciding Si of the entire gate electrode pattern. Further, it is preferable that the diffusion prevention layer 17 is made of a material that can be selectively etched with respect to the metal for silicidation and the interlayer insulating film, from the standpoint of manufacturing the element.

  Next, as shown in FIG. 4i, the diffusion prevention layer 17 (TiN film) is patterned by using the lithography technique and the RIE technique, and the diffusion prevention layer 17 on the first metal film 16 (Ni film) in the P-type MOSFET region. Only (TiN film) was removed. Thereafter, a second metal film 22 (Ni film) of the same type as the first metal film 16 was formed on the entire surface. The second metal film 22 (Ni film) was formed at room temperature by a DC magnetron sputtering method, and the thickness was 100 nm. Therefore, the Ni film having a total thickness of 155 nm is involved in the silicidation reaction on the gate insulating film in the P-type MOSFET region, whereas the 55 nm-thickness below the diffusion prevention layer 17 is formed on the gate insulating film in the N-type MOSFET region. Only the Ni film is involved in the silicidation reaction.

The film thickness of the second metal film 22 (Ni film) in this step is as follows: Si contained in the upper part of the gate electrode pattern (poly-Si film 14), Si contained in the lower part of the gate electrode pattern (W silicide layer 10), and When the Ni of the first metal film 16 and the second metal film 22 sufficiently react with each other to be silicided, the composition below the gate electrode becomes Ni _x W _y Si _1-xy (x + y ≧ 0.55), and the gate It is preferable to set the film thickness such that the composition of the upper part of the electrode is Ni _z Si _1-z (z ≧ 0.55). More preferably, the composition is such that the composition of the lower part of the gate electrode is Ni _x W _y Si _1-xy (x + y ≧ 0.55), and the upper part of the gate electrode contains a Ni ₃ Si phase as a main component.

  Next, heat treatment for silicidation of the poly-Si film 14, the first metal film 16, and the second metal film 22 on the gate insulating film was performed. This heat treatment is required to be in a non-oxidizing atmosphere in order to prevent oxidation of the first and second metal films. Further, this heat treatment provides a sufficient diffusion rate for silicidation of the sputtered Si film 13 and the poly-Si film 14 on the gate insulating film, and the silicide layer 6 formed in the source / drain diffusion region 5. Must be performed at a temperature at which the resistance does not become high. In this embodiment, since both the silicide of the silicide layer 6 formed in the source / drain diffusion region 5 and the silicide formed on the gate insulating film are Ni, the temperature is set to 450 ° C. for 2 minutes in a nitrogen gas atmosphere. If the silicide of the silicide layer 6 formed in the source / drain diffusion region 5 is Co silicide or Ti silicide, a higher temperature region, for example, about 800 ° C. is allowed.

By this heat treatment, the Ni film (first metal film 16) having a thickness of 55 nm reacts with Si in the gate electrode pattern (sputtered Si film 13, poly-Si film 14 and W silicide layer 10) in the N-type MOSFET region. Silicidation is performed up to just above the gate insulating film 3. On the other hand, in the P-type MOSFET region, the Ni film having a thickness of 155 nm reacts with Si in the gate electrode pattern (sputtered Si film 13, poly-Si film 14 and W silicide layer 10) to be silicided to the position just above the gate insulating film 3. The In the P-type MOSFET region, since the amount of Ni that can be supplied to the poly-Si film 14 having the same thickness as that of the N-type MOSFET region is large, the Ni concentration is higher than that of the upper gate electrode (Ni silicide electrode 19) in the N-type MOSFET region. An upper gate electrode (Ni silicide electrode 18) having a high height is formed. In the Ni film thickness of this embodiment, according to X-ray diffraction (XRD) measurement and Rutherford backscattering (RBS) measurement, the upper part of the gate electrode (Ni silicide electrode 19) in the N-type MOSFET region is a NiSi single phase, Its Ni / (Ni + Si) composition ratio (atomic ratio) was about 0.5. On the other hand, the upper part of the gate electrode (Ni silicide electrode 18) in the P-type MOSFET region was a Ni ₃ Si single phase, and its Ni / (Ni + Si) composition ratio (atomic number ratio) was about 0.75.

The Ni ₃ Si phase can be easily formed by setting the ratio of the thickness t1 of the Ni film involved in silicidation to the thickness T of the laminated film of the gate electrode pattern in the range of t1 / T ≧ 1.64. it can. On the other hand, in the NiSi phase or the NiSi ₂ phase, the ratio of the thickness t2 of the Ni film involved in silicidation and the thickness T of the laminated film of the gate electrode pattern is set in the range of 0.28 ≦ t / T ≦ 0.95. It can be formed more easily. In particular, the NiSi ₂ layer can be easily formed by setting 0.28 ≦ t / T ≦ 0.54 and the NiSi phase by setting 0.55 ≦ t / T ≦ 0.95.

  Finally, excess Ni film and TiN film that did not undergo silicidation reaction in the heat treatment were removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide solution. Note that no peeling of the silicide electrode was observed through the above steps.

  Through the above steps, MOSFETs having different gate electrode structures were formed in the N-type MOSFET region and the P-type MOSFET region as shown in FIG. In this MOSFET, Ni silicide layers 18 and 19 having different crystal phases are formed on the upper layer side of the gate electrode, and Ni silicide layers 20 and 21 having different compositions including W are formed on the lower layer side of the gate electrode. Yes. The silicide layers 20 and 21 below the gate electrode are adjustment silicide layers, and the thickness thereof is about 3 nm, which is substantially the same as that of the W silicide layer 10.

Tungsten (W) contained in the lower part of the gate electrode (adjustment silicide layer) of the obtained MOSFET is a work function adjustment metal and has a work function smaller than that of nickel (Ni). Therefore, the Ni silicide electrode containing W is affected by the work function of W and the effective work function is shifted toward the conduction band as compared with the Ni silicide electrode not containing W. FIG. 5 shows the change of the effective work function of the Ni silicide electrode obtained by the conventional phase control Ni silicide technique on HfSiON with respect to the Ni composition and the change of the effective work function of the Ni silicide electrode of the present invention with respect to the Ni composition. As shown in this figure, the effective work function of the gate electrode having the upper portion of the Ni ₃ Si electrode and the gate electrode having the upper portion of the NiSi electrode is 4.75 eV under the influence of W of the adjusting silicide layer below the electrode. It can be seen that Ei ± 0.15 eV can be realized. The value of the effective work function is an optimum value for a LOP (Low Operation Power) device of Vth ± 0.5 eV.

  As described above, according to the present embodiment, by forming a thin silicide layer of 5 nm or less containing a work function adjusting metal on the high dielectric constant film, fine adjustment of the effective work function is facilitated, and desired An effective work function can be realized, and as a result, the design range of Vth can be expanded.

  The Ni silicide gate electrode having a region containing the work function adjusting metal (adjustment silicide layer) below the gate electrode in contact with the gate insulating film has an effective work function value of (1) silicide metal of the adjustment silicide layer. It is governed by three parameters: type (difference in work function), (2) composition, and (3) thickness. That is, the present invention is based on the following three findings. (1) Realization of an intermediate value of effective work functions of two kinds of metal silicides by combining two kinds of metals having different work functions. (2) Effective work function adjustment by composition change of three kinds of elements (work function adjusting metal, Ni, Si). (3) A change in the amount of oozing of the wave function from the upper silicide electrode due to a change in the thickness of the adjustment silicide layer below the gate electrode. As shown in FIG. 5, in the gate electrode of the present invention in which the WNi silicide layer is provided below the gate electrode, the effective work function on HfSiON is shifted in the conduction band direction as compared with the conventional Ni silicide electrode. This is because the work function of W is smaller than that of Ni and the work function at the gate electrode / HfSiON interface changes under the influence of W.

  FIG. 6 shows a change in the composition of the W silicide film for forming the silicide layer for adjusting the effective work function in the MOSFET manufactured according to the method of the above embodiment using tungsten (W) as the work function adjusting metal. The effective work function of the gate electrode formed on HfSiON is shown. When an appropriate amount of W is present in the W silicide film, the effective work function is shifted in the conduction band direction due to Fermi pinning generated at the HfSiON / WNi silicide interface. As the W concentration decreases, the composition of the ternary adjustment silicide layer approaches the composition of the conventional Ni silicide electrode, and the shift amount of the effective work function decreases.

  FIG. 7 shows a case where W is used as the work function adjusting metal and the thickness of the W silicide film for forming the effective work function adjusting silicide layer is changed in the MOSFET manufactured according to the method of the above-described embodiment. 3 shows changes in the effective work function of the gate electrode formed on HfSiON. When the W silicide film thickness is 5 nm or less, particularly 3 nm or less, the effect of seeping out of the wave function from the upper part of the Ni silicide electrode is produced, and the value of the effective work function with the decrease in the W silicide film thickness is the conventional Ni It changes so as to approach the value of the silicide electrode.

  Thus, according to this embodiment, the threshold value (Vth) can be set according to the range of the effective work function shown in FIGS. 6 and 7, and the gate stack technology of the metal gate and the high dielectric constant film can be realized. It becomes possible to apply to a wide range of devices.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be implemented by selecting materials and structures without departing from the spirit of the present invention. is there. For example, the silicide film formed on the gate insulating film is not limited to tungsten (W) as long as the gate insulating film does not deteriorate during the process. When a larger work function adjustment width is required, it is effective to employ a metal having a large work function difference with respect to the silicide metal (Ni) constituting the main component of the gate electrode. Also, the silicide metal (Ni), which is the main component of the gate electrode, differs between the P-type MOSFET and the N-type MOSFET as long as the contact resistance of the source / drain region and the impurity profile of the diffusion region are not deteriorated in the full silicidation process. It is not limited to Ni as long as a crystal phase having a composition can be formed.

As another embodiment, in the P-type MOSFET region, the Ni silicide layer on the upper side of the gate electrode includes a Ni ₃ Si phase or a NiSi phase as a main component, and the adjustment silicide layer includes a metal having a work function larger than that of Ni and Ni In the N-type MOSFET region, the gate electrode upper layer may include Si as a main component, and the adjustment silicide layer may include a metal silicide layer having a work function larger than that of Ni. This embodiment can be formed by providing a mask in the N-type MOSFET region without forming a Ni film for silicidation, forming a Ni film only in the P-type MOSFET region, and performing silicidation. Also in such an embodiment, an effective work function suitable for an LOP device in which Vth is set to ± 0.5 V can be realized as in the above-described embodiment.

It is sectional drawing which shows embodiment of the semiconductor manufacturing apparatus which concerns on this invention. It is sectional drawing of the conventional semiconductor device. It is a graph which shows the change of the effective work function with respect to the composition of the Ni silicide electrode on a HfSiON film | membrane in a prior art. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is process sectional drawing which shows embodiment of the manufacturing method of the semiconductor device which concerns on this invention. It is a figure which shows the change with respect to Ni composition of the effective work function of the gate electrode on HfSiON about the semiconductor device produced according to embodiment of this invention and a prior art. It is a figure which shows the change with respect to W composition of the W silicide film | membrane formed under the gate electrode of the effective work function of the gate electrode on HfSiON about the semiconductor device produced according to embodiment of this invention. It is a figure which shows the change with respect to the film thickness of the W silicide film | membrane formed in the gate electrode lower part of the effective work function of the gate electrode on HfSiON about the semiconductor device produced according to embodiment of this invention.

Explanation of symbols

1 silicon substrate 2 isolation region 3 gate insulating film 3a SiO ₂ film 3b HfSiON film 4 extension diffusion region 5 a source-drain diffusion region 6 silicide layer 7 gate sidewall 8 silicide electrode layer 9 interlayer insulating film 10 W silicide layer 11 P-doped NiSi Electrode 12 B-doped NiSi electrode 13 Sputtered Si film 14 Polycrystalline silicon film (poly-Si film)
15 SiO ₂ film 16 First metal film 17 Diffusion prevention layer 18 Upper gate electrode (Ni _x Si _1-x (0.55 ≦ x <1))
19 Upper gate electrode (Ni _x Si _1-x (0 <x ≦ 0.55))
20 Lower gate electrode (Adjustment silicide layer: Ni _x W _y Si _1-xy (x + y ≧ 0.55))
21 Lower gate electrode (Adjustment silicide layer: Ni _x W _y Si _1-xy (x + y ≦ 0.55))
22 Second metal film 23 Metal film for silicide

Claims (30)

In a semiconductor device including a field effect transistor having a gate insulating film and a gate electrode provided on the gate insulating film on a silicon substrate,
The gate insulating film has a high dielectric constant insulating film made of metal oxide, metal silicate, or metal oxide or metal silicate into which nitrogen is introduced;
The gate electrode is provided on the lower layer side in contact with the high dielectric constant insulating film, and includes a first metal M1, a second metal M2 having a work function different from that of M1, and a first silicide made of silicon (Si). possess a layer region of, provided on an upper layer side in contact with the first layer region, and a second layer region formed of a silicide containing M1 and Si,
The first metal M1 is nickel (Ni), and the first layer region is made of silicide having a composition represented by Ni _x M2 _y Si _1-xy (x + y ≧ 0.55), and the second layer region Is made of silicide containing a Ni ₃ Si phase as a main component,
The thickness of the first layer region is 5 nm or less;
A semiconductor device, wherein the field effect transistor is a P-channel transistor . The semiconductor device according to claim 1, wherein the thickness of the first layer region is 1 nm or more . The semiconductor device according to claim 1, wherein the second metal M2 is W, Mo, Ta, or Ti . A semiconductor device comprising a field effect transistor having a gate insulating film and a gate electrode provided on the gate insulating film on a silicon substrate,
The gate insulating film has a high dielectric constant insulating film made of metal oxide, metal silicate, or metal oxide or metal silicate into which nitrogen is introduced;
The gate electrode, the high dielectric constant provided on the lower side in contact with the insulating film includes a nickel metal M and silicon having a different work function (Ni) (Si), Ni x M y Si 1-xy (0 A first layer region having a composition represented by ≦ x <1, 0 <y <1, 0 <x + y <1), and Ni _z Si ₁₋ provided on the upper layer side in contact with the first layer region _a second layer region having a composition represented by _z (0 ≦ z <1),
The field effect transistor includes a P-channel transistor and an N-channel transistor in which at least the composition of the second layer region is different from each other. The P-channel transistor satisfies x + y ≧ 0.55 and z ≧ 0.55, and N in channel transistor meets the x + y <0.55, z < 0.55, the semiconductor device thickness of the first layer region is 5nm or less. In the P-channel transistor, the second layer region of the gate electrode is made of silicide containing a Ni ₃ Si phase as a main component,
5. The semiconductor device according to claim 4, wherein the second channel region of the gate electrode of the N-channel transistor is made of silicide containing a NiSi phase or a NiSi ₂ phase as a main component.   6. The semiconductor device according to claim 4, wherein the composition of the first layer region satisfies 0 <x <1, 0 <y ≦ 0.5. In the P-channel transistor, the second layer region of the gate electrode is made of silicide containing a Ni ₃ Si phase as a main component,
5. The N-channel transistor according to claim 4, wherein the second layer region of the gate electrode includes Si as a main component, and the composition of the first layer region satisfies x = 0 and 0 <y ≦ 0.5. Semiconductor device. In the P-channel transistor, the second layer region of the gate electrode is made of silicide containing a NiSi phase as a main component,
5. The N-channel transistor according to claim 4, wherein the second layer region of the gate electrode includes the Si main component, and the composition of the first layer region satisfies x = 0 and 0 <y ≦ 0.5. Semiconductor device.   9. The semiconductor device according to claim 7, wherein a composition of the first layer region of the P-channel transistor satisfies 0 <x <1, 0 <y ≦ 0.5.   10. The semiconductor device according to claim 1, wherein T1 <T2 when the thickness of the first layer region is represented by T1 and the thickness of the second layer region is represented by T2. The thickness of the first layer region is T1, when the thickness of the second layer region is represented by T2, T1 <T2, and, according to any one of claims 1 to 9 which is 1nm ≦ T1 ≦ 3 nm Semiconductor device.   The semiconductor device according to claim 4, wherein the metal M is a metal capable of forming a refractory metal silicide having a melting point of 1100 ° C. or higher.   The semiconductor device according to claim 4, wherein the metal M is W, Mo, Ta, or Ti.   The semiconductor device according to claim 1, wherein the high dielectric constant insulating film includes an insulating film containing Hf or Zr.   The semiconductor device according to claim 14, wherein the insulating film containing Hf or Zr is provided in a portion in contact with the gate electrode.   16. The semiconductor device according to claim 1, wherein the gate insulating film has a stacked structure including a silicon oxide film or a silicon oxynitride film and a high dielectric constant insulating film containing Hf or Zr.   The semiconductor device according to claim 1, comprising an HfSiON film as the high dielectric constant insulating film. A method of manufacturing a semiconductor device according to claim 1,
Forming a gate insulating film on the silicon substrate;
A metal-containing film containing the second metal M2 and silicon (Si) is formed on the gate insulating film, and an amorphous silicon film, a polycrystalline silicon film, or a silicon film made of both of them is formed on the metal-containing film. And a process of
Forming a gate pattern by processing the gate insulating film, the metal-containing film and the laminated film including the silicon film;
A film of the first metal M1 is formed on the gate pattern, and heat treatment is performed to silicidize the metal-containing film including the second metal M2 and Si so as to include M1, and the silicon film is formed. Full silicidation step;
A method of manufacturing a semiconductor device, including a step of removing M1 that has not been silicided. A method of manufacturing a semiconductor device according to claim 2,
Forming a gate insulating film on the silicon substrate;
A metal-containing film containing the second metal M2 and silicon (Si) is formed on the gate insulating film, and an amorphous silicon film, a polycrystalline silicon film, or a silicon film made of both of them is formed on the metal-containing film. And a process of
Forming a gate pattern by processing the gate insulating film, the metal-containing film and the laminated film including the silicon film;
A nickel (Ni) film is formed on the gate pattern, and heat treatment is performed to silicide the metal-containing film containing the second metal M2 and Si so as to contain Ni, and the silicon film is fully silicided. The process of
Removing Ni that has not been silicided,
In the silicidation step, the second layer region of the gate electrode contains Ni ₃ Si phase as a main component, and the composition of the first layer region is Ni _x M2 _y Si _1-xy (x + y ≧ 0.55). Thus, the manufacturing method of the semiconductor device which sets the thickness of the Ni film. A method of manufacturing a semiconductor device according to claim 4,
Forming a gate insulating film on the silicon substrate;
Forming a metal-containing film containing metal M and silicon (Si) on the gate insulating film, and forming a silicon film made of an amorphous silicon film or a polycrystalline silicon film or both on the metal-containing film; ,
Forming a gate pattern by processing the gate insulating film, the metal-containing film and the laminated film including the silicon film;
Forming a nickel (Ni) film on the gate pattern, performing a heat treatment to silicide the metal-containing film containing the metal M and Si so as to contain Ni, and to fully silicide the silicon film; When,
Removing Ni that has not been silicided,
In the silicidation step, the thickness of the Ni film on the P-channel region and the N-channel region so that the composition of the gate electrode of the P-channel transistor and the composition of the gate electrode of the N-channel transistor become the predetermined composition. Semiconductor device manufacturing method for setting the thickness of the Ni film. A method of manufacturing a semiconductor device according to claim 5,
In the silicidation process, in the P channel region, the thickness of the Ni film is set so that the second layer region contains Ni ₃ Si phase as a main component and the composition of the first layer region satisfies x + y ≧ 0.55. In the N channel region, the thickness of the Ni film is set so that the second layer region is mainly composed of a NiSi phase or a NiSi ₂ phase, and the composition of the first layer region satisfies x + y <0.55. 20. A method for manufacturing a semiconductor device according to 20. A method of manufacturing a semiconductor device according to claim 7,
In the silicidation process, in the P channel region, the thickness of the Ni film is set so that the second layer region contains Ni ₃ Si phase as a main component and the composition of the first layer region satisfies x + y ≧ 0.55. 21. In the N channel region, the second layer region contains Si as a main component, and the Ni film is not provided so that the composition of the first layer region satisfies x = 0 and y ≦ 0.5. Semiconductor device manufacturing method. A method for manufacturing a semiconductor device according to claim 8, comprising:
In the silicidation step, in the P channel region, the thickness of the Ni film is set so that the second layer region contains NiSi phase as a main component and the composition of the first layer region satisfies x + y ≧ 0.55, and N 21. The semiconductor according to claim 20, wherein in the channel region, the second layer region contains Si as a main component, and the Ni film is not provided so that the composition of the first layer region satisfies x = 0 and y ≦ 0.5. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 19, wherein a ratio between the thickness t of the Ni film and the thickness T of the laminated film of the metal-containing film and the silicon film is t / T ≧ 1.64. In the P channel region, the ratio between the thickness t1 of the Ni film and the thickness T of the laminated film of the metal-containing film and the silicon film is t1 / T ≧ 1.64,
The ratio of the thickness t2 of the Ni film and the thickness T of the stacked film of the metal-containing film and the silicon film is set to 0.28 ≦ t2 / T ≦ 0.95 in the N channel region. The manufacturing method of the semiconductor device as described in any one of.   In the silicidation step, after forming the first Ni film on the N channel region and the P channel region, a diffusion prevention film stable to Ni is formed only on the N channel region, and then the P channel region is formed. 26. The method of manufacturing a semiconductor device according to claim 20, 21 or 25, wherein a second Ni film is formed on the entire surface including the element to control the thickness of the Ni film involved in silicidation.   24. The semiconductor device according to claim 22, wherein in the silicidation step, a diffusion prevention film that is stable against Ni is formed only on the N channel region, and then a Ni film is formed on the entire surface including the P channel region. Manufacturing method.   28. The method of manufacturing a semiconductor device according to claim 26, wherein the diffusion prevention film is made of a material that can be selectively etched with respect to Ni silicide.   29. The method of manufacturing a semiconductor device according to claim 26, 27 or 28, wherein the diffusion preventing film is made of a material mainly composed of TiN or TaN.   30. The method of manufacturing a semiconductor device according to claim 18, wherein the heat treatment temperature in the silicidation step is a temperature that does not increase the resistance value of the metal silicide formed in the diffusion region of the transistor.

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