JP2009038723A - Image display device and image display control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device which adjusts the difference of frequencies between writing video data into and reading it from a memory, and displays high-quality images with a simple structure without adding a structure to determine a reading timing based on a vertical synchronous signal in a memory reading side. <P>SOLUTION: A controller 29 determines whether or not reading operations catch up with writing operations for buffer memories BUF 1 to 4. If determining that the reading operations catch up with the writing operations, the controller 29 controls the next reading timing for the buffer memories BUF 1 to 4. After reading of video data for valid image lines is completed, the controller 29 delays the timing until beginning next reading of the buffer memories BUF 1 to 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image display device and an image display control method for reading out and displaying video data after storing them in a memory.

As shown in FIG. 6, the image display apparatus 101 generates digital video data from the received radio wave received by the antenna 111 via the front end processing unit 113 and the video decoder 115. Then, after writing into the video memory 119 by the video capture 117, the display data synthesizing unit 123 reads out and displays it on the liquid crystal display 127 through the display control unit 125. Such an image display apparatus 101 performs image composition processing such as combining video data and image data generated by the rendering processing of the rendering engine 121 for display.
In such an image display device 101, data writing to the buffer memory BUF in the video memory 119 is performed when the buffer memories BUF 1, BUF 2, BUF 3, BUF 4, BUF 1,. . . The ring method is used in this order. Further, the read operation from the buffer memory BUF starts later than the write operation, and the buffer memories BUF1, BUF2, BUF3, BUF4, BUF1,. . . . In order.

In the example shown in FIG. 6, it is shown that the input side writes data to the buffer memory BUF1, and the display side reads and displays the data of the buffer memory BUF3 written before that.
In the conventional image display device, when the field frequency of the input video signal is different from the frequency on the display output side, the same image (frame) is displayed twice or one image (frame) is skipped and displayed (or input). The video signal is continuously input without being interrupted, for example, by skipping one frame to be displayed).

For example, as shown in FIG. 7A, when the field frequency on the input side is higher than that on the display side and writing catches up with reading, writing to the buffer memory BUF3 is performed as shown in FIG. 7B. The catch-up is prevented by writing again to the buffer memory BUF2.
Further, as shown in FIG. 8A, when the field frequency on the display side is higher than that on the input side and the reading catches up with the writing, the reading from the buffer memory BUF2 is again performed as shown in FIG. 8B. The catch-up is prevented by reading from the buffer memory BUF1.

JP-A-7-295544

However, in the above-described conventional image display device, when displaying a continuous video image, the same image (frame) is displayed twice or frame dropping sometimes occurs. At this time, in the video with continuous motion, there is a problem in the image such as the motion of the image stops for a moment or becomes faster.
If the field frequency is sufficiently high, the above-mentioned image defect cannot be detected by the human eye, but the NTSC (National Television Standards Committee) system with a field frequency of 59.94 Hz, which is an existing television system, or a PAL (Phase
In the Alternating Line) method, the above-mentioned problem is detected depending on the content of the image, which is a problem when high display quality is required.
Such image quality deterioration is particularly noticeable in the case of an interlaced signal because the combination of odd and even fields is lost. It also appears prominently when panning the camera.

In order to solve such a problem, it is only necessary to match the field frequency on the output side with the field frequency on the input side so that catch-up does not occur between the writing side and the reading side.
Conventionally, as shown in FIG. 6, a signal synchronized with the field frequency on the input side, specifically, a vertical synchronization signal is input to the display data synthesis unit 123 (display timing generation circuit), and the readout field frequency on the display side. Has been synchronized to the input side.
However, in recent years, in order to reduce the increase in the number of input pins of hardware circuits, especially LSI (Large Scale Integration), due to a request for price cost reduction, the vertical synchronization signal input pin for external synchronization is omitted or the timing is reduced. It has been carried out that a circuit for synchronous generation is omitted. When it is necessary to use a hardware circuit that does not include such a vertical synchronization signal input pin, the conventional method described above cannot synchronize the display-side readout field frequency to the input side, resulting in display quality. There is a problem that will decrease.

  The present invention has been made in view of such circumstances, and an object of the present invention is to add video to a memory with a simple configuration without adding a configuration for determining a read timing based on a vertical synchronization signal on the read side of the memory. An object of the present invention is to provide an image display apparatus and an image display control method that enable high-quality image display by adjusting the frequency difference between data writing and reading.

  In order to solve the above-described problems of the prior art and achieve the above-described object, an image display device according to the present invention is an image display device that reads and displays video data after storing the data in a memory. A determination unit that monitors an operation of writing the video data to the memory and an operation of reading and displaying the video data from the memory, and determines whether or not the relationship of reading the video data after being written to the memory can be maintained. And when the display frequency for displaying the image according to the video data read from the memory is lowered, the read frequency for reading the video data from the memory is lowered, and the determination means determines that the relationship cannot be maintained. And a control means for controlling the display frequency so that the relationship is maintained.

In the image display device of the present invention, the determination unit monitors the video data writing operation to the memory and the operation of reading and displaying the video data from the memory, and writes the video data to the memory. It is determined whether the relationship to be read later can be held.
Then, the control unit controls the frequency at which an image corresponding to the video data read from the memory is displayed so that the relationship is maintained when the determination unit determines that the relationship cannot be maintained. At this time, the control means lowers the read frequency for reading the video data from the memory as the display frequency for displaying an image corresponding to the video data read from the memory becomes lower.
As described above, the image display apparatus of the present invention can synchronize the frequency on the display side with the frequency of the input video data without using hardware for external synchronization, so that the video data can be reproduced without frame double copying or frame dropping. The image according to can be displayed. Therefore, a high-quality moving image can be provided.

  Preferably, in the image display device according to the present invention, the read frequency is higher than a write frequency for writing the video data to the memory, and a predetermined order in a plurality of predetermined storage areas in the memory. When the video data is written, the determination means can maintain the relationship based on the storage area where the video data is read from the memory and the storage area where the write is being performed. If the control means determines that the relationship cannot be maintained, the number of lines used for displaying one image corresponding to the video data read from the memory is increased to lower the display frequency. To control.

  The image display control method of the present invention is a display control method for reading video data after storing it in a memory, and displaying the video data. The video data write operation to the memory and the video data from the memory are processed. A monitoring step for monitoring an operation to be read and displayed; a determination step for determining whether or not a relationship of reading out the video data after being written into the memory can be maintained based on a monitoring result in the monitoring step; When the display frequency for displaying the image corresponding to the video data read from the memory is lowered, the read frequency for reading the video data from the memory is lowered, and the determination process determines that the relationship cannot be maintained. And a control step of controlling the display frequency so as to be maintained.

  According to the present invention, the frequency difference between writing and reading video data to and from the memory can be adjusted with a simple configuration without adding a configuration for determining the reading timing based on the vertical synchronization signal on the reading side of the memory. Thus, it is possible to provide an image display device and an image display control method that enable high-quality image display.

Hereinafter, an image display apparatus according to an embodiment of the present invention will be described.
FIG. 1 is a functional block diagram of an image display apparatus 1 according to an embodiment of the present invention.
As shown in FIG. 1, the image display apparatus 1 includes, for example, a front-end processing unit 13, a video decoder 15, a video capture 17, a video memory 19, a drawing engine 21, a display data synthesis unit 23, a display control unit 25, and a display 27. And a control unit 29.

  Here, the overtaking determination function of the control unit 29 is an example of the determination means of the present invention. The display control register REG setting function by the control unit 29 and the display control unit 25 are examples of the control means of the present invention. The video memory 19 is an example of the memory of the present invention.

  In FIG. 1, the functions of the video decoder 15, the video capture 17, the drawing engine 21, the display data synthesis unit 23, and the display control unit 25 may be realized as hardware, or some of these functions may be implemented by software. It may be realized with.

First, an outline of features of the image display device 1 will be described.
The control unit 29 of the image display apparatus 1 illustrated in FIG. 1 specifies the buffer memories BUF1 to BUF4 in which video data writing operation is performed based on the writing end notification input from the video capture 17.
In addition, the control unit 29 specifies the buffer memories BUF1 to BUF4 from which video data is being read based on the read end notification input from the display data combining unit 23.
Based on the buffer memories BUF1 to BUF4 in which writing is performed and the buffer memories BUF1 to BUF4 in which reading is performed, the control unit 29 has a relationship of catching up that reading catches up with writing (reading after writing). It is determined whether or not a situation that cannot be maintained occurs.
When it is determined that the catch-up has occurred, the control unit 29 controls the read timing of the next buffer memory BUF1 to BUF4 and reads the video data for the effective image line (displays the image on the liquid crystal display 27). Control is performed so as to delay the timing until the reading of the next buffer memory BUF1 to BUF4 starts after the display from the top to the bottom.
Specifically, the control unit 29 rewrites the display timing value stored in the display control register REG of the display control unit 25.

  As described above, in the image display device 1, the field on the display side is synchronized with the field frequency of the input side (write side) and the display side (read side) with a circuit configuration that does not have hardware for the external synchronization function. Change the frequency. Here, when the display afterimage time is long like the liquid crystal display 27 or the like, even if the field frequency changes slightly, the temporal non-uniformity of brightness and darkness is not perceived, and the image quality is hardly deteriorated.

Hereinafter, each component shown in FIG. 1 will be described in detail.
[Front-end processing unit 13]
The front end processing unit 13 selects a designated channel from the received radio wave received by the antenna 11 and converts it into an intermediate frequency signal.
Then, the front end processing unit 13 amplifies the intermediate frequency signal, and then performs video detection by AFT (Audio Frequency Transformer) detection to extract an analog video signal.
Then, the front-end processing unit 13 performs A / D conversion on the analog video signal to generate a digital video signal.
The front-end processing unit 13 performs audio detection from the intermediate frequency signal to generate an audio signal. In the present embodiment, description of audio signal processing is omitted.

  Further, the front-end processing unit 13 extracts the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC from the analog video signal obtained from the received radio waves of the selected designated channel, and outputs them to the video decoder 15. The front end processing unit 13 generates a blank signal BLANC and a basic clock CLK from the analog video signal, but the description of these processes is omitted in the present embodiment.

[Video decoder 15]
The video decoder 15 decodes the digital video signal input from the front end processing unit 13 to generate video data S15 and outputs the video data S15 to the video capture 17.
In the present embodiment, an example in which the input is an NTSC signal and the output image is horizontal 400 pixels and vertical 240 lines will be described.
The video decoder 15 converts the input digital video signal into one line of effective horizontal pixels 720 with 240 lines per field and outputs the converted signal to the video capture 17.

[Video capture 17]
The video capture 17 performs thinning processing on the video data S15 input from the video decoder 15 and writes it to the video memory 19.
Specifically, the video capture 17 performs a thinning process on the video data S15 for one frame of the horizontal pixel number 720 input from the video decoder 15 to the display horizontal pixel number 400, and then the buffer memory BUF1 to the buffer memory BUF1 of the video memory 19. Write to 4. The number of horizontal pixels may be set to 400 by performing reduction processing (scaling) including filter processing instead of thinning processing.
The video capture 17 outputs a write end notification to the control unit 29 when the operation of writing one frame of video data to the buffer memories BUF1 to BUF4 ends.

[Video memory 19]
The video memory 19 is, for example, an SDRAM (Synchronous DRAM).
The video memory 19 has a plurality of buffer memories, and the writing operation by the video capture 17 and the reading operation by the display data synthesis unit 23 can be performed in parallel to different buffer memories.
In the example shown in FIG. 1, the video memory 19 includes buffer memories BUF1 to 4, x. The buffer memories BUF1 to 4 and x each store video data for one frame.
Video data from the video capture 17 is written into the buffer memories BUF1 to BUF4, and image data generated by the drawing engine 21 is written into the buffer memory BUFx.

The video capture 17 writes video data into the buffer memories BUF1 to BUF4 by, for example, buffer memories BUF1, BUF2, BUF3, BUF4, BUF1,. . It is done in the ring format in the order.
Further, the reading of the video data from the buffer memories BUF1 to BUF4 by the display data synthesizer 23 is delayed from the writing operation by the video capture 17, and the buffer memories BUF1, BUF2, BUF3, BUF4, BUF1,. . It is done in the ring format in the order.

[Display data composition unit 23]
The display data composition circuit synthesizes the digital video data read from the buffer memories BUF1 to BUF4 and the image data read from the drawing buffer memory BUFx based on the timing signal input from the display control unit 25 to obtain the composite image data. This is generated and output to the display control unit 25.
The display data synthesizing unit 23 outputs to the control unit 29 a read end notification indicating the timing at which the synthesized image data is generated.

[Display control unit 25]
The display control unit 25 includes a display control register REG. Based on the display timing value stored in the display control register REG, the display control unit 25 sets an image display timing according to the composite image data generated by the display data composition unit 23. Control. The display control register REG may be provided in a place other than the display control unit 25.
The display control unit 25 reads the display timing value from the display control register REG and uses it for control at the timing of the horizontal line start (the leading edge of the horizontal synchronization signal).

In this embodiment, the display-side read field frequency by the display control unit 25 is set higher than the write-side field frequency by the video capture 17. For this reason, the read operation catches up with the write operation to the video memory 19.
When such a catch-up occurs, the display control unit 25 performs vertical synchronization based on the display timing value set in the display control register REG from the control unit 29, for example, as shown in FIGS. The timing of the signal V-SYNC is delayed.

[Liquid crystal display 27]
For example, as shown in FIGS. 2 and 3, the liquid crystal display 27 is NTSC (input-side field frequency 59.94 Hz), and the time of one line on the display side is set to 61.6 μs.
As will be described later, the liquid crystal display 27 displays a line of one field when it is not determined that the read operation in the buffer memories BUF1 to BUF4 catches up with the write operation based on the control of the display control unit 25 by the control unit 29. The number is 262 (62.0 Hz). This determination will be described later.
On the other hand, if the liquid crystal display 27 is determined to catch up, the number of lines in one field is set to 282 (57.6 Hz) based on the control of the display control unit 25.
As described above, as a method of changing the number of lines in one field, a method of changing the number of horizontal lines of the vertical synchronizing signal width, a method of changing the number of lines from the leading edge of the vertical synchronizing signal to the start of the effective image line, and an effective image line There are methods to change the number.
In the example shown in FIG. 3, the number of lines from the last line of the effective image to the leading edge of the vertical synchronization signal is changed.

[Control unit 29]
The control unit 29 is, for example, an LSI that does not include an input pin for a vertical synchronization signal.
Based on the write end notification input from the video capture 17, the control unit 29 instructs the video capture 17 on the buffer memories BUF 1 to 4 to which the digital video data is next written.
For example, when the video capture 17 inputs a write end notification to the buffer memory BUF1, the control unit 29 instructs the video capture 17 to write to the buffer memory BUF2 next.

The control unit 29 instructs the display data synthesizing unit 23 on the buffer memories BUF1 to BUF4 from which the digital video data is next read based on the readout end notification input from the display data synthesizing unit 23.
For example, when a notification of completion of reading from the buffer memory BUF1 is input from the display data combining unit 23, the control unit 29 instructs the display data combining unit 23 to read from the buffer memory BUF2 next.

  In other words, the control unit 29 grasps the buffer memories BUF1 to BUF4 to which writing is currently performed in the video memory 19 and the buffer memories BUF1 to BUF4 to which reading is currently being performed. Controls whether to write to and read from the memories BUF1 to BUF4.

The read operation follows the write operation, and the buffer memories BUF1, BUF2, BUF3, BUF4, BUF1,. . . The ring operation is performed in the order of.
In the present embodiment, as described above, the display-side read field frequency by the display control unit 25 is set higher than the write-side field frequency by the video capture 17, so the read operation catches up with the write operation. .

  When the catch-up is detected, the control unit 29 controls the read timing of the next buffer memories BUF1 to BUF4. That is, as shown in FIGS. 2 and 3, the control unit 29 reads the data of the effective image line (displays the image display on the liquid crystal display 27 from the top to the bottom), and then the next buffer memory BUF1. 4 is controlled so as to delay the timing until the reading of 4 starts.

FIG. 4 is a flowchart for explaining an operation example of the control unit 29 shown in FIG.
When the reading end notification is input from the display data synthesizing unit 23 (step ST1), the control unit 29 satisfies whether or not the condition that writing to the buffer memory BUF that is instructed to read out two times has been completed is completed. Is determined (step ST2). Note that the control unit 29 may determine whether or not the condition that the writing to the buffer memories BUF1 to FU4 to be instructed to read next or three or more ahead is completed is satisfied.
When determining that the above condition is not satisfied, the control unit 29 determines that a catch-up has occurred (step ST3), and performs a process of delaying the display timing (step ST4).

Specifically, when it is determined that the catch-up has occurred, the control unit 29 controls the read timing of the next buffer memory BUF1 to BUF4, and as shown in FIG. 2 and FIG. After reading (displaying the image display on the liquid crystal display 27 from the top to the bottom), control is performed to delay the timing until the reading of the next buffer memory BUF1 to BUF4 is started.
When the digital video data is next read from the buffer memory BUF, the display control unit 25 determines the display timing based on the display timing value read from the display control register REG.

As the display frequency for displaying an image corresponding to the video data is set to be lower by the display timing value stored in the display control register REG, the display control unit 25 causes the control unit 29 to store the video data from the buffer memories BUF1 to BUF4. Is controlled to lower the read frequency. This delays the timing until the next reading is started after the video data for one screen is read from the buffer memory BUF.
Here, if the display-side field frequency (display frequency) at the delayed timing is lower than the input-side field frequency, the display-side read timing is delayed with respect to the writing side, and the catch-up phenomenon is eliminated.
Depending on the relationship between the display-side field frequency and the input frequency when delayed, and the relationship between the display-side field frequency and the input frequency when not delayed, the catch-up may be resolved by one timing delay process. There may be a case where multiple timing delay processes occur continuously (determined as catching up continuously) and eliminated.

  On the other hand, when it is determined that the control unit 29 has not caught up, the control unit 29 instructs to read the next buffer memories BUF1 to BUF4 without rewriting the display timing value of the display control register REG.

  In the example shown in FIG. 5, when the display data synthesizing unit 23 completes reading of the buffer memory BUF4, the control unit 29 determines that it has caught up because writing is being performed on the buffer memory BUF2. Then, the control unit 29 sets the display timing value stored in the display control register REG of the display control unit 25 so as to delay the display timing of the image corresponding to the video data read from the buffer memory BUF2.

  Next, when the display data synthesizing unit 23 completes the reading of the buffer memory BUF1, the control unit 29 determines that it has caught up because the writing is being performed on the buffer memory BUF3. Then, the control unit 29 sets the display timing value stored in the display control register REG of the display control unit 25 so as to delay the display timing of the image corresponding to the video data read from the buffer memory BUF3.

Next, when the display data synthesizing unit 23 completes the reading of the buffer memory BUF2, the control unit 29 determines that it has caught up because the writing is being performed on the buffer memory BUF4. Then, the control unit 29 sets the display timing value stored in the display control register REG of the display control unit 25 so as to delay the display timing of the image according to the video data read from the buffer memory BUF4.
Next, when the display data synthesizing unit 23 completes reading of the buffer memory BUF3, the control unit 29 determines that writing has been completed with respect to the buffer memory BUF1 and has not caught up. For this reason, the control unit 29 does not set the display timing value stored in the display control register REG of the display control unit 25.

Hereinafter, an example of the overall operation of the image display apparatus 1 shown in FIG. 1 will be described.
The front-end processing unit 13 performs front-end processing on the received radio wave received by the antenna 11 to generate a digital video signal.
Next, the video decoder 15 decodes the digital video signal input from the front-end processing unit 13 to generate video data S15 and outputs it to the video capture 17.

The video capture 17 performs a thinning process on the video data S15 input from the video decoder 15 and writes it to the video memory 19.
The video capture 17 outputs a write end notification to the control unit 29 when the operation of writing one frame of video data to the buffer memories BUF1 to BUF4 ends.

In parallel with the operation of the video capture 17 described above, the display data synthesizing circuit 23 reads out the digital video data from the buffer memories BUF1 to BUF4 and the drawing buffer memory BUFx based on the timing signal input from the display control unit 25. The synthesized image data is generated by combining the read image data and is output to the display control unit 25.
Further, the display data synthesizing unit 23 outputs a read end notification indicating the timing at which the synthesized image data is generated to the control unit 29.

Then, the display control unit 25 controls the display timing of the image according to the composite image data generated by the display data composition unit 23 based on the display timing value stored in the display control register REG. Under the control of the display control unit 25, an image corresponding to the composite image data is displayed on the display 27.
At this time, when reading from the buffer memories BUF1 to BUF4 does not catch up with writing, the time interval of the vertical synchronizing signal is 262H as shown in FIG. Here, H is the time of one horizontal synchronization period, for example, 61.6 μsec.

Further, as described with reference to FIG. 4, when the reading end notification is input from the display data synthesizing unit 23 (step ST1), the control unit 29 writes to the buffer memory BUF that is to be instructed to read out two times ahead. It is determined whether or not the condition that the process is completed is satisfied (step ST2).
When determining that the above condition is not satisfied, the control unit 29 determines that a catch-up has occurred (step ST3), and performs a process of delaying the display timing (step ST4).
Specifically, when the control unit 29 detects the catch-up, as shown in FIG. 3, after reading the data of the effective image line (displaying the image display on the liquid crystal display 27 from the top to the bottom), Control is performed so as to delay the timing until reading of the next buffer memories BUF1 to BUF4 starts. In the present embodiment, the time interval of the vertical synchronization signal is increased to 282H. As a result, catch-up of the read operation to the write operation is avoided.

As described above, in the image display apparatus 1, the control unit 29 monitors the writing operation and the reading operation with respect to the video memory 19 and determines whether or not a catch-up has occurred. When the control unit 29 determines that the catch-up has occurred, the control unit 29 controls the display control unit 25 to delay the display timing.
As described above, the image display apparatus 1 uses the control unit 29 that does not have the hardware for the external synchronization function to display the field frequency on the input side (writing side) and the display side (reading side) in synchronization. The field frequency on the side is changed. Here, in the case where the display afterimage time is long such as the liquid crystal display 27, even if the field frequency is slightly changed, the temporal unevenness of brightness and darkness is not perceived, so that the image quality does not deteriorate.
According to the image display device 1, even without hardware for external synchronization, the input video signal can be transmitted without synchronizing the frame frequency on the display side with the field frequency of the input video signal, and without frame double copying or frame dropping. Can be displayed.

In other words, in the image display device 1, the field frequency on the display (reading) side is always set to a field frequency higher than the field frequency on the input side. When reading has caught up with writing, the display (reading) side waits for a certain time after displaying the image and starts reading the next surface. In other words, the same frame is not displayed twice, but instead waits for display. On the other hand, when it is not in the catch-up state, reading (display) is started without waiting.
In the image display apparatus 1, the field frequency on the display side can smoothly follow the field frequency on the input side by repeating the above operation.

The present invention is not limited to the embodiment described above.
That is, those skilled in the art may make various modifications, combinations, subcombinations, and alternatives regarding the components of the above-described embodiments within the technical scope of the present invention or an equivalent scope thereof.

  For example, the control unit 29 monitors the write frequency and the read frequency to the buffer memories BUF1 to BUF4, and even when there is only a difference between the write address and the read address by an address shorter than the address length of one buffer memory. If the read frequency at that time is higher than the write frequency, it may not be determined that the catch-up is.

  In the above-described embodiment, when the writing to the buffer memories BUF1 to BUF4 catches up with the reading, the control unit 29 may control the display control unit 25 to increase the frequency of image display. In this case, effective pixel lines may be thinned out as necessary.

Further, in the above-described embodiment, as illustrated in FIG. 1, the case where the video capture 17 writes in the four buffer memories BUF1 to BUF4 in a ring manner is illustrated, but the number of buffer memories is particularly limited as long as the number is three or more. Not.
The present invention can also be applied to a configuration that does not use the drawing engine 21 and the buffer memory BUFx.

  The present invention is applicable to a system in which video data is stored in a memory and then read and displayed.

It is a functional block diagram of the image display apparatus of the embodiment of the present invention. It is a figure for demonstrating control of the display timing by the control part and display control part which are shown in FIG. It is a figure for demonstrating control of the display timing by the control part and display control part which are shown in FIG. It is a flowchart for demonstrating the process by the control part shown in FIG. It is a figure for demonstrating an example of the display control by the control part shown in FIG. It is a functional block diagram of the conventional image display apparatus. It is a figure for demonstrating the case where write-in operation | movement has caught up with read-out operation in the buffer memory. It is a figure for demonstrating the case where read-out operation has caught up with write-in operation in the buffer memory.

Explanation of symbols

1 ... Image display device,
11 ... Antenna,
13 ... front end processing unit,
15 ... Video decoder,
17 ... Video capture,
19 ... Video memory,
BUF1-4, x ... buffer memory 21 ... drawing engine,
23 ... Display data composition unit 25 ... Display control unit 27 ... Liquid crystal display

Claims (3)

In an image display device that reads and displays video data after storing it in memory,
The operation of writing the video data to the memory and the operation of reading the video data from the memory and displaying them are monitored, and it is determined whether or not the relationship of reading the video data after being written to the memory can be maintained. A determination means;
When the display frequency for displaying the image according to the video data read from the memory is lowered, the read frequency for reading the video data from the memory is lowered, and when the determination means determines that the relationship cannot be maintained, An image display device comprising: control means for controlling the display frequency so that the relationship is maintained. The read frequency is higher than a write frequency for writing the video data to the memory,
When writing the video data in a predetermined order to a plurality of predetermined storage areas in the memory,
The determination means determines whether or not the relationship can be maintained based on the storage area where the video data is read from the memory and the storage area where the writing is performed,
The control means performs control so as to increase the number of lines used for displaying one image corresponding to video data read from the memory and to lower the display frequency when it is determined that the relationship cannot be maintained. The image display device according to claim 1. In a display control method for reading and displaying video data after storing it in a memory,
A monitoring step of monitoring an operation of writing the video data to the memory and an operation of reading and displaying the video data from the memory;
A determination step of determining whether or not a relationship of reading out the video data after being written into the memory can be maintained based on a monitoring result in the monitoring step;
When the display frequency for displaying the image according to the video data read from the memory is lowered, the read frequency for reading the video data from the memory is lowered, and when it is determined in the determination step that the relationship cannot be maintained, And a control step of controlling the display frequency so that the relationship is maintained.