JP2007225863A - Emi reducing controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a FIFO memory capacity for eliminating an influence on a video signal by transition of a clock frequency when performing spread spectrum for reducing EMI. <P>SOLUTION: When performing spread spectrum for reducing EMI, a clock 1 after spread spectrum is synchronized with a clock before the spread spectrum in a sufficiently shorter period than one horizontal period, and also read-out address of the FIFO memory is advanced more than write-in address by the amount quantity of modulation of clock frequency or more. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to clock generation of digital equipment such as a liquid crystal television and a liquid crystal display, and more particularly to control of a spread spectrum clock.

  In general, in video equipment using a digital display device such as a liquid crystal television or a PDP television, the clock to the panel display device is modulated using a spread spectrum technology to suppress unnecessary radiation from the panel display device and its interface, and the clock is used as the clock. Efforts have been made to reduce the peak of unnecessary radiation by diffusing signal change points of the entire synchronized digital circuit.

In the conventional spread spectrum, a video signal of one horizontal period is stored in a FIFO memory capable of storing a video signal of at least one horizontal period, while a clock signal is generated using a horizontal synchronization signal, and each scanning line is generated based on the clock signal. Spectrum control is performed by generating a pixel clock reference signal that has been spread spectrum so as to spread within the spectrum (see, for example, Patent Document 1). FIG. 4 is a timing chart showing the operation of the conventional EMI reduction control apparatus. In the conventional EMI reduction control apparatus, a video signal for one horizontal period (a video signal of one wavelength time of the horizontal synchronization signal Hsync) is written in the FIFO memory according to a clock. On the other hand, the video signal written in the FIFO memory is read according to the pixel clock reference signal.
Special table 2004-505565 gazette

  However, the above configuration requires a FIFO memory of at least one horizontal period. For example, a memory with a small storage capacity such as a memory provided in an FPGA (Field Programmable Gate Array) cannot be used, and it is used for spread spectrum. There was a problem that the memory could not be miniaturized.

  An object of the present invention is to provide an EMI reduction control device in which a memory used for spread spectrum is downsized.

  In order to solve the above problems, the EMI reduction control apparatus of the present invention performs spectrum spreading for suppressing the capacity of the FIFO memory for eliminating the influence on the video signal due to the transition of the clock frequency when performing spectrum spreading for EMI reduction. The clock after spreading is synchronized with the clock before spread spectrum in a period sufficiently shorter than one horizontal period, and the read address of the FIFO memory is advanced more than the modulation amount of the clock frequency than the write address. It is.

  As described above, according to the present invention, when performing spread spectrum to reduce EMI, the clock after spread spectrum is used to suppress the capacity of the FIFO memory for eliminating the influence on the video signal due to the transition of the clock frequency. The FIFO memory capacity can be reduced by synchronizing with the clock before spread spectrum in a period sufficiently shorter than one horizontal period and by moving the read address of the FIFO memory more than the write address by the amount of modulation of the clock frequency. This makes it possible to reduce the size of the memory used for spread spectrum.

  According to the first aspect of the present invention, when spectrum spread is performed to reduce EMI, the clock after spectrum spread is 1 in order to suppress the capacity of the FIFO memory for eliminating the influence on the video signal due to the transition of the clock frequency. It is characterized in that it is synchronized with the clock before spread spectrum in a period sufficiently shorter than the horizontal period, and the read address of the FIFO memory is advanced more than the write address by the modulation amount of the clock frequency.

  According to a second aspect of the present invention, a first frequency dividing circuit that divides a clock synchronized with an input video signal and a clock of a liquid crystal panel after spectrum spread are divided and the frequency dividing ratio is the first frequency dividing circuit. Based on the second divider circuit that is the same as the divider circuit, the PLL that generates a clock by comparing the outputs of the two divider circuits in the previous period, and the liquid crystal panel clock to modulate the control voltage of the previous PLL A modulation pulse generation circuit that generates a modulation pulse, a video memory having a period sufficiently shorter than the horizontal synchronization period, and a read reset pulse of the previous video memory that delays a write reset pulse, which is a power-on reset pulse, for a period longer than the modulation amount And a vessel.

(Embodiment 1)
FIG. 1 is an example of a configuration diagram of an EMI reduction control apparatus according to the present invention, and FIG. 2 is a timing diagram showing an operation of the EMI reduction control apparatus.

  In FIG. 1, the EMI reduction control device includes a video signal processing LSI 1 and an EMI reduction circuit 8, and the EMI reduction circuit 8 further includes a memory 2, a delay device 3, a first frequency divider circuit 4, and a second frequency divider. The circuit 5, the PLL circuit 6, and the modulation pulse generation circuit 7 are configured. A specific operation will be described below.

  The video signal processing LSI 1 converts, for example, a composite signal, luminance, and color difference signals into RGB signals, performs a scaling process for converting the number of pixels in the display area in accordance with the resolution of the liquid crystal panel, and corrects the characteristics of the liquid crystal panel. The video signal input to the video signal processing LSI 1 is converted into an input digital video signal by performing contour correction, gamma correction, white balance adjustment, and the like that convert the video signal into user-preferred image quality. The memory 2 is a memory for storing a digital video signal. Here, the digital video signal is an RGB signal having a sample rate corresponding to a pixel of the liquid crystal panel, and the input digital video signal is a digital video signal input to the memory 2. Further, the video signal processing LSI 1 generates an input clock: CLOCK which is a signal having a frequency synchronized with the sample rate of the input digital video signal. Among the outputs of the video signal processing LSI 1, an input digital video signal is input to the memory 2 of the EMI reduction circuit 8, and an input clock: CLOCK is input to the first frequency divider 4 and the memory 2 of the EMI reduction circuit 8. . The input clock: CLOCK is divided by the first frequency dividing circuit 4 in a period sufficiently shorter than one horizontal period. For example, one horizontal period may be divided by 8, 16, 16, 32, or the like. The PLL circuit 6 generates an output clock: CLOCK_SS modulated using the output of the first frequency divider 4 as a reference. The output clock: CLOCK_SS is smoothed by generating a modulation pulse such as a triangular wave for modulating the input clock: CLOCK in the modulation pulse generation circuit 7 and then added to the clock control voltage of the PLL circuit 6. Further, the output clock: CLOCK_SS is frequency-divided by the second frequency dividing circuit 5 at the same frequency dividing ratio as that of the first frequency dividing circuit 4 and fed back to the PLL circuit 6. Thus, the input clock: CLOCK output from the video signal processing LSI 1 is modulated to the spectrum-spread output clock: CLOCK_SS. The delay device 3 is a delay device that delays the timing for reading the digital video signal from the memory 2 with respect to the writing timing by delaying the power-on reset signal. Here, the power-on reset signal is a pulse necessary for initializing an internal circuit in an LSI or the like, and is generally a pulse signal that maintains a low level for a certain period when the power is turned on and then becomes a high level. In the present embodiment, a power-on reset signal that is directly input to the memory 2 and has no delay, and a power-on reset signal that is once input to the delay unit 3 and delayed for a certain period are input to the memory 2. Then, by comparing the two, the memory 2 detects the delay amount of the power-on reset signal by the delay device 3, and the memory 2 detects the timing of reading the stored digital video signal with respect to the timing of writing. Delay the amount and sync.

  FIG. 2 is a timing chart showing the operation of the EMI reduction control apparatus. 1 to 8 described in the write timing and the read timing in FIG. 2 are generalized representations of digital data values of the pixels corresponding to the pixels of the liquid crystal panel, and in the present embodiment, DATA1 to DATA8 are respectively shown below. It describes. The horizontal direction represents the time axis. Using the output clock obtained by modulating the input clock and the input clock as described above, the memory 2 performs an operation of changing the input digital video signal synchronized with the input clock to the output digital video signal synchronized with the output clock. The input digital video signal is written in the memory 2 in accordance with the timing of the input clock: CLOCK, and the digital video signal written in the memory 2 is read out in the timing of the output clock: CLOCK_SS.

  On the other hand, when the input digital video signal is written to the memory 2 and the output digital video signal is read from the memory 2 based on the input clock: CLOCK and the output clock: CLOCK_SS, the read timing must be delayed with respect to the write timing. , There may be a jump between writing and reading. FIG. 3 shows an example of the digital video signal read / write timing with respect to the memory 2 when the delay device 3 does not delay the power-on reset signal. As in FIG. 2, 1 to 8 shown in FIG. 3 are generalized representations of digital data values of each pixel corresponding to the pixels of the liquid crystal panel, similarly to 1 to 8 in FIG. The horizontal direction represents the time axis. According to FIG. 3, for example, for DATA2, since the read timing is earlier than the write timing, the jump between the write and read occurs. This makes it impossible to change the clock of the video signal. In order to solve this problem, the delay unit 3 delays by the overtaking of the write timing and the read timing. This overtaking amount corresponds to the amount of modulation of the input clock: CLOCK and the output clock: CLOCK_SS. In the above example, reading of digital data for a maximum of two pixels overtakes writing. For this reason, the delay amount of the delay unit 3 needs to secure digital data for three pixels or more. As described above, by delaying the power-on-set signal in the delay unit 3 so that reading does not overtake writing, it is possible to prevent skipping between writing and reading, and it is possible to change clocks stably for video signals. Become. Finally, the data read from the memory 2 by the output clock: CLOCK_SS is output to the panel display device together with the input clock: CLOCK_SS as an output digital video signal.

  According to this configuration, the input digital video signal is written to the memory 2 using the input clock: CLOCK generated using the horizontal synchronizing signal, and stored in the memory 2 using the output clock: CLOCK_SS obtained by modulating the input clock: CLOCK. Reducing the amount of data of the digital video signal that must be stored in the memory 2 by reading out the read digital video signal and delaying the read timing by at least the modulation amount of the clock frequency from the write timing. Can do. Therefore, since the capacity of the memory for temporarily storing the digital video signal can be reduced, a memory having a small storage capacity such as a memory provided in an FPGA (Field Programmable Gate Array) is used. Even if it is used, the spectrum can be spread.

  The EMI reduction control apparatus according to the present invention is capable of suppressing the capacity of the FIFO memory, and in generating clocks for digital devices such as liquid crystal televisions and liquid crystal displays, especially for controlling spread spectrum clocks. Useful.

Configuration diagram of an EMI reduction control apparatus according to Embodiment 1 of the present invention. Timing chart showing the operation of the EMI reduction control apparatus according to Embodiment 1 of the present invention. The figure showing an example of the timing of reading / writing of the EMI reduction control apparatus in Embodiment 1 of this invention Timing diagram showing the operation of a conventional EMI reduction control device

Explanation of symbols

1 Video signal processing LSI
2 memory 3 delay device 4 first frequency divider circuit 5 second frequency divider circuit 6 PLL circuit 7 modulation pulse generation circuit 8 EMI reduction circuit

Claims (2)

When performing spread spectrum to reduce EMI, the clock after spread spectrum has a spectrum that is sufficiently shorter than one horizontal period in order to suppress the capacity of the FIFO memory for eliminating the influence on the video signal due to the transition of the clock frequency. An EMI reduction control device characterized by synchronizing with a clock before spreading, and a read address of the FIFO memory being advanced more than a write amount by a modulation amount of a clock frequency. A first frequency divider circuit that divides the clock synchronized with the input video signal, and a second frequency divider that divides the clock of the liquid crystal panel after spectrum spread and has the same frequency division ratio as the first frequency divider circuit. A PLL circuit that generates a clock by phase-comparing the outputs of the two frequency dividers in the previous period, and a modulation pulse generating circuit that generates a modulation pulse based on the clock of the liquid crystal panel to modulate the control voltage of the previous PLL And a video memory having a cycle sufficiently shorter than the horizontal synchronization cycle, and a delay device for delaying a write reset pulse, which is a power-on reset pulse, as a power-on reset pulse for a period longer than a modulation amount. EMI reduction control device.

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