TWI393068B - Video processing system and method with scalable frame rate - Google Patents

Description

Image processing system and method capable of expanding frame rate

The present invention relates to image processors, and more particularly to an image processing system that is scalable in frame rate.

As the resolution of the image display increases, the frame rate of the image gradually increases from the conventional 60 frames per second (ie, 60 Hz) to 120 frames per second (ie, 120 Hz) or higher. For example, a video display (such as a television) with a frame rate of 120 Hz, a video processor or a timing controller (TCON) that processes and transmits data to the display panel must have a processing and transmission of 120 Hz data. Ability. Since the image processor (or timing controller) needs to process twice the amount of data compared to the conventional 60 Hz image processor at the same time, the signal rate of the image input and output terminals is doubled, and the internal circuit area is also required. Increased to handle twice the amount of data, the size of the chip package and its number of pins also increased and increased. Therefore, whenever the image frame rate increases, the integrated circuit must be redesigned from the front-end process to the back-end process, and the device may need to be replaced, thus causing an increase in cost and delaying the time-to-market of the product.

In view of this, it is urgent to propose a novel image processing system architecture, which has scalability, can be easily expanded with the increase of the frame rate, and can even support the traditional frame rate.

In view of the above prior art, the conventional image processing system can only process a single frame rate, and when the frame rate is increased, the corresponding image processor needs to be redesigned and manufactured; one of the purposes of the embodiment of the present invention is to propose a figure. A frame rate scalable image processing system for processing and transmitting image data of various frame rates for displaying images on a display panel.

According to an embodiment of the invention, a master image processor processes part of the screen image data and transmits it to the timing controller. In addition, at least one slave image processor processes the remaining portion of the image data and transmits it to the timing controller. The master image processor and the slave image processor respectively generate partial results, and the master image processor generates an overall adjustment value (such as a brightness control signal or a gamma adjustment signal) according to the partial results to provide Display panel. According to an embodiment, a set value storage area is further included for storing related setting values of different frame rates. When the frame rate change is detected, the master image processor and the slave image processor download the corresponding set value from the set value storage area. When the frame rate becomes smaller, at least one of the slave image processors is turned off; when the frame rate becomes larger, at least one of the slave image processors is turned on.

Figure 1A shows a block diagram of a scalable image processing system in accordance with an embodiment of the present invention. Although the present embodiment is exemplified by a digital television set, the embodiments of the present invention are applicable to displays of other forms, sizes, and resolutions. Furthermore, the image processing system of the present embodiment has a frame rate expandable function, but can also be used as an image processing system with a fixed frame rate.

In this embodiment, the image processing system mainly includes a master image processor (also referred to as an analog video processor or an AVP) 10 and a slave image processor 12. The master image processor 10 and the slave image processor 12 of the present embodiment each have the ability to process and transmit a frame rate of 60 Hz. However, in other embodiments, the frame rate of the master image processor 10 and the slave image processor 12 is not limited to 60 Hz, and the frame rates of the two are not necessarily the same.

Continuing to refer to FIG. 1A, the master image processor 10 and the slave image processor 12 transmit signals between the master bus 1012 and the slave bus 1210. In this embodiment, the main control bus 1012 is a (120 Hz) unidirectional serial communication channel coupled to the slave image processor 12 by the master image processor 10, and includes two bits for sampling. The clock bit and the data bit of the transmitted data. In addition, the slave bus 1210 is a (120 Hz) unidirectional serial communication channel that is coupled to the master image processor 10 by the slave image processor 12, and also includes two-bit-sampling clock bits and transmission data. Data bit. In other embodiments, the master bus 1012 and the slave bus 1210 are not limited to one-way and serial, and the number of bits is not limited to two bits, and even the two buss may be combined.

According to the image processing system architecture of the 120 Hz frame rate of the embodiment, the master image processor 10 and the slave image processor 12 receive and process half of the image data of the screen from the input bus bars 100 and 120, respectively. After processing, the image data is transmitted to the 120 Hz timing controller (TCON) 14 via the output bus bars 102 and 122, respectively, and displayed on the display panel 16. In this embodiment, the input bus bar 100/120 and the output bus bar 102/122 use (but are not limited to) a dual channel low voltage differential signaling (dual LVDS) transmission format, and the output of the timing controller (TCON) 14 Bus 140 can use, but is not limited to, a small dual channel low voltage differential signal (mini-LVDS) or a reduced wobble differential signal (RSDS) transmission format.

As described above, the master image processor 10 and the slave image processor 12 respectively transfer half of the image data processed by the image processor 10 to the timing controller (TCON) 14 via the output bus 102/122. However, some control and adjustment of the image, such as backlight brightness control or gamma adjustment, must be based on the image data of the entire picture to obtain a better adjustment value. In order to consider the control and adjustment of the image, the master image processor 10 and the slave image processor 12 of the embodiment respectively calculate individual partial results by using the image data received by the image, and the slave image processor 12 The partial result is transmitted to the master image processor 10 by the slave bus 1210. The master image processor 10 coordinates and integrates the partial results provided by the slave image processor 12 to obtain a better overall adjustment value. In addition, the overall adjustment value may also be transmitted to the slave image processor 12 by the master bus 1012. The master image processor 10 then transmits the preferred overall adjustment value to the display panel 16. For example, the backlight brightness control signal PWM is transmitted through the wire 104, and the gamma adjustment signal GM is transmitted through the wire 106. In this embodiment, the backlight brightness control may be an automatic control according to the image itself or a manual brightness control signal PWM_I input according to the wire 108. In addition, when the wire 106 transmits the gamma adjustment signal GM, the common electrode voltage (Vcom) can also be transmitted by the way. Although the brightness control and the gamma adjustment are taken as an example in this embodiment, the present embodiment is also applicable to other parameters of the image, such as contrast adjustment of the image.

The second figure shows a timing diagram in which the master image processor 10 and the slave image processor 12 coordinately generate better adjustment values. During the horizontal scanning period 20, the master image processor 10 and the slave image processor 12 individually calculate the individual partial results by half of the image data received by themselves. During the final vertical blanking period 220 of the vertical scanning period 22, the master image processor 10 and the slave image processor 12 perform the aforementioned coordinated integration work - that is, the slave image processor 12 transmits some of its results to The master image processor 10 and the master image processor 10 further coordinate and integrate to obtain a better overall adjustment value. In the present embodiment, since the amount of data of the partial result of the slave image processor 12 is not large, the vertical blanking period 220 can be fully utilized for transmission and coordinated integration. The transmission frequency of the master bus 1012 and the slave bus 1210 can be adjusted according to the actual application.

The embodiment shown in FIG. A can be switched to support a basic 60 Hz frame rate in addition to being expandable to a frame rate of 120 Hz. In this embodiment, the master image processor 10 detects whether the input data of the input bus 100 is switched to the basic 60 Hz at an appropriate time (or each time the power is turned on); if the frame rate is detected to be switched to a new one, At the frame rate (for example, 60 Hz), the master image processor 10 and the slave image processor 12 download a new frame rate from the set value storage area 18 (for example, electronic erasable programmable read only memory, EEPROM) (for example, 60 Hz) related set values (such as overdrive data table or timing related settings); and, the slave image processor 12 will disable itself to allow the image processing system to perform 60 Hz image processing. If it is detected that the frame rate is restored to 120 Hz, the slave image processor 12 will be enabled again, and the master image processor 10 and the slave image processor 12 will re-download the frame rate of 120 Hz from the set value storage area 18. Related settings allow the image processing system to perform 120 Hz image processing.

In accordance with an architecture of an embodiment of the invention, a single 60 Hz frame rate image processor can be used to expand to an image processing system of 120 Hz. Thereby, the process and equipment of the integrated circuit are not required to be changed, thereby saving costs. Furthermore, the image processing system can support a basic 60Hz frame rate in addition to being expandable to 120Hz.

FIG. 1B is a block diagram showing a scalable image processing system according to another embodiment of the present invention, and the same elements as those in the first A are the same component symbols. Different from the first A-picture architecture, the timing controller (TCON) 14 of the present embodiment is separately fabricated in the master image processor 10 and the slave image processor 12. In this embodiment, the output bus 102/122 uses (but is not limited to) a small dual-channel low-voltage differential signal (mini-LVDS) or a reduced wobble differential signal (RSDS) transmission format for transmitting and displaying data. On the display panel 16.

The third figure shows a block diagram of a scalable image processing system according to still another embodiment of the present invention, and the same elements as those of the first A figure follow the same component symbols. In addition to the master image processor 10, the present embodiment uses three slave image processors - a first slave image processor 12A, a second slave image processor 12B, and a third slave image processor 12C. The master image processor 10 is coupled to the first/second/third slave image processor 12A/12B/12C by a (shared) master bus 1012; and the first/second/third slave image processor 12A The /12B/12C is coupled to the master image processor 10 by (independent) first/second/third slave busbars 1210A/1210B/1210C, respectively.

According to the architecture shown in the third figure, the master image processor 10 and the first/second/third slave image processors 12A/12B/12C receive and process four points from the input busbars 100 and 120A, 120B, and 120C, respectively. One of the screen image data. After processing, the image data is transmitted to the 240HZ timing controller (TCON) 14 via the output bus 102 and 122A, 122B, and 122C, respectively, and displayed on the display panel 16. The timing controller (TCON) 14 can also be fabricated in the master image processor 10 and the first/second/third slave image processors 12A/12B/12C, respectively. Then, the master image processor 10 and the first/second/third slave image processor 12A/12B/12C respectively calculate individual partial results by using the screen image data received by themselves, and the first/second/ The third slave image processor 12A/12B/12C transmits its partial results to the master image processor 10 by the slave busbars 1210A/1210B/1210C, respectively. The master image processor 10 coordinates and integrates part of the results provided by the first/second/third slave image processor 12A/12B/12C to obtain a better overall adjustment value. In addition, the overall adjustment value can also be transmitted to the first/second/third slave image processor 12A/12B/12C by the master bus 1012. The master image processor 10 then transmits the preferred overall adjustment value to the display panel 16.

According to the architecture of the embodiment shown in the third figure, a single 60 Hz frame rate image processor can be used to expand to an image processing system of 240 Hz. Thereby, the process and equipment of the integrated circuit are not required to be changed, thereby saving costs. Furthermore, the image processing system can support a basic 60Hz frame rate (turning off three slave image processors) or a 120Hz frame rate (turning off two slave image processors) in addition to being expandable to 240 Hz. Furthermore, the architecture of this embodiment can be further extended to above the 240 Hz frame rate.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

10. . . Master image processor

12. . . Slave image processor

12A. . . First slave image processor

12B. . . Second slave image processor

12C. . . Third slave image processor

14. . . Timing controller

16. . . Display panel

18. . . Set value storage area

20. . . Horizontal scanning period

twenty two. . . Vertical scan period

100. . . (master image processor) input bus

102. . . (master image processor) output bus

104. . . (brightness control signal) wire

106. . . (gamma adjustment signal) wire

108. . . (manual brightness control signal) wire

120. . . (subordinate image processor) input bus

120A. . . (first slave image processor) input bus

120B. . . (second slave image processor) input bus

120C. . . (third slave image processor) input bus

122. . . (subordinate image processor) output bus

122A. . . (first slave image processor) output bus

122B. . . (second slave image processor) output bus

122C. . . (third slave image processor) output bus

140. . . (sequence controller) output bus

220. . . Vertical occlusion period

1012. . . Master bus

1210. . . Dependent bus

1210A. . . First subordinate bus

1210B. . . Second slave bus

1210C. . . Third subordinate bus

PWM. . . Brightness control signal

PWM_I. . . Manual brightness control signal

GM. . . Gamma adjustment signal

Figure 1A shows a block diagram of an expandable image processing system in accordance with an embodiment of the present invention.

Figure 1B is a block diagram showing an expandable image processing system in accordance with another embodiment of the present invention.

The second figure shows a timing diagram for the master image processor and the slave image processor to coordinate the generation of better adjustment values.

The third figure shows a block diagram of an expandable image processing system in accordance with yet another embodiment of the present invention.

10. . . Master image processor

12. . . Slave image processor

14. . . Timing controller

16. . . Display panel

18. . . Set value storage area

100. . . (master image processor) input bus

102. . . (master image processor) output bus

104. . . (brightness control signal) wire

106. . . (gamma adjustment signal) wire

108. . . (manual brightness control signal) wire

120. . . (subordinate image processor) input bus

122. . . (subordinate image processor) output bus

140. . . (sequence controller) output bus

1012. . . Master bus

1210. . . Dependent bus

PWM. . . Brightness control signal

PWM_I. . . Manual brightness control signal

GM. . . Gamma adjustment signal

Claims (25)

A frame rate scalable image processing system includes: a master image processor that processes part of the image data of the screen and transmits it to a timing controller; at least one slave (slave) An image processor that processes the remaining portion of the image data and transmits the same to the timing controller; and a set value storage area for storing the relevant set values of the different frame rates; wherein the master image processor and the slave The image processor respectively generates a partial result, and the master image processor generates an overall adjustment value according to the partial results and provides it to a display panel. The frame processing expandable image processing system according to claim 1, wherein the timing controller is located inside the master image processor and the slave image processor. The frame processing expandable image processing system according to claim 1, wherein the timing controller is located outside the master image processor and the slave image processor. The image processing system is expandable according to the scope of claim 1, wherein the frame rate of the master image processor and the slave image processor is 60 Hz. The frame processing expandable image processing system of claim 1, wherein the overall adjustment value comprises a brightness control signal. An image processing system scalable according to the scope of claim 1 wherein the overall adjustment value comprises a gamma adjustment signal. The image processing system of the frame rate expandable according to the scope of claim 1 further includes a master bus, and the master image processor is coupled to the slave image processor for the master image The overall adjustment value generated by the processor is passed to the slave image processor. The image processing system is expandable according to claim 7, wherein the main control bus is a one-way serial communication channel. The image processing system of the frame rate expandable according to claim 1 further includes a slave bus, and the slave image processor is coupled to the master image processor for the slave image processor Some of the results are transmitted to the master image processor. The frame processing expandable image processing system according to claim 9 is characterized in that the above-mentioned slave bus is a one-way serial communication channel. The frame processing expandable image processing system according to claim 1, wherein the master image processor generates the overall adjustment value during a vertical blanking period. The image processing system of the frame rate expandable according to the first aspect of the patent application, when the master image processor detects a frame rate change from the input end, the master image processor and the slave image processor That is, the corresponding set value is downloaded from the set value storage area. The image processing system capable of expanding the frame rate according to claim 12, wherein at least one of the slave image processors is turned off when the frame rate is small, and at least one of the slave image processing is performed when the frame rate is increased. The device will open. The image processing system of the frame rate expandable according to claim 1, wherein the at least one slave image processor comprises a slave image processor, and the master image processor processes half of the image data separately Transfer to the timing controller separately. The frame processing expandable image processing system according to claim 1, wherein the at least one slave image processor comprises a total of three slave image processors, and the master image processor processes the quarter by one The screen image data is transmitted to the timing controller separately. A frame rate scalable image processing method includes: performing a master image processing to process part of the image data of the screen and generating a part of the result; performing a slave (slave) Image processing to process the remaining portion of the image data and generate another portion of the result; generating an overall adjustment value based on the partial results for providing to a display panel; and detecting the image based on the input image Frame rate, when the frame rate change is detected, the corresponding set value is downloaded. The image processing method of the frame rate expandable according to claim 16 of the patent application, wherein the frame rate of the master image processing and the dependent image processing are both 60 Hz. An image processing method capable of expanding the frame rate as described in claim 16 wherein the overall adjustment value includes a brightness control signal. An image processing method capable of expanding the frame rate as described in claim 16 wherein the overall adjustment value includes a gamma adjustment signal. The image processing method of the frame rate expandable according to claim 16 of the patent application scope further includes providing a master bus bar for transmitting the overall adjustment value. The image processing method capable of expanding the frame rate according to claim 20, wherein the main control bus is a one-way serial communication channel. The image processing method capable of expanding the frame rate as described in claim 16 of the patent application further includes a slave bus for transmitting the partial result. The image processing method capable of expanding the frame rate according to claim 22, wherein the above-mentioned slave bus is a one-way serial communication channel. An image processing method capable of expanding the frame rate as described in claim 16 wherein the overall adjustment value is generated during a vertical blanking period. The image processing method capable of expanding the frame rate as described in claim 16 of the patent application, when the frame rate becomes small, the partial image processing of the portion is turned off; when the frame rate becomes large, the partial image of the slave is turned on. deal with.