JP2008205719A - Display device and display method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display a display image on a display and its waveform image by changing over their respective display modes, and to perform displaying within the range of a reference value of the display. <P>SOLUTION: The display includes an FPGA 20 having: a module 24 for generating waveform signals from video signals which are selected by selectors 21, 22; and a selector 25 for changing over signals to be used for an inlaid image among the video signals and the waveform signals generated by the module 24. The display is also provided with a device 30 including: an input port 31 and a scaler 35 for applying conversion processing for main image displaying to one video signal to be used for the inlaid image changed-over by the selector 25; and an input port 32 and a scaler 36 for applying the image conversion processing for sub-image displaying to the other video signal or waveform signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device and a display method for displaying an image based on a video signal supplied from a video signal supply source, for example.

  Conventionally, an input video signal has been checked by connecting a measuring instrument to the outside of the display and monitoring the signal level of the video signal input to the display. The monitoring of the input video signal is performed in order to determine whether or not the measured value falls within the range of the reference value determined in advance on the display. Examples of values measured by this measuring instrument include a luminance level and a white level.

  As such a measuring instrument, there is an instrument that displays an image screen of an object to be measured and its electrical signal by combining them on the same screen. In this measuring instrument, first, a synchronizing signal of a video input signal is separated into a horizontal synchronizing signal and a vertical synchronizing signal, and a clock is generated based on the horizontal synchronizing signal.

  Measurement data using the count values of the vertical counter and horizontal counter based on this clock as read addresses is stored in the frame memory. Then, a DC reference value is given to the video input signal from the clamp circuit, and the data from the frame memory is combined with the data from the clamp circuit (see Patent Document 1).

  Further, component video signals including a luminance signal (Y), a color difference signal (RY), and a color difference signal (BY) are used as video signals for television broadcasting and video tape recorder recording / playback. In addition, a composite video signal including a luminance signal (Y), a color difference signal, a synchronization signal, and a color burst signal is used. The aspect ratio of the screen display of these video signals is 4 to 3 in normal television broadcasting (SD) (525 scanning lines), and 16 to 9 in high definition television broadcasting (HD) (1125 scanning lines). Book).

Other than this, the resolution of RGB signals output by the computer includes VGA (640 × 480), SVGA (800 × 600), XGA (1280 × 768), SXGA (1280 × 1024), and QXGA (2048 × 1536). Is present. Displaying a plurality of screens on the display using the video signals of these various resolutions has also been performed.
JP-A-6-62317

  In the monitoring of the input video signal by the conventional measuring instrument described above, a measuring instrument other than the display main body must be connected outside the display. For this reason, it is necessary to separately connect measuring instruments and perform measurement operations.

  Further, the display mode such as the display size and display layout of the measurement waveform is fixed. For this reason, this display mode cannot be arbitrarily changed corresponding to the display image on the display. That is, there is an inconvenience that it is difficult to monitor the input video signal corresponding to the display image on the display.

  Moreover, in the measuring device described in Patent Document 1 described above, a waveform or voltage value such as vibration of each part of the display image on the display is displayed on the same screen. Therefore, the waveform change can be displayed in real time. However, there is an inconvenience that it is impossible to determine how much the input video signal is relative to the reference value range of the display.

  Therefore, the present invention can display a waveform image corresponding to the display image together with the display image in the display, and can arbitrarily change the display mode of the waveform image corresponding to the display image of the display. It is an object of the present invention to provide a display device and a display method that enable display with respect to a reference value range of a display.

  In order to solve the above problems and achieve the object of the present invention, the display device of the present invention is a display means for displaying an arbitrary inset image using an arbitrary video signal selected from a plurality of input video signals. A waveform signal generating means for generating a waveform signal corresponding to the video signal from the selected arbitrary video signal, the selected arbitrary video signal, and the waveform signal generated by the waveform signal generating means, Switching means for selectively switching one and other signals used for an arbitrary inset image, and one signal used for an arbitrary inset image selectively switched by the switching means is converted into an image for main image display. And the other signal used for an arbitrary inset image is displayed after image conversion processing corresponding to the image conversion processing for main image display is performed for sub-image display. It is obtained by a video signal converting means for supplying the stage.

  Thereby, the waveform signal generating means generates a waveform signal corresponding to the video signal from the selected arbitrary video signal. The switching means selectively switches one and the other signals used for an arbitrary inset image from the selected arbitrary video signal and the waveform signal generated by the waveform signal generating means.

  Then, the video signal converting means converts one signal (for example, a video signal) used for an arbitrary inset image selectively switched by the switching means into an image corresponding to the display means for displaying the main image. Apply. At the same time, the video signal conversion means performs an image conversion process corresponding to the image conversion process for displaying the main image for the sub-image display on the other signal (for example, the video signal or the waveform signal based on the video signal). Later supplied to the display means.

  Therefore, when one and the other video signals used for an arbitrary inset image are selected, a main image obtained by performing conversion processing for main image display on the one video signal is displayed on the display means. Further, a sub-image obtained by converting the other video signal for sub-image display is displayed on the display means.

  At this time, a waveform signal based on the video signal is generated from the selected one video signal. Therefore, when one video signal used for an arbitrary inset image and a waveform signal based on the video signal are selected, the main image obtained by performing conversion processing for main image display on the one video signal is displayed on the display means. Is done. In addition, a sub-image obtained by converting the waveform signal based on the video signal for sub-image display is displayed on the display means.

  The display method of the present invention includes a step of generating a waveform signal corresponding to the selected video signal from the selected arbitrary video signal, the selected arbitrary video signal, and the waveform generated by the waveform signal generating means. Among the signals, a step of selectively switching one and the other signals used for an arbitrary inset image, and a process of converting one signal used for the selectively switched arbitrary inset image into an image for main image display. Performing and supplying the display means with the other signal used for an arbitrary inset image after performing image conversion processing corresponding to the image conversion processing for main image display for sub-image display; and An image that has undergone image conversion processing for main image display and an image that has been subjected to image conversion processing for sub-image display are displayed as arbitrary inset images on the display means. Tsu is intended to include and-flops.

  Thereby, first, a waveform signal based on the video signal is generated from the selected arbitrary video signal. Next, one of the selected video signal and the waveform signal generated by the waveform signal generation means is selectively switched between one and the other signal used for an arbitrary inset image.

  Then, conversion processing is performed on the image corresponding to the display unit for displaying the main image for one of the selectively used images that is selectively switched, and for displaying the main image for displaying the sub image for the other. An image conversion process corresponding to the image conversion process is performed and then supplied to the display means.

  Therefore, an image based on a video signal subjected to image conversion processing for main image display, an image based on a video signal subjected to image conversion processing for sub-image display, or an image based on a waveform signal based on the video signal is arbitrarily set as an inset image. Displayed by display means.

  According to the present invention, there is no need to connect a measuring instrument to the outside of the display, and it is possible to display the waveform image corresponding to the display image together with the display image in the display. For this reason, it is not necessary to connect the measuring instrument or perform the measurement operation separately, and the operability is improved.

Moreover, the display mode of the waveform image corresponding to the display image can be arbitrarily changed corresponding to the display image on the display. For this reason, arbitrary inset images can be generated by arbitrarily changing the display mode such as the display size and the display layout.
Furthermore, it is possible to display the range of the reference value of the display. If the display range of the waveform image corresponding to the display image is set within the reference value, the level of the waveform image with respect to the reference value can be grasped at a glance. For this reason, the visibility in the determination of the waveform image with respect to the reference value is improved.

Hereinafter, a display device according to an embodiment of the present invention will be described in detail with reference to the drawings as appropriate.
First, a block diagram illustrating a functional configuration of a display device according to an embodiment of the present invention will be described.
FIG. 1 is a block diagram illustrating a functional configuration of the display device according to the present embodiment.
In FIG. 1, the display device includes a video signal input unit 1 that selects an arbitrary video signal from among a plurality of input video signals. That is, the video signal input unit 1 performs video signal input selection in order to display an arbitrary inset image on the subsequent inset image display unit 7 using the selected arbitrary video signal.

  The display device further includes a waveform signal generation unit 3 that generates a waveform signal corresponding to the video signal from an arbitrary video signal selected by the video signal input unit 1. That is, the waveform signal generator 3 generates a waveform signal corresponding to the level value related to an arbitrary video signal selected by the video signal input unit 1. This waveform signal is displayed in a graph in the range of the reference value of the inset image display unit 7.

  In addition, the display device selects one of the video signals selected by the video signal input unit 1 and the waveform signal generated by the waveform signal generation unit 3 to select one and the other signal to be used for an arbitrary inset image. There is provided a video signal switching unit 2 for switching automatically.

  That is, the video signal switching unit 2 selectively switches between the case where one arbitrary video signal selected by the video signal input unit 1 and the other video signal are used as a signal used for the inset image. The video signal switching unit 2 is generated by the waveform signal generating unit 3 based on any one video signal selected by the video signal input unit 1 as a signal used for the inset image and the one video signal. The case of using a waveform signal is selectively switched.

  In addition, this display device uses an embedded image display unit 7 for displaying a main image with respect to one of the video signals used for an arbitrary embedded image selectively switched by the video signal switching unit 2. Is provided with a video signal / waveform signal conversion unit 4 that performs conversion processing on an image corresponding to the above.

  At the same time, the video signal / waveform signal conversion unit 4 performs image conversion processing corresponding to the image conversion processing for main image display for sub-image display on the image based on the other video signal or the waveform signal based on the video signal. . The video signal / waveform signal conversion unit 4 outputs the processed main image display signal and sub-image display signal to the inset image display unit 7 side after the above processing.

  That is, the video signal / waveform signal conversion unit 4 performs pixel and frequency conversion for displaying the main image on the inset image display unit 7 for one video signal for main image display. The video signal / waveform signal conversion unit 4 displays a sub image on the inset image display unit 7 for the waveform signal generated by the waveform signal generation unit 3 based on one video signal for sub image display. For this purpose, pixel and frequency conversion is performed.

  In addition, the display device uses the main image display signal and the sub-image display signal after the conversion processing performed by the video signal / waveform signal conversion unit 4 to use the main image in the inset image in the inset image display unit 7. An inset image generation unit 5 for generating display timing and sub-image display timing signals is provided.

  That is, the inset image generation unit 5 generates a main image display timing and a sub image display timing signal for specifying the main image display region and the sub image display region in the inset image in the inset image display unit 7. Here, the embedded image generation unit 5 is provided at the subsequent stage of the video signal / waveform signal conversion unit 4. However, the present invention is not limited to this, and the video signal / waveform signal conversion unit 4 is provided at the subsequent stage of the embedded image generation unit 5. Also good.

The display device also generates horizontal and vertical drive signals for displaying the inset image in the inset image display unit 7 based on the main image display timing and sub-image display timing signals generated by the inset image generation unit 5. Is provided with an inset image output unit 6.
In addition, the display device includes an inset image display unit 7 that displays an inset image by horizontal and vertical drive signals output from the inset image output unit 6.

  In addition, this display device controls input for video signal input selection in the video signal input unit 1, waveform signal graph display in the waveform signal generation unit 3, selection of a signal used for an inset image in the video signal switching unit 2, video A control unit 8 is provided that supplies a control signal for either the selection of conversion processing in the signal / waveform signal conversion unit 4 or the timing selection in the inset image generation unit 5.

Here, the control unit 8 may set a predetermined state as a default setting for any control signal and supply the control signal only when a change is requested.
In addition, the display device includes an operation panel 9 capable of operating keys displayed on the panel in order to cause the control unit 8 to generate a control signal.

Hereinafter, an example in which the embodiment of the present invention is applied to a display will be specifically described with reference to the drawings.
FIG. 2 is a block diagram showing a multi-display to which the present embodiment is applied. This multi-display uses a luminance signal (Y), a color difference signal (RY), and a color difference signal (BY) as video signals for television broadcasting and video tape recorder recording / playback as standards for analog transmission of video signals. And an input port (inputs 1 and 2) through which a composite video signal 12 including a luminance signal (Y), a color difference signal, a synchronization signal, and a color burst signal can be input as an input video signal 10. Yes.

This multi-display also has an input port (high definition) digital video signal 13 corresponding to DVI (Digital Visual Interface) which is a standard for digital transmission of video signals. Input 3).
Furthermore, this multi-display has an input port (inputs 4 and 5) through which RGB signals 14 and 15 output from a computer can be input as an input video signal 10 as an option.

  Various input video signals 10 input to such input ports (inputs 1, 2, 3, 4, 5) are input to a multi-display FPGA (field programmable gate all) 20. The FPGA 20 is an IC (Integrated Circuit) that can program arbitrary processing in units of fields of the input video signal 10 using a logic gate.

  The FPGA 20 includes a selector 21 that selects any two video signals from various input video signals 10 input to input ports (inputs 1, 2, 3, 4, and 5). The FPGA 20 includes a selector 22 that supplies the two video signals selected by the selector 21 as the port A input and the port B input, respectively, and supplies either the port A input or the port B input to the subsequent module 24. ing.

  The selector 22 uses the two video signals selected by the selector 21 as the port A input and the port B input, respectively, and selectively switches one of the fixed contacts on the port A side or the port B side with the movable contact and connects them. 23 is provided.

  The FPGA 20 is a module for generating a waveform signal of a video signal on the port A side or the port B side connected by selectively switching the movable contact and the fixed contact on the port A side or the port B side with the switch 23 of the selector 22. 24.

  The waveform signal generated by the module 24 is to display a level value relating to an arbitrary video signal on the port A side or the port B side selected by the switch 23 of the selector 22 on the display 38 in the subsequent stage.

  The waveform display of the waveform signal generated by the module 24 includes a WFM (waveform generator) indicating whether the luminance level of the video signal is within the reference of the display 38, and the output level of the audio signal corresponding to the video signal. Displayed by an ALM (audio level monitor) indicating whether or not it is within the standard of the speaker built in the display 38.

  The FPGA 20 is a selector that selects one of the port B input and the port C input by using the video signal on the port B side of the selector 22 as the port B input and the waveform signal of the module 24 as the port C input. 25. The selector 25 is provided with a switch 26 for selectively switching either the fixed contact on the port B side or the port C side with the movable contact.

  The port A input of the selector 21 is directly output as the port A output, and the signal of the fixed contact on the port B side or the port C side connected to the movable contact by the switch 26 of the selector 25 is output from the FPGA 20 as the port B output.

  The multi-display includes a device 30 to which the port A output and the port B output output from the FPGA 20 are input as a port A input and a port B input, respectively. The device 30 generates a timing for displaying the main image based on the port A input video signal and the video signal on the port B side of port B input or the sub image based on the waveform signal on the port C side on the subsequent display 38. Thus, it is a device that outputs together with the main image and sub-image signals.

  That is, the device 30 displays a sub-image by an input port 31 that generates a display timing signal of a main image based on a video signal input to port A, and a video signal on the port B side of port B input or a waveform signal on the port C side. And an input port 32 for generating a timing signal. The input port 31 generates a display timing signal of a main image for causing the display 38 in the subsequent stage to display the main image based on the video signal input to the port A corresponding to the display area of the display 38.

  The input port 32 generates a sub-image display timing signal for causing the display 38 in the subsequent stage to display the sub-image based on the video signal on the port B side of the port B input or the waveform signal on the port C side. The display timing of the sub-image is different from the display timing signal of the main image at the input port 31. Here, the display timing signal of the sub-image different from the display timing signal of the main image includes a timing that partially overlaps, but may be any signal that does not completely match.

  In addition, the device 30 includes a scaler 35 that performs pixel and frequency conversion on the video signal input to the port A in order to display the main image on the display 38 with the display timing signal of the main image at the input port 31. In addition, in order to display a sub-image on the display 38 in accordance with the sub-image display timing signal at the input port 32, a scaler that performs pixel and frequency conversion to the port B input side video signal or port C side waveform signal of the port B input. 36.

  Further, the device 30 includes a first path 33 of the main image generation system by the input port 31 and the scaler 35 and a second path 34 of the sub image generation system by the input port 32 and the scaler 36. Then, the first path 33 and the second path 34 are combined at the output stage of the device 30, and the main image and the sub-image are combined with the respective display timing signals to form one output video signal.

  The multi-display also uses a horizontal drive signal and a vertical drive signal for causing the display 38 to display a combined display of the main image and the sub-image based on the output video signal output from the device 30. A display driver 37 is provided.

  In addition, the multi-display includes a display 38 that displays a main image and a sub-image in combination on a single screen by a horizontal drive signal and a vertical drive signal output from the display driver 37.

  The multi-display further includes a CPU 39 that supplies a control signal for controlling the FPGA 20 and the device 30 based on the operation of the operation panel 40. That is, the CPU 39 controls selection of the selector 21 of the FPGA 20, selection of switching of the switch 23 of the selector 22, switching selection of the switch 26 of the selector 25, and generation of the waveform signal of the module 24 based on the control signal.

  Further, the CPU 39 controls the main image generation system by the input port 31 and the scaler 35 of the first path 33 and the sub-image generation system by the input port 32 and the scaler 36 of the second path 34 based on the control signal. And control.

  Further, the multi-display includes an operation panel 40 for causing the CPU 39 to generate a control signal based on an operation. That is, the operation panel 40 is provided with a key or a touch panel for selecting, for example, a video signal or a waveform signal to be a main image and a sub image and a combination display example of a main image and a sub image shown in FIG. It has been.

  As a default setting, the operation panel 40 is set so that a video signal to be a predetermined main image and sub-image is selected and a combination pattern of the main image and sub-image is displayed. It may be possible to operate only.

  FIG. 3 is a diagram illustrating an example of an inset image, FIG. 3A is a picture-in-picture (PIP), FIG. 3B is a picture-by-picture (PBP), FIG. 3C is a picture-out picture (POP (16: 9)), 3D is a picture-out picture (POP (4: 3)). FIG. 3 shows a combination pattern of the main image and the sub-image displayed on the display 38 of FIG. FIG. 3 shows an example in which both the main image and the sub-image correspond to the input video signal.

  The example of picture-in-picture (PIP) shown in FIG. 3A shows an example in which the main image 41 is displayed on the entire display area of the display 38 and the sub-image 42 is displayed on a part of the main image 41. .

  The main image 41 corresponds to the video signal of the port A input of the picture-in-picture (PIP) generated by the main image generation system by the input port 31 and the scaler 35 of the first path 33 of the device 30 of FIG. At this time, the input port 31 and the scaler 35 generate the display timing of the video signal of the port A input so as to generate the picture-in-picture (PIP) main image 41 by the control signal, and convert the pixel and the frequency.

  The sub-image 42 is a video signal on the port B side of the port B input of the picture-in-picture (PIP) generated by the input port 32 of the second path 34 of the device 30 of FIG. It corresponds. At this time, the input port 32 and the scaler 36 generate the display timing of the video signal on the port B side of the port B input so as to generate the picture-in-picture (PIP) sub-image 42 by the control signal, and the pixel and frequency Convert.

  The example of the picture-by-picture (PBP) shown in FIG. 3B is an example in which the main image 43 is displayed on the left half of the display area of the display 38 and the sub image 44 is displayed on the right half along with the main image 43. Show.

  The main image 43 corresponds to the video signal of the port A input of the picture-by-picture (PBP) generated by the input port 31 of the first path 33 of the device 30 of FIG. At this time, the input port 31 and the scaler 35 generate the display timing of the video signal of the port A input so as to generate the picture-by-picture (PBP) main image 43 by the control signal, and convert the pixel and the frequency.

  The sub-picture 44 is converted into a video signal on the port B side of the port B input of the picture-by-picture (PBP) generated by the sub-picture generation system by the input port 32 and the scaler 36 of the second path 34 of the device 30 in FIG. It corresponds. At this time, the input port 32 and the scaler 36 generate the display timing of the video signal of the port B input so as to generate the picture-by-picture (PBP) sub-image 44 by the control signal, and convert the pixel and the frequency.

  In the example of the picture-out picture (POP (aspect ratio is 16: 9)) shown in FIG. 3C, the main image 45 (16: 9) is displayed in the entire horizontal direction above the display area of the display 38, and the main picture 45 (16: 9) is displayed. In this example, the sub-image 46 is displayed outside the area of the image 45 (16: 9).

  The main image 45 (16: 9) is a picture signal of the port A input of the picture-out-picture (POP) generated by the input port 31 of the first path 33 of the device 30 of FIG. It corresponds. At this time, the input port 31 and the scaler 35 generate the display timing of the video signal of the port A input so as to generate the main image 45 (16: 9) of the picture out picture (POP) by the control signal, and the pixel and frequency Convert.

  The sub-image 46 is converted into a video signal on the port B side of the port B input of the picture-out-picture (POP) generated by the sub-image generation system by the input port 32 and the scaler 36 of the second path 34 of the device 30 in FIG. It corresponds. At this time, the input port 32 and the scaler 36 generate the display timing of the video signal on the port B side of the port B input so as to generate the picture-out-picture (POP) sub-image 46 by the control signal, and the pixel and frequency Convert.

  In the example of the picture-out picture (POP (aspect ratio is 4: 3)) shown in FIG. 3D, the main image 47 (4: 3) is displayed in the entire vertical direction on the right side of the display area of the display 38, and the main image 47 (4: 3) is displayed. An example in which the sub-image 48 is displayed outside the area of the image 47 (4: 3) is shown.

  The main image 47 (4: 3) is a video signal input to the port A of the picture-out-picture (POP) generated by the main image generation system by the input port 31 and the scaler 35 of the first path 33 of the device 30 of FIG. It corresponds. At this time, the input port 31 and the scaler 35 generate the display timing of the video signal of the port A input so as to generate the main image 47 (4: 3) of the picture out picture (POP) by the control signal, and the pixel and frequency Convert.

  The sub-image 48 corresponds to the video signal of the port B input of the picture-out picture (POP) generated by the sub-port generation system by the input port 32 and the scaler 36 of the second path 34 of the device 30 of FIG. At this time, the input port 32 and the scaler 36 generate the display timing of the video signal on the port B ｀ side of the port B input so as to generate the picture-out-picture (POP) sub-image 48 by the control signal, and the pixel and frequency Convert.

  4A and 4B are diagrams showing examples of other inset images. FIG. 4A is a picture-in-picture (PIP), FIG. 4B is a picture-by-picture (PBP), and FIG. 4C is a picture-out picture (POP (16: 9)). 4D is a picture-out picture (POP (4: 3)).

  FIG. 4 shows another combination pattern of the main image and the sub-image displayed on the display 38 of FIG. FIG. 4 shows an example in which only the main image is an image corresponding to the input video signal, and the sub-image is a graph display image of a waveform signal related to the input video signal.

  The example of picture-in-picture (PIP) shown in FIG. 4A shows an example in which the main image 51 is displayed on the entire display area of the display 38 and the sub-image 52 is displayed on a part of the main image 51. .

  The main image 51 corresponds to the video signal of the port A input of the picture-in-picture (PIP) generated by the main image generation system by the input port 31 and the scaler 35 of the first path 33 of the device 30 of FIG. At this time, the input port 31 and the scaler 35 generate the display timing of the video signal of the port A input so as to generate the picture-in-picture (PIP) main image 51 by the control signal, and convert the pixel and the frequency.

  The sub-image 52 corresponds to the waveform signal on the port C side of the port B input of the picture-in-picture (PIP) generated by the sub-image generation system by the input port 32 and the scaler 36 of the second path 34 of the device 30 of FIG. is doing. At this time, the input port 32 and the scaler 36 generate the display timing of the waveform signal on the port C side of the port B input so as to generate the picture-in-picture (PIP) sub-image 52 by the control signal, and change the pixel and frequency. Convert.

  The waveform signal on the port C side of the port B input is a waveform signal of the video signal of the port A input generated by the module 24 and is displayed in a graph. The graph display is displayed as a picture-in-picture (PIP) sub-image 52 by WFM indicating the luminance level of the video signal and ALM indicating the output level of the audio signal.

  The example of the picture-by-picture (PBP) shown in FIG. 4B is an example in which the main image 53 is displayed on the left half of the display area of the display 38 and the sub image 54 is displayed on the right half along with the main image 53. Show.

  The main image 53 corresponds to the video signal of the port A input of the picture-by-picture (PBP) generated by the input port 31 of the first path 33 of the device 30 of FIG. At this time, the input port 31 and the scaler 35 generate the display timing of the video signal input to the port A so as to generate the picture-by-picture (PBP) main image 53 by the control signal, and convert the pixel and the frequency.

  The sub-image 54 corresponds to the waveform signal on the port C side of the port B input of the picture-by-picture (PBP) generated by the input port 32 of the second path 34 of the device 30 of FIG. is doing. At this time, the input port 32 and the scaler 36 generate the display timing of the waveform signal on the port C side of the port B input so as to generate the picture-by-picture (PBP) sub-image 54 by the control signal, and change the pixel and frequency. Convert.

  The waveform signal on the port C side of the port B input is a waveform signal of the video signal of the port A input generated by the module 24 and is displayed in a graph. The graph display is displayed as a picture-by-picture (PBP) sub-image 54 using WFM indicating the luminance level of the video signal and ALM indicating the output level of the audio signal.

  In the example of the picture-out picture (POP (aspect ratio is 16: 9)) shown in FIG. 4C, the main image 55 (16: 9) is displayed in the entire horizontal direction above the display area of the display 38, and the main picture 55 (16: 9) is displayed. In this example, the sub-image 56 is displayed outside the area of the image 55 (16: 9).

  The main image 55 (16: 9) is a video signal input to the port A of the picture-out-picture (POP) generated by the main image generation system by the input port 31 and the scaler 35 of the first path 33 of the device 30 of FIG. It corresponds. At this time, the input port 31 and the scaler 35 convert the display timing, the pixel, and the frequency of the video signal of the port A input so as to generate a picture-out-picture (POP) main image 55 (16: 9) by the control signal. .

  The sub image 56 corresponds to the waveform signal on the port C side of the port B input of the picture out picture (POP) generated by the sub image generation system by the input port 32 and the scaler 36 of the second path 34 of the device 30 of FIG. is doing. At this time, the input port 32 and the scaler 36 generate the display timing of the waveform signal on the port C side of the port B input so as to generate the picture-out-picture (POP) sub-image 56 by the control signal, and change the pixel and frequency. Convert.

  The waveform signal on the port C side of the port B input is a waveform signal of the video signal of the port A input generated by the module 24 and is displayed in a graph. The graph display is displayed as a picture-out-picture (POP) sub-image 56 with WFM indicating the luminance level of the video signal and ALM indicating the output level of the audio signal.

  In the example of the picture-out picture (POP (aspect ratio is 4: 3)) shown in FIG. 4D, the main image 47 (4: 3) is displayed in the entire vertical direction on the right side of the display area of the display 38, and the main image 47 (4: 3) is displayed. An example is shown in which the sub-image 58 is displayed outside the area of the image 57 (4: 3).

  The main image 57 (4: 3) is a picture signal of the port A input of the picture-out-picture (POP) generated by the input port 31 of the first path 33 of the device 30 of FIG. It corresponds. At this time, the input port 31 and the scaler 35 generate the display timing of the video signal of the port A input so as to generate the main image 47 (4: 3) of the picture out picture (POP) by the control signal, and the pixel and frequency Convert.

  The sub-image 58 corresponds to the waveform signal on the port C side of the port B input of the picture-out-picture (POP) generated by the sub-image generation system by the input port 32 and the scaler 36 of the second path 34 of the device 30 of FIG. is doing. At this time, the input port 32 and the scaler 36 generate the display timing of the waveform signal on the port C side of the port B input so as to generate the picture-out-picture (POP) sub-image 58 by the control signal, and change the pixel and frequency. Convert.

  The waveform signal on the port C side of the port B input is a waveform signal of the video signal of the port A input generated by the module 24 and is displayed in a graph. The graph display is displayed as a picture-out-picture (POP) sub-image 56 with WFM indicating the luminance level of the video signal and ALM indicating the output level of the audio signal.

Next, details of the waveform generation of the WFM by the module 24 and the display state of the WFM will be described.
5A and 5B are diagrams illustrating waveform generation (WFM) of the module. FIG. 5A is an example of an input video signal, FIG. 5B is a horizontal synchronization signal, FIG. 5C is a horizontal video signal, FIG. 5D is a vertical synchronization signal, and FIG. This is a vertical video signal.

  When the input video signal 61 shown in FIG. 5A is displayed as an image, a certain blanking area 63 is required in addition to the effective video signal area 62. In the video signal area 62, for example, the horizontal to vertical pixel ratio is represented by 1280 × 1024.

  At this time, when the input video signal 61 shown in FIG. 5A is input as the video signal of the port A input of the selector 22 of the FPGA 20 of FIG. 2, the input video signal 61 shown in FIG. 5A is supplied to the module 24 via the switch 23. Is done. Here, the module 24 samples one line in the sampling area 64 above the video signal area 62 of the input video signal 61.

  That is, sampling is performed on the horizontal video signal shown in FIG. 5C over one line of the horizontal synchronization signal shown in FIG. 5B. The horizontal sampling is performed so that “640” horizontal sampling numbers 65 indicated by “0” to “639” are obtained at a constant sampling interval 66.

  The sampling data 70 thus horizontally sampled is stored in the horizontal memory 69. In the horizontal memory 69, 10-bit data is stored at “640” addresses. The 10-bit data is data indicating luminance values such as “16”, “1000”, “1000”, “1000”, “1000”, “900” indicated at the addresses @ 1 to @ 4.

  Further, the vertical video signal shown in FIG. 5E is sampled over the number of vertical lines in the sampling area 64 of the vertical synchronization signal shown in FIG. 5D. The vertical sampling is executed at a constant sampling interval 68 so that “640” vertical sampling numbers 67 indicated by “0” to “639” are obtained.

  The sampling data 71 thus vertically sampled is stored in the vertical memory 73. In the vertical memory 73, 10-bit data is stored at “640” addresses. The 10-bit data is data indicating luminance values such as “900”, “800”, “700”, “700” indicated at the addresses @ 1 to @ 3.

  Next, the horizontally sampled sampling data 70 stored in the horizontal memory 69 and the vertically sampled sampling data 71 stored in the vertical memory 73 are decoded 75 by the module 24 and the look-up table 74 is obtained. Created.

  The look-up table 74 stores a table value indicating the display level of the WFM that is the waveform signal corresponding to the address of the display area of the WFM that is the waveform signal. The sampling data 70 and 71 are luminance values indicated by absolute values, whereas the table value indicating the display level of the WFM that is the waveform signal is within a specified range with respect to the specified value of the display 38. It is a relative value indicating whether or not.

  Then, the table value of the look-up table 74 is read out by the module 24 and displayed in the display layout 76 at the address of the display area of the WFM that is the waveform signal of the display 38.

  6A and 6B are diagrams illustrating a display state of waveform generation (WFM). FIG. 6A is an example of a display layout of waveform generation (WFM), and FIG. 6B is a display example of waveform generation (WFM). FIG. 6 shows a state in which WFM is displayed in the WFM display area which is a waveform signal of the display 38.

  In the waveform generation (WFM) display layout example shown in FIG. 6A, the horizontal pixel to vertical pixel ratio is 800 based on the horizontal synchronization signal 79 and the vertical synchronization signal 80 with respect to the display area of the WFM that is the waveform signal of the display 38. An image of × 500 is displayed. This image display area requires a certain blanking area 78 in addition to an effective waveform layout area 77.

  The waveform layout area 77 has a horizontal pixel to vertical pixel ratio of 640 × 480. A waveform layout area 77 of 640 × 480 is assigned with the upper left point (x, y) of the waveform layout area 77 as the origin (0, 0).

  That is, addresses corresponding to “640” pixels indicated by “@ 0” to “@ 639” are assigned in the horizontal direction of the waveform layout area 77, and “480” indicated by “L0” to “L479” in the vertical direction. A vertical line corresponding to the book pixel is assigned.

  In the waveform layout area 77, “640” pixels indicated by “@ 0” to “@ 639” in the horizontal direction are pixels in the horizontal direction of the video signal area 62 of the input video signal 61 shown in FIG. 5A. It corresponds. In addition, the pixels of “480” vertical lines indicated by “L0” to “L479” in the vertical direction have the luminance values indicated by the absolute values of the horizontally sampled sampling data 70 shown in FIG. 5B in the vertical direction. It is made to correspond as a relative value.

  That is, the pixels of “480” vertical lines indicated by “L0” (maximum value) to “L479” (minimum value) in the vertical direction are allocated so as to be within a specified range corresponding to the specified value of the display 38. Yes. Accordingly, the luminance value indicating the display level of the WFM as the waveform signal is assigned as a relative value within the range of “480” lines indicated by “L0” (maximum value) to “L479” (minimum value) in the vertical direction.

  Here, assignment of a luminance value indicating a display level of WFM which is a waveform signal in the horizontal direction is shown. Addresses “@ 0” to “@ 639” in the horizontally sampled sampling data 70 stored in the horizontal memory 69 shown in FIG. 5B are “@ 0” in the horizontal direction of the waveform layout area 77 shown in FIG. 6A. ”To“ @ 639 ”corresponding to“ 640 ”pixels.

  Also, the luminance value indicated by an absolute value from “1000” (maximum value) to “16” (minimum value) of the horizontally sampled sampling data 70 stored in the horizontal memory 69 shown in FIG. 5B. Are associated with relative values indicated by “L0” (maximum value) to “L479” (minimum value) in the vertical direction of the waveform layout area 77 shown in FIG. 6A.

  That is, the luminance value “16” (minimum value) indicated by the absolute value of the address “@ 0” in the horizontally sampled sampling data 70 stored in the horizontal memory 69 shown in FIG. As shown in FIG. 6A, the waveform layout area 77 shown in FIG. 6A is assigned with the horizontal address “@ 0” corresponding to the relative value indicated by the vertical vertical line “L470”.

  Next, the luminance value “1000” (maximum value) indicated by the absolute value of the address “@ 1” in the horizontally sampled sampling data 70 stored in the horizontal memory 69 shown in FIG. As shown in FIG. 6A, the waveform layout area 77 shown in FIG. 6A is assigned in correspondence with the relative value indicated by the vertical address “@ 12” at the horizontal address “@ 1”.

  Similarly, the luminance value “1000” (maximum value) indicated by the absolute value of the address “@ 2” in the horizontally sampled sampling data 70 stored in the horizontal memory 69 shown in FIG. As shown in FIG. 6A, the waveform layout area 77 shown in FIG. 6A is assigned in correspondence with the relative value indicated by the vertical line “L12” at the horizontal address “@ 2”.

  Similarly, the luminance value “1000” (maximum value) indicated by the absolute value of the address “@ 3” in the horizontally sampled sampling data 70 stored in the horizontal memory 69 shown in FIG. As shown in FIG. 6A, the waveform layout area 77 shown in FIG. 6A is assigned with the horizontal address “@ 3” corresponding to the relative value indicated by the vertical vertical line “L12”.

  Furthermore, the luminance value “900” indicated by the absolute value of the address “@ 4” in the horizontally sampled sampling data 70 stored in the horizontal memory 69 shown in FIG. The waveform layout area 77 shown in FIG. 6A is assigned in correspondence with the relative value indicated by the vertical address “@ 63” at the horizontal address “@ 4”.

  Similarly, luminance values indicated by absolute values from addresses “@ 5” to “@ 639” in the horizontally sampled sampling data 70 stored in the horizontal memory 69 shown in FIG. 6A, the horizontal addresses “@ 5” to “@ 639” of the waveform layout area 77 shown in FIG. 6A are allocated in correspondence with the relative values indicated by the vertical lines “L470” to “L12”.

The display layout is described as a table value of the lookup table 74 so that the assignment as described above can be performed.
Here, only the assignment of the luminance value indicating the display level of the WFM that is the horizontal waveform signal is shown, but the assignment of the luminance value indicating the display level of the WFM that is the vertical waveform signal is performed in the same manner. Is done.

  In the waveform generation (WFM) display example shown in FIG. 6B, a background color 86 and a grid 87 indicating vertical and horizontal axes and a grid 88 indicating scales are displayed in the waveform layout area 77 shown in FIG. 6A.

The default setting value can be changed by a control signal from the CPU 40 to the module 24 by operating the operation panel 40.
Then, as shown in FIG. 6A, the generated waveform 89 is displayed as WFM within the range of relative values.

Next, details of the ALM waveform generation by the module 24 and the display state of the ALM will be described.
FIG. 7 is a diagram showing module waveform generation (ALM).
An input L / R channel audio signal 91 corresponding to the input video signal 61 shown in FIG. 5A is input to the peak hold circuit 92 in the module 24. The peak value of the output level value of the input L / R channel audio signal 91 input in real time by the peak hold circuit 92 is temporarily held.

  Temporary holding of the peak value of the output level value of the input L / R channel audio signal 91 by the peak hold circuit 92 is performed in accordance with the waveform display timing of ALMs that are sequentially refreshed.

  As for the output level value of the input L / R channel audio signal 91 on which the peak value is temporarily held by the peak hold circuit 92, the L channel and the R channel are decoded 93, and a lookup table 94 is created. .

  The look-up table 94 stores a table value indicating the display level of the ALM that is the waveform signal corresponding to the address of the display area of the ALM that is the waveform signal. The peak value temporarily held is the output level value indicated by the absolute value, whereas the table value indicating the display level of the ALM as the waveform signal is the value of the speaker built in the display 38. It is a relative value indicating whether or not it is within a specified range with respect to the specified value.

  Then, the table value of the look-up table 94 is read by the module 24 and displayed in the display layout 95 at the address of the ALM display area which is the waveform signal of the display 38.

The peak value of the output level value of the input L / R channel audio signal 91 input in real time by the peak hold circuit 92 is temporarily held.
As shown in the display layout 95, the output level values of the L channel and R channel indicated by absolute values are assigned to the display area of the ALM that is a waveform signal.

  That is, of “480 lines” in the vertical direction, “0 line” to “234 line” are assigned to the L channel, and “245 line” to “479 line” are assigned to the R channel. Then, the L channel and R channel output level values indicated by absolute values are assigned in correspondence with the relative values indicated by “30 dots” to “580 dots” of “640 dots” in the horizontal direction.

The display layout is described as a table value of the lookup table 94 so that the assignment as described above can be performed.
In the waveform generation (ALM) display example shown in FIG. 7, the background color 96 and the grid 97 indicating the horizontal axis and the grid 98 indicating the scale that are preset in advance are displayed in the display area of the ALM that is the waveform signal.

The default setting value can be changed by a control signal from the CPU 40 to the module 24 by operating the operation panel 40.
Then, as shown in FIG. 7, the generated waveform 99 is displayed as ALM within the range of relative values.

FIG. 8 is a diagram illustrating a sampling state of the input video signal. FIG. 8 shows a sampling pattern for waveform generation (WFM) of the module 24 shown in FIG.
For the frequency 48 Hz, 50 Hz, 56 Hz, 60 Hz, 72 Hz, 75 Hz, 85 Hz of the input video signal 101, the sampling timing 102 is SP1, SP2, SP3,..., SPN-1, SPN having the same cycle as 60 Hz. . Here, the numbers of frames for sampling each input video signal 101 having frequencies of 48 Hz, 50 Hz, 56 Hz, 60 Hz, 72 Hz, 75 Hz, and 85 Hz are indicated by numbers from “1” to “85”, respectively.

FIG. 9 is a diagram illustrating the controls for the selector, the port, and the scaler.
9 shows that the CPU 39 shown in FIG. 2 selects the selector 21 of the FPGA 20, selects the switch 23 of the selector 22, selects the switch 26 of the selector 25, and generates the waveform signal of the module 24 based on the control signal. The example of the corresponding display image when performing this control is shown.

  The CPU 39 controls the main image generation system by the input port 31 and the scaler 35 of the first path 33 of the device 30 and the sub-image generation system by the input port 32 and the scaler 36 of the second path 34 based on the control signal. The example of the corresponding display image when performing control of this is shown.

In FIG. 9, first, an example of a picture-in-picture (PIP) shown in FIG. 3A as a display image shown by 111 will be described.
In this case, the input video signal for the port A input and the port B input is selected by the selector 21 of the FPGA 20, and the open which selects neither the port A input nor the port B input is selected for the switch 23 of the selector 22. For the switch 26, port B is selected.

  Next, a timing signal for a main image of a picture-in-picture (PIP) is generated at the input port 31 of the device 30 for the video signal input at the port A, and the video at the port B side of the port B input at the input port 32 A timing signal for a picture-in-picture (PIP) sub-picture is generated for the signal.

  Then, the scaler 35 performs picture-in-picture (PIP) main picture pixel and frequency conversion on the port A input video signal, and the scaler 36 performs picture conversion on the port B input side video signal on the port B input side. In-picture (PIP) sub-picture pixels and frequency conversion are performed.

Next, an example of a picture-by-picture (PBP) shown in FIG. 3B as the display image shown at 112 will be described.
In this case, the input video signal for the port A input and the port B input is selected by the selector 21 of the FPGA 20, the open which selects neither the port A input nor the port B input is selected for the switch 23 of the selector 22, and the selector 25 For the switch 26, port B is selected.

  Next, a timing signal for a picture-by-picture (PBP) main image is generated from the port A input video signal at the input port 31 of the device 30, and the video at the port B input side of the port B input at the input port 32 is generated. A timing signal for a picture-by-picture (PBP) sub-picture is generated for the signal.

  Then, the scaler 35 performs picture-by-picture (PBP) main image pixel and frequency conversion on the video signal input to port A, and the scaler 36 performs picture conversion on the video signal on the port B side of port B input. Bi-picture (PBP) sub-picture pixels and frequency conversion are performed.

Next, an example of the picture-out picture (POP (16: 9)) shown in FIG. 3C as the display image shown by 113 will be described.
In this case, the input video signal for the port A input and the port B input is selected by the selector 21 of the FPGA 20, and the open which selects neither the port A input nor the port B input is selected by the switch 23 of the selector 22. In the switch 26, the port B is selected.

  Next, a timing signal for a main image of a picture-out picture (POP (16: 9)) is generated from the video signal input at port A at the input port 31 of the device 30, and the port B input port is input at the input port 32. A timing signal for a sub-picture of picture out picture (POP) is generated for the video signal on the B side.

  The scaler 35 converts the picture-out picture (POP (16: 9)) main picture pixel and frequency of the video signal input to the port A, and the scaler 36 converts the port B input side of the port B side. Conversion of pixels and frequency for a picture out picture (POP) sub-image is performed on the video signal.

Next, an example of a picture-out picture (POP (4: 3)) shown in FIG. 3D as a display image shown by 114 will be described.
In this case, the input video signal for the port A input and the port B input is selected by the selector 21 of the FPGA 20, and the open which selects neither the port A input nor the port B input is selected by the switch 23 of the selector 22. In the switch 26, the port B is selected.

  Next, the timing signal for the main image of the picture-out picture (POP (4: 3)) is generated from the video signal input to port A at the input port 31 of the device 30, and the port B input port is input at the input port 32. A timing signal for a sub-picture of picture out picture (POP) is generated for the video signal on the B side.

  Then, the scaler 35 converts the picture-out picture (POP (4: 3)) main picture pixel and frequency of the video signal input to the port A, and the scaler 36 outputs the video on the port B side of the port B input. The signal is subjected to picture out picture (POP) sub-picture pixel and frequency conversion.

Furthermore, an example of a picture-in-picture (PIP) shown in FIG. 4A as the display image shown in 115 will be described.
In this case, the selector 21 of the FPGA 20 selects the input video signal for the port A input and the port B input, the switch 23 of the selector 22 selects the port A input, and the switch 26 of the selector 25 selects the port C.

  Next, a timing signal for a picture-in-picture (PIP) main image is generated from the video signal input to port A at the input port 31 of the device 30, and the waveform signal on the port C side of the port B input at the input port 32. In response to this, a timing signal for a picture-in-picture (PIP) sub-picture is generated.

  Then, the scaler 35 converts the picture-in-picture (PIP) main picture pixel and frequency of the video signal input to the port A, and the scaler 36 converts the picture to the waveform signal on the port C side of the port B input. In-picture (PIP) sub-picture pixels and frequency conversion are performed.

Next, an example of the picture-by-picture (PBP) shown in FIG. 4B as the display image shown at 116 will be described.
In this case, the selector 21 of the FPGA 20 selects the input video signal for the port A input and the port B input, the switch 23 of the selector 22 selects the port A input, and the switch 26 of the selector 25 selects the port C.

  Next, a timing signal for a picture-by-picture (PBP) main image is generated from the video signal input to port A at the input port 31 of the device 30, and the waveform signal on the port C side of the port B input at the input port 32. In response to this, a timing signal for a picture-by-picture (PBP) sub-picture is generated.

  The scaler 35 converts the picture-by-picture (PBP) main image pixel and frequency of the video signal input to the port A, and the scaler 36 converts the picture to the waveform signal on the port C side of the port B input. Bi-picture (PBP) sub-picture pixels and frequency conversion are performed.

Next, an example of a picture-out picture (POP (16: 9)) shown in FIG. 4C as a display image shown by 117 will be described.
In this case, an input video signal for port A input and port B input is selected by the selector 21 of the FPGA 20, the port A is selected by the switch 23 of the selector 22, and the port C is selected by the switch 26 of the selector 25.

  Next, a timing signal for a main image of a picture-out picture (POP (16: 9)) is generated from the video signal input at port A at the input port 31 of the device 30, and the port B input port is input at the input port 32. A timing signal for a picture out picture (POP) sub-picture is generated for the waveform signal on the C side.

  Then, the scaler 35 converts the picture-out picture (POP (16: 9)) main picture pixel and frequency of the port A input video signal, and the scaler 36 uses the port B input port C side waveform. A pixel and frequency conversion for a picture out picture (POP) sub-image is performed on the signal.

Next, an example of a picture-out picture (POP (4: 3)) shown in FIG. 4D as a display image shown by 118 will be described.
In this case, the selector 21 of the FPGA 20 selects the input video signal for port A input and port B input, the switch 23 of the selector 22 selects the port A input, and the switch 26 of the selector 25 selects port C.

  Next, the timing signal for the main image of the picture-out picture (POP (4: 3)) is generated from the video signal input to port A at the input port 31 of the device 30, and the port B input port is input at the input port 32. A timing signal for a picture out picture (POP) sub-picture is generated for the waveform signal on the C side.

  Then, the scaler 35 converts the picture-out picture (POP (4: 3)) main image pixel and frequency of the video signal input to the port A, and the scaler 36 converts the waveform on the port C side of the port B input. A pixel and frequency conversion for a picture out picture (POP) sub-image is performed on the signal.

The display state switching described above will be specifically described below.
Here, for example, the display image 111 of the main image by the picture-in-picture (PIP) video signal and the sub-image by another video signal shown in FIG. 3A is displayed on the display 38 by default setting or previous setting. To do. From the main image based on the picture-in-picture (PIP) video signal shown in FIG. 3A and the sub-image display image 111 based on the other video signal, the main image based on the picture-by-picture (PBP) video signal shown in FIG. When the display mode is switched to the display image 112 of the sub-image based on the video signal, the following control is performed by controlling the selector, port, and scaler shown in FIG.

  The input image signal for port A input and port B input is already selected by the selector 21 of the FPGA 20 in the display state of the display image 111 of the main image by the picture signal of picture-in-picture (PIP) and the sub-image by another video signal. Has been. In addition, the switch 23 of the selector 22 is selected to be open and selects neither the port A input nor the port B input, and the switch 26 of the selector 25 is selected to be port B ポ ー ト.

  Therefore, when the display mode is switched to the display image 112 of the main image based on the picture-by-picture (PBP) video signal and the sub-image based on the other video signal, the control of the selector 21, the selector 22, and the selector 25 of the FPGA 20 is changed. Absent.

  Next, in the display state of the main image based on the picture signal of picture-in-picture (PIP) and the display image 111 of the sub-image based on another video signal, the input port 31 of the device 30 is used for the main image of picture-in-picture (PIP). A timing signal is generated. Further, a timing signal for a sub-picture of picture-in-picture (PIP) is generated at the input port 32.

  For this reason, when the display mode is switched to the display image 112 of the main image based on the picture-by-picture (PBP) video signal and the sub-image based on the other video signal, the main image of the picture-by-picture (PBP) is switched at the input port 31 of the device 30. A timing signal for an image is generated. Also, a timing signal for a picture-by-picture (PBP) sub-image is generated at the input port 32.

  Then, in the display state of the main image by the picture-in-picture (PIP) video signal and the display image 111 of the sub-image by another video signal, the scaler 35 converts the pixel and frequency of the picture-in-picture (PIP) main image. I do. In addition, the scaler 36 performs pixel-in-picture (PIP) sub-picture pixel and frequency conversion.

  In addition, when the display mode is switched to a display image 112 of a main image based on a picture-by-picture (PBP) video signal and a sub-image based on another video signal, the scaler 35 uses pixels for the main image of the picture-by-picture (PBP) and Perform frequency conversion. Further, the scaler 36 performs pixel-by-picture (PBP) sub-picture pixel and frequency conversion.

  Further, from the display mode shown in the display image 112 of the main image by the picture signal of picture-by-picture (PBP) by the above-described control and the sub-image by another video signal, the video signal of the picture-in-picture (PIP) shown in FIG. 4A is used. When switching the display mode of the display image 115 of the sub image based on the main image and its waveform signal, the following control is performed by controlling the selector, port, and scaler shown in FIG.

  In the display state of the picture-by-picture (PBP) display image 112 shown in FIG. 3B, the input video signal for port A input and port B input is selected by the selector 21 of the FPGA 20. In addition, the switch 23 of the selector 22 is selected to open that does not select either the port A input or the port B input, and the switch 26 of the selector 25 is selected to select port B ｀.

  For this reason, when the display mode is switched to the display image 115 of the main image by the picture-in-picture (PIP) video signal and the sub-image by the waveform signal shown in FIG. An input video signal is selected. Further, the switch A of the selector 22 selects the port A input, and the switch 26 of the selector 25 selects the port C.

  Next, in the display state of the picture-by-picture (PBP) display image 112 shown in FIG. 3B, the timing signal for the picture-by-picture (PBP) main image is generated at the input port 31 of the device 30. Further, a timing signal for a picture-by-picture (PBP) sub-image is generated at the input port 32.

  Therefore, when the display mode is switched to the display image 115 of the main image based on the picture-in-picture (PIP) video signal and the sub-image based on the waveform signal shown in FIG. 4A, the picture-in-picture (PIP) at the input port 31 of the device 30. ) Of the main image. In addition, a timing signal for a sub-picture of picture-in-picture (PIP) is generated at the input port 32.

  Then, in the display state of the picture-by-picture (PBP) display image 112 shown in FIG. 3B, the scaler 35 performs pixel and frequency conversion for the picture-by-picture (PBP) main image. Further, the scaler 36 performs pixel-by-picture (PBP) sub-picture pixel and frequency conversion.

  For this reason, when the display mode is switched to the display image 115 of the main image by the picture signal of picture-in-picture (PIP) shown in FIG. 4A and the sub-image by the waveform signal, the main image of picture-in-picture (PIP) by the scaler 35. Pixel and frequency conversion is performed. Further, the scaler 36 performs pixel-in-picture (PIP) sub-picture pixel and frequency conversion.

  In this way, from the state in which the picture-in-picture (PIP) display image 111 shown in FIG. 3A is displayed on the display 38 by the default setting or the previous setting, the picture-by-picture (PBP) display shown in FIG. 3B is displayed. The display state of the image 112 can be switched. Furthermore, the display mode can be switched to the picture-in-picture (PIP) display image 115 shown in FIG. 4A.

  Not only the above-described switching but also any other switching can be performed. The display mode can be arbitrarily switched according to the format of the input video signal, the display size of the display 38, and the like.

  FIG. 10 is a diagram illustrating an example of the display size of an inset image. FIG. 10A is a picture-in-picture (PIP), FIG. 10B is a picture-by-picture (PBP), and FIG. 10C is a picture-out picture (POP (16: 9)). FIG. 10D shows a picture-out picture (POP (4: 3)).

  FIG. 10 shows an example of the display size on the display 38 of the display image shown in FIG. The display size is converted by generating the timing signal for the main image at the input port 31 of the device 30, the timing signal for the sub-image at the input port 32, and the main image for the scaler 35 by the control shown in FIG. Pixel and frequency conversion, and subpixel image and frequency conversion of the scaler 36 are necessary.

An example of the picture-in-picture (PIP) illustrated in FIG. 10A will be described.
In this example, the main image 121 is displayed on the display 38 with a horizontal / vertical pixel ratio of 1280 × 1024, and the sub-image 122 is displayed with a horizontal / vertical pixel ratio of 640 × 480 on a part of the upper right of the main image 121.

At this time, the following control is performed by the control described above.
First, a timing signal for a picture-in-picture (PIP) main image is generated at the input port 31 of the device 30 so that the main image 121 is displayed at a horizontal / vertical pixel ratio of 1280 × 1024.

  Also, a timing signal for a picture-in-picture (PIP) sub-image is generated at the input port 32 so that the sub-image 122 is displayed at a part of the upper right of the main image 121 at a horizontal / vertical pixel ratio of 640 × 480. Let

  Then, the scaler 35 performs pixel-in-picture (PIP) main image pixel and frequency conversion so that the main image 121 is displayed at a horizontal / vertical pixel ratio of 1280 × 1024. In addition, the scaler 36 converts the pixel and frequency of the sub-image of the picture-in-picture (PIP) so that the sub-image 122 is displayed at a part of the upper right of the main image 121 at a horizontal / vertical pixel ratio of 640 × 480. I do.

Next, an example of the picture-by-picture (PBP) illustrated in FIG. 10B will be described.
In this example, the main image 123 is displayed on the left half of the display 38 at a horizontal / vertical pixel ratio of 640 × 480, and the sub-image 124 is displayed on the right half along with the main image 123 at a horizontal / vertical pixel ratio of 640 × 480. The

At this time, the following control is performed by the control described above.
First, a timing signal for a picture-by-picture (PBP) main image is generated at the input port 31 of the device 30 so that the main image 123 is displayed on the left half of the display 38 with a horizontal / vertical pixel ratio of 640 × 480. Let

  Also, at the input port 32, a timing signal for a picture-by-picture (PBP) sub-image is generated so that the sub-image 124 is displayed with a horizontal / vertical pixel ratio of 640 × 480 along with the main image 123 in the right half. Let

  Then, the scaler 35 performs picture-by-picture (PBP) main image pixel and frequency conversion so that the main image 123 is displayed on the left half of the display 38 at a horizontal / vertical pixel ratio of 640 × 480.

  In addition, the scaler 36 converts the pixel and frequency for the picture-by-picture (PBP) sub-image so that the sub-image 124 is displayed in the right half alongside the main image 123 at a horizontal / vertical pixel ratio of 640 × 480. I do.

Next, an example of a picture-out picture (POP (16: 9)) illustrated in FIG. 10C will be described.
In this example, the main image 125 is displayed on the display 38 at a horizontal / vertical pixel ratio of 1280 × 720, and the sub-image 126 is displayed at a horizontal / vertical pixel ratio of 640 × 480 so as to partially overlap the lower left outside of the main image 125. Is done.

At this time, the following control is performed by the control described above.
First, a timing signal for a main image of a picture-out picture (POP (16: 9)) is generated at the input port 31 of the device 30 so that the main image 125 is displayed with a horizontal / vertical pixel ratio of 1280 × 720. .

  Further, at the input port 32, the sub-image 126 for the picture-out-picture (POP) is displayed so that the sub-image 126 is displayed at a horizontal / vertical pixel ratio of 640 × 480 so as to partially overlap the lower left outside of the main image 125. A timing signal is generated.

  Then, the scaler 35 performs pixel and frequency conversion for the main image of the picture-out picture (POP (16: 9)) so that the main image 125 is displayed at a horizontal / vertical pixel ratio of 1280 × 720.

  In addition, the sub-image pixels of the picture-out picture (POP) are displayed on the scaler 36 so that the sub-image 126 is displayed at a horizontal / vertical pixel ratio of 640 × 480 so as to partially overlap the lower left outside of the main image 125. And frequency conversion.

Next, an example of the picture-out picture (POP (4: 3)) illustrated in FIG. 10D will be described.
In this example, the main image 127 is displayed on the right side of the display 38 with a horizontal and vertical pixel ratio of 1600 × 1200, and the sub-image 128 is displayed on the outside of the lower left side of the main image 127 with a horizontal and vertical pixel ratio of 320 × 240.

At this time, the following control is performed by the control described above.
First, a timing signal for a main image of a picture-out picture (POP (4: 3)) is generated at the input port 31 of the device 30 so that the main image 127 is displayed with a horizontal and vertical pixel ratio of 1600 × 1200. .

  In addition, a timing signal for a sub-image of a picture-out picture (POP) is generated at the input port 32 so that the sub-image 128 is displayed at a horizontal and vertical pixel ratio of 320 × 240 outside the lower left of the main image 127. .

  Then, the scaler 35 performs pixel and frequency conversion for the main image of the picture-out picture (POP (4: 3)) so that the main image 127 is displayed at a horizontal and vertical pixel ratio of 1600 × 1200.

  In addition, the scaler 36 performs pixel and frequency conversion for the sub-image of the picture-out picture (POP) so that the sub-image 128 is displayed at a horizontal and vertical pixel ratio of 320 × 240 outside the lower left of the main image 127. Do.

  At this time, the main image 121 of the picture-in-picture (PIP) in FIG. 10A is an image based on the input video signal, and the sub-image 122 is an image based on the input video signal or WFM and ALM of the input video signal.

  The main image 123 of the picture-by-picture (PBP) in FIG. 10B is an image based on the input video signal, and the sub-image 124 is an image based on the input video signal or WFM and ALM of the input video signal.

  The main image 125 of the picture-out picture (POP (16: 9)) in FIG. 10C is an image based on the input video signal, and the sub-image 126 is an image based on the input video signal or WFM and ALM of the input video signal.

  The main image 127 of the picture-out picture (POP (4: 3)) in FIG. 10D is an image based on the input video signal, and the sub-image 128 is an image based on the input video signal or WFM and ALM of the input video signal.

  Further, the present invention is not limited to the above-described examples, and it is needless to say that various other configurations can be adopted without departing from the gist of the present invention described in the claims.

It is a block diagram which shows the function structure of the display apparatus of this Embodiment. It is a block block diagram which shows the multi display to which this Embodiment is applied. FIG. 3A is a picture-in-picture (PIP), FIG. 3B is a picture-by-picture (PBP), FIG. 3C is a picture-out picture (POP (16: 9)), and FIG. 3D is a picture-out picture. It is a picture (POP (4: 3)). FIG. 4A shows a picture-in-picture (PIP), FIG. 4B shows a picture-by-picture (PBP), FIG. 4C shows a picture-out picture (POP (16: 9)), and FIG. It is a picture-out picture (POP (4: 3)). FIG. 5A is an example of an input video signal, FIG. 5B is a horizontal synchronization signal, FIG. 5C is a horizontal video signal, FIG. 5D is a vertical synchronization signal, and FIG. 5E is a vertical video signal. is there. FIG. 6A is a diagram illustrating a display state of waveform generation (WFM), FIG. 6A is an example of a display layout of waveform generation (WFM), and FIG. 6B is a display example of waveform generation (WFM). It is a figure which shows the waveform generation (ALM) of a module. It is a figure which shows the sampling state of an input video signal. It is a figure which shows the control with respect to a selector, a port, and a scaler. FIG. 10A is a picture-in-picture (PIP), FIG. 10B is a picture-by-picture (PBP), FIG. 10C is a picture-out picture (POP (16: 9)), and FIG. It is a picture-out picture (POP (4: 3)).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Video signal input part, 2 ... Video signal switching part, 3 ... Waveform signal generation part, 4 ... Video signal / waveform signal conversion part, 5 ... Inset image (video / waveform) generation part, 6 ... Inset image output part, DESCRIPTION OF SYMBOLS 7 ... Embedded image display part, 8 ... Control part, 9 ... Operation panel, 10 ... Input video signal, 11 ... Component video signal, 12 ... Composite video signal, 13 ... Digital high-definition video signal, 14, 15 ... Optional video signal 20 ... FPGA, 21 ... selector, 23 ... switch, 24 ... module, 25 ... selector, 26 ... switch, 30 ... device, 31 ... input port, 22 ... input port, 33 ... first path, 34 ... second path 35 ... Scaler, 36 ... Scaler, 37 ... Display driver, 38 ... Display, 39 ... CPU, 40 ... Operation panel, 41, 43, 45, 47 ... Main image, 42 44, 46, 48 ... sub-image, 51, 53, 55, 57 ... main image, 52, 54, 56, 58 ... sub-image, 61 ... input video signal, 62 ... video signal area, 63 ... blanking area, 64 Sampling area 65, 67 Sampling number 66, 68 Sampling interval 69 Horizontal memory 70 71 71 Sampling data 73 Vertical memory 74 Look-up table 75 Decode 76 Display Layout, 77 ... Waveform layout area, 78 ... Blanking area, 79 ... Horizontal sync signal, 80 ... Vertical sync signal, 81 to 85 ... Layout pixels, 86 ... Background color, 87, 88 ... Grid, 89 ... Waveform, 91 ... Input L / R channel audio signal, 92 ... peak hold circuit, 93 ... decode, 94 ... look-up table, 95 ... table Layout ... 96 ... Background color, 97,98 ... Grid, 99 ... Waveform, 101 ... Input video signal, 102 ... Sampling timing, 111 ... Picture in picture (PIP) control in FIG. 3A, 112 ... Picture by picture in FIG. 3B (PBP) control 113... Picture-out picture (POP (16: 9)) control in FIG. 3C, 114... Picture-out picture (POP (4: 3)) control in FIG. 3D, 121, 123, 125, 127 ... main image, 122, 124, 126, 128 ... sub-image

Claims (6)

Display means for displaying an arbitrary inset image using an arbitrary video signal selected from a plurality of input video signals;
Waveform signal generating means for generating a waveform signal corresponding to the video signal from the selected arbitrary video signal;
Switching means for selectively switching one and the other signals used for the arbitrary inset image from the selected arbitrary video signal and the waveform signal generated by the waveform signal generation means;
One signal used for the arbitrary inset image selectively switched by the switching means is converted into an image for main image display and supplied to the display means, while the other signal used for the arbitrary inset image is supplied. Video signal conversion means for supplying a signal to the display means after performing image conversion processing corresponding to the image conversion processing for displaying the main image for sub-image display;
A display device comprising: The display device according to claim 1,
The display device according to claim 1, wherein the waveform signal generated by the waveform signal generation means is a signal for graphically displaying a level value related to the selected arbitrary video signal on the display means. The display device according to claim 2,
The display means includes a voice output means,
The graph display indicates whether the luminance level of the video signal is within the reference of the display means, and whether the output level of the audio signal corresponding to the video signal is within the reference of the audio output means. A display device characterized by indicating the above. The display device according to claim 2,
The waveform signal generation means includes a memory for storing a luminance level value sampled from the video signal, and a look-up table for laying out the luminance level stored in the memory in an area for graph display on the display means. A display device characterized by that. The display device according to claim 2,
The waveform signal generating means holds a peak hold circuit for holding a peak value of an output level value sampled from an audio signal corresponding to the video signal, and displays the peak value held by the peak hold circuit on the display means in a graph. A display device comprising a lookup table for laying out an area. In a display method for displaying an arbitrary inset image using an arbitrary video signal selected from a plurality of input video signals,
Generating a waveform signal corresponding to the video signal from the selected arbitrary video signal;
Selectively switching one and the other signals used for the arbitrary inset image from the selected arbitrary video signal and the waveform signal generated by the waveform signal generating means;
One signal used for the arbitrarily fitted image that has been selectively switched is converted into a main image display image and supplied to the display means, and the other signal used for the arbitrarily fitted image is sub-imaged. Supplying the display means after performing image conversion processing corresponding to the image conversion processing for displaying the main image for display;
Displaying the image subjected to the image conversion process for displaying the main image and the image subjected to the image conversion process for displaying the sub image on the display unit as an arbitrary inset image;
A display method comprising: