JP5259867B2 - Video display device and video processing method - Google Patents

Description

  Embodiments described herein relate generally to a video display device and a video signal video processing method.

  2. Description of the Related Art Television receivers (hereinafter referred to as “TVs”) that allow users to enjoy games by connecting game machines have become widespread. The user connects and operates the game device to the external input terminal of the television, whereby the video and audio generated by the game device are output from the television display and speaker. That is, by using a television as an external output device of a game machine, a user can enjoy a game on a large screen.

  In recent televisions, various video signals are processed to improve image quality. In order to process the video signal, since information and processing in units of frames are necessary, a predetermined time is required. In viewing a normal broadcast program or the like, a slight display delay of, for example, less than 50 milliseconds (ms) does not become a problem. However, if the video signal output from the game device is displayed with a delay, the user's operation on the display will be delayed, causing the user to feel uncomfortable or changing the result of the game. There was a risk of it occurring. For example, in a shooting game in which a target that moves at high speed on the display screen is shot, the shooting timing is shifted even with a slight delay time.

  For this reason, for example, in the case of playing a game, a display device that can shorten the delay time by omitting the digital calculation processing of the input video signal is known.

JP 2005-338605 A

  An object of the present invention is to provide a video display device and a video processing method that do not give a user a sense of incongruity when displaying game content or the like.

  A video display device according to one embodiment of the present invention includes a video processing module that outputs a display video signal generated by performing at least image quality enhancement processing and double speed processing on an input video signal to a display module, and the video signal A controller for receiving a low-delay processing instruction with a short delay time for the display video signal, and a frame memory for storing the video signal for at least one frame, wherein the video signal processing module is stored in the frame memory. The video signal is processed, and the display video signal is output. When the controller receives the low-delay processing instruction, the video signal of the at least one frame starts processing to be stored in the frame memory. Then, after the first predetermined time has elapsed, before the storage process is completed, at least the image quality improvement process is started. The video processing module is configured to control the video processing module, and to start the double speed processing after the second predetermined time has elapsed from the start of the at least image quality improvement processing and before the completion of the at least image quality improvement processing. Control the module.

It is a block diagram of the television receiver of embodiment. It is a block diagram for demonstrating the video signal processing of a television receiver, FIG. 2 (A) has shown the case where the low delay process is OFF, and FIG. 2 (B) has shown the case where the low delay process is ON. 6 is a time chart for explaining a delay time of the television 101. FIG. It is a figure for demonstrating the display state in the display panel by the kind of display video signal, FIG. 4 (A) is a display state of the 720p video signal displayed on the 1080p display panel, FIG.4 (B) is 1080p. The display state of the 480p video signal displayed on the display panel is shown. It is a block diagram for demonstrating the signal processing of the television receiver of embodiment. It is the block diagram which showed the relationship between the synchronizing signal of an input video signal and the synchronizing signal of a display video signal for demonstrating a synchronous compensation module. It is a flowchart for demonstrating the flow of the video signal process of the television receiver of embodiment. It is a figure which shows the display screen for demonstrating the processing mode selection method in the television receiver of embodiment. FIG. 9A is an explanatory diagram for explaining the “overtaking phenomenon”, FIG. 9A shows a written video, FIG. 9B shows a read video, and FIG. 9C shows a time chart at the time of writing / reading. ing. It is a time chart for demonstrating the signal processing in this Embodiment. It is a time chart for demonstrating the delay time of the television receiver of embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a video display apparatus according to an embodiment of the present invention.

  As shown in FIG. 1, a television receiver (television) 1 as a video display device includes a tuner 11, an external input terminal 12, a pre-processing module 13, a frame memory 14, a video processing module 30, and an operation. An input unit 21, a controller 20, an audio processor 16, and an audio delay processing module 17 are provided. For convenience of explanation, the frame memory 14 and the video processing module 30 are distinguished from each other. However, the frame memory 14 can be regarded as a part of the function of the video processing module 30, and the frame memory 14, the video processing module 30, and the like. May be mounted on one system LSI.

  In the television 1, the antenna 2 is connected to the tuner 11, and the game device 3 having the game operation unit 4 is connected to the external input terminal 12, and an image is displayed on the display panel 15 that is a display module, and the speaker 18 that is an audio output module. Output audio.

  The tuner 11 selects / processes broadcast signals such as satellite broadcasts such as BS broadcasts and CS broadcasts, and terrestrial broadcasts, and outputs video signals and audio signals. The tuner 11 can also receive a signal from a communication line such as a cable TV line.

  The external input terminal 12 receives, as an external input, a video signal / audio signal from an external device such as a game machine 3 and a hard disk recorder in a signal form such as a composite signal, an S terminal signal, a color difference signal, and a D-sub signal. .

  The pre-processing module 13 receives a plurality of video signals / audio signals and the like from the tuner 11 and the external input terminal 12, selects one of the video signals / audio signals, performs pre-processing, and stores the video signal in the frame memory 14 The audio signal is output to the audio processor 16.

  The video signal is signal-processed by a video processing module 30 described later in detail through the frame memory 14, and the display video signal is output to the display panel 15. The audio signal is processed by the audio processor 16 and then output to the speaker 18 via the audio delay processing module 17 that delays the audio signal in accordance with the delay time of the video signal.

  The operation input unit 21 generates an operation signal based on a user operation and gives it to the controller 20. The controller 20 is a CPU that controls the entire television 1 based on an operation signal from the operation input unit 21. The controller 20 determines whether to operate the video processing module 30 by turning on the low delay processing operation with a short delay time of the display video signal with respect to the input video signal or by turning off the low delay processing operation. It can be switched.

  The controller 20 can turn on and off the low-delay processing operation according to the video mode. The television 1 can operate in accordance with, for example, modes such as Omakase / Azayaka / Standard / TV Pro / Movie Pro / Game / PC as video modes. For example, the controller 20 turns on the low-delay processing operation when a game or PC is selected as the video mode. Note that the controller 20 is configured to perform normal processing with the operation of the low-delay processing turned off when the video mode is Auto / Azure / Standard / TV Pro / Movie Pro. The operation input unit 21 may directly specify on / off of the operation of the low delay processing. In this case, the controller 20 operates the operation of the low delay processing based on the operation signal from the operation input unit 21. On and off.

  In the case of the low delay processing ON mode, the controller 20 turns on the low delay processing operation and operates the video processing module 30.

  Here, for comparison with the television 1, a television 101 that shortens the delay time by a method different from the television 1 will be described. The television 101 employs a frame memory 114A and a video processing module 130 in place of the frame memory 14 and the video processing module 30, respectively. In the television 101, when the low delay process for reducing the delay time is selected, the controller 20 performs control so that a part of the signal processing by the video processing module 130 is omitted.

  That is, the television 101 performs all signal processing of the video processing module 130 shown in FIG. 2A when the low delay processing is OFF (low delay processing OFF mode), whereas when the low delay processing is ON ( In the low delay processing ON mode), as shown in FIG. 2B, only the image quality improvement processing by the image quality improvement module 134 is performed.

  The video processing module 130 of the television 101 includes an IP conversion / NR (noise reduction) module 131, a scaler 133, a frame memory 114B, a high image quality module 134, a super-resolution module 132, a double speed processing module 136, Have

  An IP (Interlace / Progressive) conversion / NR (Noise Reduction) module 131 performs an IP conversion process for converting an interlace video signal into a progressive video signal, and also provides video roughness, flicker, blocking noise, and mosquito. Perform noise reduction processing to reduce noise. That is, the IP conversion / NR module 131 includes an IP conversion processing module and an NR module. Note that the IP conversion process is not performed on progressive input video signals. Further, when the noise of the input video signal is low, the noise reduction process may be omitted. That is, the IP conversion / NR module 131 performs at least one of IP conversion and noise reduction processing.

  The scaler 133 performs a scaling process in accordance with the specifications of the display panel 15 on a video signal different from the specifications of the display panel 15. For example, when the aspect ratio of the input video signal is 4: 3 and the aspect ratio of the display panel is 16: 9, the scaler 133 converts the input video signal into a display video signal having an aspect ratio of 16: 9.

  The frame memory 114B stores (stores) video signals in units of frames in the same manner as the previous frame memory 114A for high image quality processing by the subsequent image quality improving module 134. Note that the frame memory 114A and the frame memory 114B may use different storage areas of one memory as long as each can store a video signal of at least one frame.

  In order to improve the image quality of the video, the image quality enhancement module 134 is, for example, color correction (gamma correction, white balance adjustment, brightness adjustment, contrast adjustment), sharpness adjustment, contour enhancement (edge enhancement), response speed improvement, etc. Perform high image quality processing.

  The super-resolution module 132, which is a high-resolution module, generates new pixel value data between pixels, creates a high frequency component, and sharpens it, so that an image exceeding the original resolution of the image can be obtained. Generate. That is, the original pixel value is estimated from the low-resolution video signal that is the first resolution and the number of pixels is increased, thereby restoring the high-resolution video signal that is the second resolution. Here, the “original pixel value” is, for example, an image obtained when the same subject as that obtained when a low resolution (first resolution) video signal is captured with a high resolution (second resolution) camera. A value indicated by each pixel of the signal. “Increase the number of pixels by estimation” means to capture the characteristics of the target video, estimate the original pixel value from the video with high correlation within the same frame or between frames, and create a new pixel. This means that the corresponding pixel value is used. That is, video correlation is used. The super-resolution module 132 uses a known technique, for example, a technique for restoring an image having a frequency component higher than the Nyquist frequency determined by the sampling period of the input image.

  The double speed processing module 136 performs double speed processing that doubles the frame frequency to 100 Hz when the frame frequency is 50 Hz, and 120 Hz when the frame frequency is 60 Hz to reduce the afterimage feeling. As the double speed processing, a method of generating an interpolated frame to be inserted between two consecutive frames based on motion compensation prediction may be used, or a so-called “simple double swing method” in which the same video is simply displayed twice. (Simple double repeat method) ".

  Here, the delay time resulting from the signal processing in each module will be described. Since the frame memory 114A and the frame memory 114B store and output the video signal in units of frames, each causes a delay time of one frame. The double speed processing module 136 also causes a delay time of one frame. In the following description, the frame frequency is 60 Hz as an example. In this case, one frame corresponds to approximately 16.7 ms.

  For this reason, as shown in FIG. 3, in the television 101, for example, a delay time of about 50 ms of 3 frames occurs in the low delay processing OFF mode, but in the low delay processing ON mode, the delay occurs. Time can be reduced to 33.3 ms for 2 frames.

  However, as shown in FIG. 4, when the input video signal is 720p or 480p smaller than the specification (1080p) of the display panel 15, a time for displaying the non-signal area (black area) at the top and bottom of the screen is generated. Therefore, the delay time is longer, 38.3 ms and 41.3 ms, respectively. Since the scaling process is performed in the low delay processing OFF mode, the delay time is 50 ms, which is the same as in the case of 1080p, even when the input video signal is 720p or 480p.

  That is, in the television 101, the image quality improvement module 134 has a specification that can process only the video signal read directly from the frame memory. Therefore, even in the low-delay processing mode, the image from the frame memory immediately before the image quality improvement processing 4 Need to capture signal. In this case, in the configuration in which the video signal is read from the frame memory 114B, the video signal is stored twice in the frame memory, so that the delay time reduction effect is small. Therefore, as shown in FIG. 2B, the television 101 realizes low delay processing with a minimum delay time by reading the video signal from the frame memory 114A. However, since the television 101 cannot perform IP conversion processing / NR processing and scaler processing in the low delay processing mode, it cannot process interlace signals such as 480i or 1080i. However, when the progressive signal is non-scaling (Dot By Dot), the delay time can be shortened. In other words, the television 101 can reduce the delay time when the low-delay processing mode is selected under a predetermined restriction.

  On the other hand, the television 1 of the present embodiment has a processing module similar to the television 101 shown in FIG. FIG. 5 is a block diagram showing the detailed configuration of FIG. 1, particularly the specific configuration of the video processing module 30. The IP conversion / NR module 31, the scaler 33, the image quality enhancement module 34, the super-resolution module 32, and the double speed processing module 36 in FIG. 5 are respectively the IP conversion / NR module 131, the scaler 133, and the image quality in FIG. This is a module that performs the same processing as the conversion module 134, the super-resolution module 132, and the double speed processing module 136.

  As shown in FIG. 5, the television 1 according to the present embodiment is different from the television 101 in that the memory corresponding to the frame memory 114B is omitted and the order of signal processing in the video processing module 30 is different. That is, since the video analysis module 22 can perform analysis processing using the video signal stored in the frame memory 14, the frame memory 114B that the television 101 has is unnecessary, and the high image quality module 34 It is not a specification that requires reading video directly from memory. Therefore, the television 1 includes a frame memory 14, an IP conversion / NR module 31, a super-resolution module 32, a scaler 33, an image quality enhancement module 34, a double speed processing module 36, a video analysis module 22, A synchronization signal generation module 41, a clock 42, a synchronization correction module 43, and a display synchronization signal generation module 44 are included. Note that the function of the module having the same name as the module already described in the television 101 is the same, and thus the description thereof is omitted. The video analysis module 22, the synchronization signal generation module 41, the clock 42, the synchronization correction module 43, and the display synchronization signal generation module 44 also have the television 101, but the description thereof is omitted.

  The video analysis module 22 analyzes the video signal stored in the frame memory 14 and outputs frame information used by the controller 20 for controlling the video processing module 30. That is, the video analysis module 22 divides the dynamic range of the luminance level into n, for example, and counts the number of pixels corresponding to each of the luminance levels 1 to n for one frame, thereby counting one frame. Or obtain brightness histogram data. The video analysis module 22 also detects the frequency distribution of the video signal, for example. In the television 101, the video analysis module analyzes the video signal stored in the frame memory 114B and outputs the video signal to the high image quality module 134 and the super-resolution module 132.

  As shown in FIG. 6, the synchronization signal generation module 41 generates a synchronization signal by separating it from the input video signal. The clock 42 generates a signal having a predetermined frequency, and the display synchronization signal generation module 44 generates a synchronization signal (display synchronization signal) of the display video signal displayed on the display panel 15 based on the signal generated by the clock 42. .

  The synchronization correction module 43 synchronizes the input synchronization signal of the video signal generated by the synchronization signal generation module 41 and the display synchronization signal generated by the display synchronization signal generation module 44. When a flat panel display (hereinafter referred to as FPD) is adopted as the display device, horizontal and vertical synchronization signals (hereinafter referred to as display synchronization signals) used for display in the FPD are horizontal and vertical synchronization signals of the input video signal. It is generated asynchronously with (input synchronization signal). The frequency of the FPD display synchronization signal has an allowable range. If the input synchronization signal is within this allowable range (hereinafter referred to as a synchronization compensation period), the FPD can always perform display based on the input video signal.

  However, if the display synchronization signal is not synchronized with the input synchronization signal, the display memory may overflow or underflow due to the difference between the frequency of the display synchronization signal and the frequency of the input synchronization signal. For this reason, the synchronization correction module 43 synchronizes the display synchronization signal with the input synchronization signal. The synchronization correction module 43 generates a display synchronization signal synchronized with an input synchronization signal in a predetermined synchronization compensation period, and outputs the display synchronization signal to the display panel 15.

  In the present embodiment, in the television 1, the video processing module 30 performs all the signal processing shown in FIG. 5 in the low delay processing ON (mode) as in the case of the low delay processing OFF (mode). . However, when the low delay processing is OFF, the controller 20 controls the video processing module 30 so that the signal processing is started after the storage processing of one frame of video signal in the frame memory 14 is completed. On the other hand, when the low delay processing is ON, the first waiting time after the storage processing is started without waiting for the completion of the storage processing of the video signal of one frame in the frame memory 14 is the first waiting time. The controller 20 controls the video processing module 30 to start signal processing after a predetermined time (T1) has elapsed. That is, it takes a time corresponding to one frame (about 16.7 ms) to complete the storing process of one frame of video signal in the frame memory 14, but when the low delay processing is ON, the time shorter than the time corresponding to one frame is used. Since the signal processing of the video processing module 30 is started after elapse of one predetermined time (T1), the delay time can be shortened by a time corresponding to about one frame. As the first predetermined time (T1), for example, 3.65 ms to 8.65 ms (about 0.2 to 0.5 frame period) can be employed.

  Further, in the present embodiment, when the low delay processing is ON, the modules 31 to 34 other than the double speed processing module 36 do not wait for the completion of the storage processing of the video signal of one frame in the frame memory 14. The video processing is performed so that the signal processing of the double speed processing module 36 is started after the second predetermined time (T2) which is the second waiting time from the start of the processing of the modules 31 to 34 without waiting for the completion of the processing. The controller 30 controls the module 30. That is, in the case of the low delay processing ON, the signal processing of the modules 31 to 34 is started after the elapse of the first predetermined time (T1) shorter than the time corresponding to one frame, and the signal processing of the modules 31 to 34 is started. Since the signal processing of the double speed processing module 36 is started after the elapse of the second predetermined time (T2), the delay time can be shortened by a time corresponding to about 1.5 frames. As the second predetermined time (T2), for example, 8.35 ms (about 0.5 frame period) can be employed.

  Hereinafter, the flow of processing of the video processing module 30 in the television 1 of the present embodiment will be described using the flowchart of FIG.

<Step S10> Process Selection Step As the signal processing mode, process selection is performed to turn on / off the operation of low delay processing with a short delay time of the display video signal with respect to the video signal. For example, a menu screen as shown in FIG. 8 is displayed on the display panel 15 and the controller 20 switches the designation of “game direct” from “off” to “on” with a remote controller or the like, whereby the controller 20 changes the video mode to the game mode. Switch to. When the video mode is switched to the game, the controller 20 selects the low delay processing ON mode. Conversely, when the user switches the designation of “game direct” from “on” to “off”, the controller 20 selects the low-delay processing OFF mode. Further, the game device 3 has a dedicated external input terminal, and when a signal is input from the game device 3, the controller 20 automatically sets the game mode and turns on the operation of the low delay processing. You may do it.

(Low delay processing OFF mode)
<Step S11> Storage Processing Start Process When the low delay processing is not ON (S10: No), that is, in the low delay processing OFF mode, the storage processing of the video signal for one frame in the frame memory 14 is started. The

<Step S12> Storage process completed?
The controller 20 controls the video processing module 30 not to start signal processing until the storage processing of one frame of video signal in the frame memory 14 is completed (S12: Yes).

<Step S13> Signal Processing Step When the video signal of one frame is completed (S12: Yes), the controller 20 controls the video processing module 30 to start signal processing. Then, the video processing module 30 performs signal processing for converting the video signal into a display video signal to be displayed on the display panel 15. That is, as shown in FIG. 5, the IP conversion / NR processing, the super-resolution processing, the scaling processing, the image quality enhancement processing, the synchronization correction processing, and the double speed processing are performed in order.

  If the analysis by the video analysis module 22 reveals that it is not preferable to display the video signal of the frame on the display panel 15 such as a signal that is extremely deteriorated, the controller 20 displays the frame. In some cases, the video signal is not output to the display panel 15.

<Steps S <b> 14 and S <b>15> Display Video Signal Output The video processing module 30 processes the video signal and outputs the display video signal to the display panel 15. Then, the signal-processed video is displayed on the display panel 15. Then, the processing from S11 is repeated until the end (S15: Yes).

(Low delay processing ON mode)
Next, signal processing in the low delay processing ON mode will be described with reference to FIGS. FIG. 9 is an explanatory diagram for explaining the overtaking phenomenon, and FIG. 10 is a timing chart for explaining the signal processing in the present embodiment.

<Step S16> Storage Processing Start Step In S10, when the low delay processing ON mode is selected (S10: Yes), the storage processing of the video signal for one frame in the frame memory 14 is started as in S11. <Step S17> First predetermined time elapsed?
The controller 20 measures the time from the start of the storage process in the frame memory 14 by a timer or the like (not shown), and until the first predetermined time (Delay value: T1) elapses (S17: Yes), The video processing module 30 is controlled so as not to start signal processing. In other words, the reading process of the video signal stored in the frame memory 14 is not started until the first predetermined time (Delay value: T1) elapses after the storage process in the frame memory 14 is started.

  This is to prevent the so-called “overtaking phenomenon” where the writing process and the reading process intersect.

  Here, the case where the writing video divided into 10 line groups (L1 to L10) as shown in FIG. 9A is pasted to the center of the display video as shown in FIG. 9B. The “overtaking phenomenon” will be described as an example. As shown in the upper part of FIG. 9C, the writing (storing) processing of the ten line groups (L1 to L10) to the memory is sequentially performed in time series. However, as shown in the lower part of FIG. 9C, due to the existence of areas corresponding to the upper and lower parts of the display image of FIG. 9B, the data of the line group just written is read out simultaneously with the start of the writing process. If you try to read it, you may read the data one frame before. This phenomenon is the “overtaking phenomenon”. Similarly, if the video signal stored in the frame memory 14 is read simultaneously with the start of the storage process or after an extremely short time has elapsed, a “passing phenomenon” occurs, and the stored signal cannot be read reliably. .

  Therefore, in the present embodiment, the first predetermined time is set before the signal processing of the modules 31 to 34 is started. FIG. 10 shows a case where a writing video divided into 10 line groups (L1 to L10) as shown in FIG. 9A is pasted on the center of the display video as shown in FIG. 9B. Signal processing is shown.

  As shown in FIG. 10A, writing (storing) processing of the ten line groups (L1 to L10) into the memory is sequentially performed in time series in accordance with the writing clock (WRITE). However, due to the overtaking phenomenon described above, the data of the line group just written cannot be read simultaneously with the start of the writing process or after a very short time.

  For this reason, the controller 20 sets the video processing module 30 so as not to start signal processing using the video signal stored in the frame memory 14 until the first predetermined time (T1) has elapsed (S17: Yes). I have control. The first predetermined time (T1) is appropriately determined depending on the resolution of the video signal or the display method of the display video signal.

<Step S18> Signal Processing Start Step of Modules 31 to 34 When the first predetermined time (T1) has elapsed (S17: Yes), the controller 20 waits for the completion of the storage processing of the video signal of one frame in the frame memory 14. Without control, each of the modules 31 to 34 in the video processing module 30 is controlled to start signal processing. Thereby, the video processing module 30 starts reading from the frame memory 14 according to the read clock (READ). Each of the modules 31 to 34 performs signal processing for converting a video signal into a display video signal to be displayed on the display panel 15 as in the low delay processing OFF mode. That is, as shown in FIG. 5, an IP conversion / NR process, a super-resolution process, a scaling process, a high image quality process, and a synchronization correction process are performed in order.

<Step S19> Has the second predetermined time elapsed?
The controller 20 measures the time after the modules 31 to 34 start signal processing using a timer or the like (not shown), and until the second predetermined time (Delay value: T2) elapses (S19: Yes), The video processing module 30 is controlled so that the signal processing of the double speed processing module 36 is not started. In other words, the signal processing results of the modules 31 to 34 are not read by the double speed processing module 36 until the second predetermined time (Delay value: T2) elapses after the signal processing of the modules 31 to 34 is started. This is to prevent the processing by the double speed processing module 36 from overtaking the processing of the modules 31 to 34. Note that the second predetermined time (T2) is appropriately determined by the resolution of the video signal or the display method of the display video signal, the writing and reading processing of a FIFO memory (not shown) used for the double speed processing by the double speed processing module 36, and the like.

<Step S20> Signal Processing Start Step of Module 36 When the second predetermined time (T2) has elapsed (S19: Yes), the controller 20 completes the storage processing of the video signal of one frame in the frame memory 14 and the modules 31 to 31. Without waiting for the completion of the signal processing 34, the double speed processing module 36 is controlled to start the double speed processing. Thereby, the double speed processing by the double speed processing module 36 is started. The double speed processing module 36 obtains the video signal after the double speed processing by writing the signal after the signal processing of the modules 31 to 34 to a FIFO memory (not shown) and reading the double speed.

<Steps S21 and S22> Display Video Signal Output FIG. 10C shows the double speed when the double speed processing by the double speed processing module 136 of the television 101 is performed after the processing by the modules 31 to 34 shown in FIG. The output after processing is shown. The double speed processing module 136 controls writing and reading of a FIFO memory (not shown) for double speed processing, and sequentially stores the outputs signal-processed by the modules 31 to 34. When the signal for one frame is stored, the double speed processing module 136 reads out the signal at double speed and outputs the video signal subjected to the double speed processing.

  That is, as shown in FIG. 10C, the double-speed processing module 136 receives the next frame after the signal processing of the modules 31 to 34, that is, the module 31 to the module 31 after one frame period elapses after reading from the frame memory 14. The signal processed by the signal 34 is given and double-speed processed and output.

  On the other hand, in the present embodiment, as shown in FIG. 10D, the double speed processing module 36, when the second predetermined time T2 elapses from the start of the signal processing of the modules 31 to 34, Reading of the signal processed by the signal 34 and written in the FIFO memory is started, and double speed processing is performed and output. FIG. 10D shows that a 0.5 frame period is set as the second predetermined time T2.

  The output of the double speed processing module 36 is output to the display panel 15 as a display video signal from the video processing module 30. Thus, the signal-processed video is displayed on the display panel 15. Then, the processing from S16 is repeated until the end (S22: Yes).

  As shown in FIG. 11, in the television 1 of the present embodiment, the low delay processing OFF mode has a delay time of 33.3 ms of 2 frames, and in the low delay processing ON mode, the delay time (3.65 by the modules 31 to 34). ˜8.65 (0.2 to 0.5 frame)) and the delay time ((8.35 (0.5 frame)) by the double speed processing module 36, about 12 ms to 17 ms (about 0.7 to 1) Further, as shown in Fig. 11, even when the input video signal is 720p or 480p smaller than the display panel (1080p), the scaling process is performed. Is 12 ms to 17 ms, which is the same as in the case of 1080p, and Fig. 11 shows an example in which the delay time is 12 ms.

  That is, in the low delay processing ON mode, the television 1 has a total delay time of, for example, 12 ms and the first and second predetermined times necessary for preventing the “overtaking phenomenon” (even if double speed processing is performed) Since it is the sum of T1, T2), it is a time shorter than the time corresponding to approximately one frame. Obviously, if the double speed processing is not performed, the delay time is further shortened.

  As described above, the television 1 of the present embodiment has the IP conversion / noise reduction processing, the scaling processing according to the display module, and the resolution of the video signal irrespective of ON / OFF of the operation of the low delay processing. And a controller 20 that controls the video processing module 30 so as to perform high resolution processing and double speed processing.

  That is, the television 1 of the present embodiment is capable of at least IP conversion / NR processing, scaling processing, super-resolution processing, and double speed processing even in the low delay processing ON mode. By using the system LSI, more complicated processing can be performed as necessary.

  In the television 1, since the IP conversion / NR processing, the scaling processing, the super-resolution processing, and the double speed processing are performed even in the low delay processing ON mode, the display video signal is high quality. Moreover, the delay time until obtaining the video signal after the double speed processing is sufficiently small.

  As described above, the television 1 of the present embodiment has a very small display delay when displaying game content and the like, and the display video and output sound are uncomfortable with the user's operation by the game operation unit 4. The video processing method of the television 1 can display a video that does not give the user an uncomfortable feeling when displaying game content or the like.

  The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1 ... Television receiver, 2 ... Antenna, 3 ... Game equipment, 4 ... Game operation part, 11 ... Tuner, 12 ... External input terminal, 13 ... Pre-processing module, 14 ... Frame memory, 15 ... Display panel, 16 ... Audio processor, 17 ... audio delay processing module, 18 ... speaker, 20 ... controller, 21 ... operation input unit, 22 ... video analysis module, 30 ... video processing module, 31 ... IP conversion / NR module, 32 ... super-resolution module 33 ... Scaler, 34 ... High image quality module, 36 ... Double speed processing module, 41 ... Synchronization signal generation module, 42 ... Clock, 43 ... Synchronization correction module, 44 ... Display synchronization signal generation module, 101 ... Television receiver, 114A, 114B ... frame memory, 130 ... video processing module, 31 ... IP conversion / NR module 132 ... super-resolution module 133 ... scaler, 134 ... image quality module, 136 ... doubling processing module

Claims (8)

A video processing module that outputs a display video signal generated by performing at least high image quality processing and double speed processing on the input video signal to the display module;
A controller for receiving an instruction of low delay processing with a short delay time of the display video signal with respect to the video signal;
A frame memory for storing at least one frame of the video signal;
The video signal processing module performs signal processing on the video signal stored in the frame memory and outputs the display video signal;
When the controller receives the low-delay processing instruction, after the first predetermined time elapses after the video signal of the at least one frame starts storing processing in the frame memory, before the storage processing is completed In addition, the video processing module is controlled so as to start the at least image quality improvement processing, and after the second predetermined time has elapsed from the start of the at least image quality improvement processing, at least before the completion of the at least image quality improvement processing. In addition, the video display device controls the video processing module to start the double speed processing.   When the controller receives an instruction for the low delay processing, the video processing module controls the video signal to perform at least one of IP conversion and noise reduction processing in addition to the image quality improvement processing. The video display device according to claim 1.   The video processing module has a high resolution module that increases the resolution of the video signal, and when the controller receives the low delay processing instruction, the controller performs the high resolution module in addition to the high image quality processing. The video display device according to claim 1, wherein the video display device is controlled to perform processing.   The frame analysis block according to claim 1, further comprising: a frame analysis block that analyzes the video signal of one frame stored in the frame memory and outputs frame information used by the controller to control the video processing module. Video display device. The video processing module generates a display video signal to be displayed on the display module by performing at least high image quality processing and double speed processing on the input video signal,
When the controller starts storing the video signal in the frame memory and receives the low-delay processing instruction, the controller starts the storage process in the frame memory after the video signal of the at least one frame starts. After the elapse of a predetermined time of 1 and before the completion of the storage process, the video processing module is controlled so as to start the at least high quality image processing, and at least a second predetermined time has elapsed since the start of the at least high quality image processing. Thereafter, the double speed processing is started before the processing of at least the high image quality processing is completed.   6. The video processing method according to claim 5, wherein at least one of IP conversion and noise reduction processing is included as the at least high image quality processing.   The controller controls the video processing module to start the signal processing after the video signal of the at least one frame has been stored in the frame memory when the controller has not received the low-delay processing instruction. The video display device according to claim 1, wherein the video display device is a video display device.   8. The controller according to claim 1, wherein the controller controls the video processing module so that the delay time is set to 12 msec to 17 msec or less when receiving the low-delay processing instruction. The video display apparatus as described in any one.

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