JP2009038351A - 半導体デバイス - Google Patents

半導体デバイス Download PDF

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Publication number
JP2009038351A
JP2009038351A JP2008163159A JP2008163159A JP2009038351A JP 2009038351 A JP2009038351 A JP 2009038351A JP 2008163159 A JP2008163159 A JP 2008163159A JP 2008163159 A JP2008163159 A JP 2008163159A JP 2009038351 A JP2009038351 A JP 2009038351A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
partially modified
modified region
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008163159A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009038351A5 (https=
Inventor
Damien Lenoble
ダミアン・ルノーブル
Nadine Collaert
ナディーネ・コラエルト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Publication of JP2009038351A publication Critical patent/JP2009038351A/ja
Publication of JP2009038351A5 publication Critical patent/JP2009038351A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2008163159A 2007-06-25 2008-06-23 半導体デバイス Pending JP2009038351A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP07012358A EP2009679A1 (en) 2007-06-25 2007-06-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2009038351A true JP2009038351A (ja) 2009-02-19
JP2009038351A5 JP2009038351A5 (https=) 2012-07-05

Family

ID=38647645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008163159A Pending JP2009038351A (ja) 2007-06-25 2008-06-23 半導体デバイス

Country Status (3)

Country Link
US (1) US20090020786A1 (https=)
EP (1) EP2009679A1 (https=)
JP (1) JP2009038351A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013514673A (ja) * 2009-12-17 2013-04-25 アプライド マテリアルズ インコーポレイテッド Ｎｍｏｓエピ層の形成方法
KR20180011854A (ko) * 2015-06-24 2018-02-02 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. 핀 리세스가 없고 게이트-스페이서 풀-다운이 없는 ｆｉｎｆｅｔ 스페이서 에칭

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100308440A1 (en) * 2009-06-08 2010-12-09 Globalfoundries Inc. Semiconductor structures and methods for stabilizing silicon-comprising structures on a silicon oxide layer of a semiconductor substrate
US8124507B2 (en) * 2009-06-24 2012-02-28 Panasonic Corporation Semiconductor device and method for fabricating the same
WO2011013271A1 (ja) * 2009-07-27 2011-02-03 パナソニック株式会社 半導体装置の製造方法及びプラズマドーピング装置
US8071467B2 (en) 2010-04-07 2011-12-06 Micron Technology, Inc. Methods of forming patterns, and methods of forming integrated circuits
US8357579B2 (en) * 2010-11-30 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits
US9000498B2 (en) * 2013-06-28 2015-04-07 Stmicroelectronics, Inc. FinFET with multiple concentration percentages
US9553174B2 (en) * 2014-03-28 2017-01-24 Applied Materials, Inc. Conversion process utilized for manufacturing advanced 3D features for semiconductor device applications
US10297448B2 (en) * 2015-11-30 2019-05-21 International Business Machines Corporation SiGe fins formed on a substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3859821B2 (ja) * 1997-07-04 2006-12-20 株式会社半導体エネルギー研究所 半導体装置
US6432798B1 (en) * 2000-08-10 2002-08-13 Intel Corporation Extension of shallow trench isolation by ion implantation
JP2004103899A (ja) * 2002-09-11 2004-04-02 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
KR100476940B1 (ko) * 2003-06-20 2005-03-16 삼성전자주식회사 기판으로부터 수직으로 연장된 게이트 채널을 갖는디램기억 셀 및 그 제조방법
US7049662B2 (en) * 2003-11-26 2006-05-23 International Business Machines Corporation Structure and method to fabricate FinFET devices
US7384838B2 (en) * 2005-09-13 2008-06-10 International Business Machines Corporation Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures
DE102006030264B4 (de) * 2006-06-30 2008-08-28 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Transistoren mit einem Kanal mit biaxialer Verformung, die durch Silizium/Germanium in der Gateelektrode hervorgerufen wird

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013514673A (ja) * 2009-12-17 2013-04-25 アプライド マテリアルズ インコーポレイテッド Ｎｍｏｓエピ層の形成方法
KR20180011854A (ko) * 2015-06-24 2018-02-02 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. 핀 리세스가 없고 게이트-스페이서 풀-다운이 없는 ｆｉｎｆｅｔ 스페이서 에칭
JP2018518846A (ja) * 2015-06-24 2018-07-12 ヴァリアン セミコンダクター イクイップメント アソシエイツ インコーポレイテッド フィン・リセスなし、ゲート−スペーサのプルダウンなしのＦｉｎＦＥＴのスペーサ・エッチング方法
KR102590843B1 (ko) 2015-06-24 2023-10-19 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. 3차원 디바이스 및 ｆｉｎｆｅｔ 디바이스 프로세싱 방법 및 ｆｉｎｆｅｔ 디바이스 형성 방법

Also Published As

Publication number Publication date
US20090020786A1 (en) 2009-01-22
EP2009679A1 (en) 2008-12-31

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