CN111668309A - 具有扩散阻挡间隙件部分的场效应晶体管 - Google Patents
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Abstract
本发明涉及具有扩散阻挡间隙件部分的场效应晶体管,揭露场效应晶体管的结构以及形成场效应晶体管的方法。在由半导体材料组成的主动区上方设置该场效应晶体管的栅极结构。邻近该栅极结构设置第一侧壁间隙件。第二侧壁间隙件包括设置于该第一侧壁间隙件与该主动区之间的部分。该第一侧壁间隙件由低k介电材料组成。
Description
技术领域
本发明涉及半导体装置制造及集成电路,尤其涉及场效应晶体管的结构以及形成场效应晶体管的方法。
背景技术
用于场效应晶体管的装置结构通常包括本体区,定义于该本体区中的源极及漏极,以及经配置以切换在操作期间在该本体区中所形成的沟道中的载流子流的栅极电极。当向该栅极电极施加超过指定阈值电压的控制电压时,在该源极与漏极之间的该沟道中发生载流子流,从而产生装置输出电流。对于平面场效应晶体管,该本体区及沟道位于支持该栅极电极的衬底的顶部表面下方。
鳍式场效应晶体管(fin-type field-effect transistor;FinFET)是非平面装置结构,与平面场效应晶体管相比,它可被更密集地封装于集成电路中。FinFET可包括由半导体材料组成的一个或多个鳍件,重掺杂源/漏区,以及环绕位于该源/漏区之间的该鳍件本体中的沟道的栅极电极。与平面晶体管相比,在该栅极电极与鳍件本体之间的该环绕布置改进对该沟道的控制并减少该FinFET处于“关闭”状态时的漏电流。相应地,与平面晶体管相比,这促进较低的阈值电压,并导致改进的性能以及降低的功耗。
场效应晶体管的装置结构包括经设置以围绕栅极电极的侧壁间隙件。为了减少电容,该侧壁间隙件可由低k介电材料组成,与其它类型的介电材料例如氮化硅相比,该低k介电材料以较低的介电常数为特征。可通过使用含碳氧化物作为该低k介电材料来实现电容的减少。不过,包含于该侧壁间隙件中的该碳是可迁移的,其允许从该侧壁间隙件至该场效应晶体管的其它部分中的扩散。不想要的碳的存在可负面影响源/漏区中的掺杂物分布。例如,碳可与源/漏区中的掺杂物例如硼簇聚,从而减少掺杂物活化。
在替代栅极制程期间,低k侧壁间隙件还可能容易受到侵蚀。在不太严重的情况下,该侵蚀导致栅极电极延长,从而增加装置静电的变异性。在较严重的情况下,该侵蚀可能允许形成连接通过移除伪栅极所形成的空间与源/漏区的其中一个或两个的路径。随后,在形成金属栅极时用导体填充该路径。此导体填充路径可在该金属栅极电极与该源/漏区之间生成短路。
需要改进的场效应晶体管的结构以及形成场效应晶体管的方法。
发明内容
在一个实施例中,一种结构包括位于由半导体材料组成的主动区上方的栅极结构,与该栅极结构相邻的第一侧壁间隙件,以及包括设置于该第一侧壁间隙件与该主动区之间的部分的第二侧壁间隙件。该第一侧壁间隙件由低k介电材料组成。
在一个实施例中,一种方法包括在由半导体材料组成的主动区上方形成栅极结构,形成邻近该栅极结构的第一侧壁间隙件,以及形成设置于该第一侧壁间隙件与该主动区之间的第二侧壁间隙件的部分。该第一侧壁间隙件由低k介电材料组成。
附图说明
包含于并构成本说明书的一部分的附图示例说明本发明的各种实施例,并与上面所作的有关本发明的概括说明以及下面所作的有关实施例的详细说明一起用以解释本发明的实施例。
图1显示依据本发明的实施例处于制程方法的初始制造阶段的装置结构的顶视图。
图2显示大体沿图1中的线2-2所作的剖视图。
图2A显示大体沿图1中的线2A-2A所作的剖视图。
图3-8显示处于图2之后的连续制造阶段的该装置的剖视图。
图9及10显示依据本发明的实施例的装置结构的剖视图。
具体实施方式
请参照图1、2、2A并依据本发明的实施例,半导体鳍件10设置于衬底12上并自衬底12的顶部表面向上突出。通过使用例如侧壁图像转移(sidewall imaging transfer;SIT)制程、自对准双重图案化(self-aligned double patterning;SADP),或自对准四重图案化(self-aligned quadruple patterning;SAQP),可自衬底12的半导体材料或形成于衬底12上的外延层图案化半导体鳍件10,该半导体鳍件包含单晶半导体材料,例如单晶硅。各半导体鳍件10具有顶部表面11以及自顶部表面11延伸至衬底12的侧壁13。
设置介电层14以包围并掩埋半导体鳍件10的下方部分,且半导体鳍件10的上方部分暴露于介电层14的顶部表面17上方。在一个实施例中,介电层14可由通过化学气相沉积所沉积的介电材料例如二氧化硅组成。在沉积之后,可通过蚀刻制程凹入介电层14,以暴露半导体鳍件10的该上方部分。半导体鳍件10的该上方部分自介电层14的顶部表面17向上延伸至各半导体鳍件10的顶部表面11,且半导体鳍件10的该下方部分与介电层14电性隔离。
设置栅极结构16以横跨半导体鳍件10及介电层14的顶部表面17。栅极结构16横跨半导体鳍件10的长度纵向取向并可被切割成分段,栅极结构16在隔开的位置与半导体鳍件10中的相应沟道区叠置。各栅极结构16包括侧壁15,该侧壁自介电层14向上延伸并与半导体鳍件10的顶部表面11及侧壁13叠置。
栅极结构16可包括由多晶半导体材料例如多晶硅组成的伪栅极,以及设置于该伪栅极与半导体鳍件10的外表面(例如,顶部表面11)之间的薄介电层(例如,二氧化硅)。通过在半导体鳍件10及介电层14上方沉积该伪栅极及薄介电层的该材料并用光刻及蚀刻制程图案化该材料,可形成栅极结构16。栅极结构16构成占位体,其随后被移除并由其它栅极结构替代。
在各栅极结构16的顶部表面上设置栅极覆盖层18。栅极覆盖层18可由通过化学气相沉积所沉积的介电材料例如氮化硅组成。
请参照图3,其中类似的附图标记表示图2中类似的特征,且在下一制造阶段,在形成栅极结构16以后,在半导体鳍件10的顶部表面11及侧壁13、介电层14,以及栅极结构16的侧壁15上方形成介电层20。介电层20可由介电材料例如氮化硅组成,其通过原子层沉积共形沉积并可伴随所采用的拓扑结构在所有涂布表面上具有名义上相等的厚度。在一个实施例中,介电层20可具有在一(1)纳米至四(4)纳米的范围内的厚度。在形成介电层20之后,可接着将离子注入半导体鳍件10,以提供源/漏延伸区及环状区,以及调节阈值电压。介电层20充当在注入期间保护半导体鳍件10的屏蔽层。
在各半导体鳍件10的顶部表面11及侧壁13,介电层14,以及各栅极结构16的侧壁15上方形成介电层22。在沉积介电层22之前所沉积的介电层20设置于介电层22与半导体鳍件10的顶部表面11及侧壁13,介电层14,以及栅极结构16的侧壁15之间。介电层22可由介电常数小于介电层20的介电常数的介电材料组成。例如,介电层22可由含碳的低k介电材料组成,例如碳掺杂氧化硅,如SiOCN或SiOC。介电层22可通过例如原子层沉积共形沉积,并可伴随所采用的拓扑结构在所有涂布表面上具有名义上相等的厚度。
在该注入之后,不移除或另外蚀刻介电层20,其意味着在沉积介电层22之前,不移除或另外蚀刻介电层20。相反,介电层20被保留于各半导体鳍件10的顶部表面11及侧壁13、介电层14,以及各栅极结构16的侧壁15上,并最终部分出现于完整装置结构中。由于该保留部分,因此介电层20不是完全牺牲的,而是只是半牺牲的。
请参照图4,其中类似的附图标记表示图3中类似的特征,且在下一制造阶段,通过定向或非等向性蚀刻制程例如反应离子蚀刻来蚀刻介电层20及介电层22,从而形成双层间隙件24。各双层间隙件24邻近栅极结构16的其中关联一个的侧壁15设置。各双层间隙件24包括自介电层20通过该非等向性蚀刻制程所形成的内侧壁间隙件26。各内侧壁间隙件26具有L形状,其包括介电层20的部分27以及自部分27的端部向上延伸的介电层20的部分28。介电层20的各部分27设置于关联半导体鳍件10的顶部表面11上方并与其直接接触。介电层20的各部分28邻近关联栅极结构16的侧壁15设置并与其具有直接接触关系。
各双层间隙件24还包括自介电层22通过该非等向性蚀刻制程所形成的外侧壁间隙件30。介电层20的部分28的其中之一在各外侧壁间隙件30与关联栅极结构16的侧壁15之间沿水平方向设置。介电层20的部分27的其中之一在各外侧壁间隙件30与关联栅极鳍件10的顶部表面11之间沿直立方向设置。可自邻近双层间隙件24的各半导体鳍件的顶部表面11通过该非等向性蚀刻制程移除介电层20、22。
通过使用等向性蚀刻制程及/或非等向性蚀刻制程蚀刻成形开口并自半导体鳍件10外延生长半导体材料,在各半导体鳍件10中可形成源/漏区32。本文中所使用的术语“源/漏区”是指可充当场效应晶体管的源极或漏极的半导体材料掺杂区。源/漏区32可由外延半导体材料组成,其通过外延生长制程生长于该开口中并采取位于半导体鳍件10内部的该开口的形状。在该开口的外部,源/漏区32的该外延半导体材料可采取小平面形状。该外延半导体材料可由例如硅锗(SiGe)或碳掺杂硅(Si:C)组成,且可包括在生长期间所引入的掺杂物,以提供给定的导电类型。为形成p型场效应晶体管,可用提供p型导电性的p型掺杂物(例如,硼(B))掺杂源/漏区32的该半导体材料。为形成n型场效应晶体管,可用提供n型导电性的n型掺杂物(例如,磷(P)及/或砷(As))掺杂源/漏区32的该半导体材料。
在源/漏区32的该生长期间并在该生长之后,介电层20的部分27设置于外侧壁间隙件30与源/漏区32之间。介电层20的部分27充当扩散阻挡层,以防止或减少迁移原子种类例如碳原子自外侧壁间隙件30向源/漏区32的热致迁移。
请参照图5,其中类似的附图标记表示图4中类似的特征,且在下一制造阶段,顺序沉积共形接触蚀刻停止层(conformal contact etch stop layer;CESL)34以及层间介电层36。CESL 34可由通过原子层共形沉积所沉积的薄介电材料层例如氮化硅组成。层间介电层36可由介电材料例如二氧化硅组成,其通过化学气相沉积覆被(blanket)沉积并被平坦化。CESL 34涂布源/漏区32及外侧壁间隙件30,并设置于层间介电层36的部分与源/漏区32之间。
请参照图6,其中类似的附图标记表示图5中类似的特征,且在下一制造阶段,移除栅极结构16及它们的栅极覆盖层18,以定义开口38作为替代金属栅极制程的部分。在栅极结构16的该移除之后,接着在各开口38内部暴露内侧壁间隙件26的部分28。
请参照图7,其中类似的附图标记表示图6中类似的特征,且在下一制造阶段,在移除栅极结构16以后,通过蚀刻制程,例如通过使用缓冲氢氟酸溶液的湿化学蚀刻制程,在各开口38内部移除内侧壁间隙件26的暴露部分28。该蚀刻制程可相对于构成该外侧壁间隙件的该介电材料移除构成内侧壁间隙件26的该介电材料。在该蚀刻制程期间,外侧壁间隙件30掩蔽并覆盖内侧壁间隙件26的部分27。
内侧壁间隙件26的部分27设置于外侧壁间隙件30下方,因此在外侧壁间隙件30与各半导体鳍件10的顶部表面11之间。各部分27横向设置于关联的上方侧壁间隙件30的内边缘31与外边缘33之间。在移除栅极结构16的该蚀刻制程期间,内侧壁间隙件26的部分27保护下方源/漏区32及/或半导体鳍件10免于蚀刻,以减少在后续形成的金属栅极结构与源/漏区32之间短路的风险。内侧壁间隙件26的部分28的该移除稍微扩大开口38。此扩大由内侧壁间隙件26的该材料与外侧壁间隙件30的该材料之间的蚀刻选择性控制并抑制。
请参照图8,其中类似的附图标记表示图7中类似的特征,且在下一制造阶段,在移除内侧壁间隙件26的部分28以后,在各开口38中形成栅极结构及栅极覆盖层42,以完成场效应晶体管50的形成,该场效应晶体管具有代表形式的鳍式场效应晶体管,以半导体鳍件10的该半导体材料提供相应主动区。各栅极结构40可包括栅极电极39以及设置于栅极电极39与各叠置半导体鳍件10之间的栅极介电质41。栅极电极39可包括一个或多个共形阻挡金属层及/或功函数金属层,例如由碳化铝钛及/或氮化钛组成的金属层,以及/或者由导体例如钨、钴或铝组成的金属栅极填充层。栅极介电质41可由高k介电材料例如氧化铪组成。栅极覆盖层42可由介电材料例如氮化硅组成,且可形成于栅极结构40上方,该栅极结构可相对于外侧壁间隙件30被凹入。
各外侧壁间隙件30的内边缘31与关联的栅极结构40直接接触,且各外侧壁间隙件30的外边缘33以外侧壁间隙件30的厚度与内边缘31隔开。各内侧壁间隙件26的部分27可自关联外侧壁间隙件30的内边缘31以均匀的厚度延伸至关联侧壁间隙件30的外边缘33。在一个实施例中,各部分27与相应的上方外侧壁间隙件30的该内边缘对齐。各部分27可在关联外侧壁间隙件30的内边缘31下方的区域上与关联栅极结构40直接接触。在一个实施例中,各部分27可在直接位于关联外侧壁间隙件30的内边缘31下方的区域上与关联栅极结构40直接接触。各部分27可终止于或接近外侧壁间隙件30的外边缘33。
在形成栅极结构40以后,在层间介电层36上方形成覆盖层44。在延伸穿过覆盖层44、层间介电层36,以及CESL 34至源/漏区32的接触开口中形成接触46。接触46可包含经沉积并平坦化的金属硅化物,例如硅化钨、硅化钛、硅化镍,或硅化钴,以及金属填充物,例如钨。
请参照图9、10,其中类似的附图标记表示图8中类似的特征,且依据本发明的替代实施例,可基于使用主动区而不是半导体鳍件10如前所述形成场效应晶体管50。尤其,可将场效应晶体管50制造为平面装置结构而不是鳍式装置结构。
例如并如图9中所示,各场效应晶体管50可包括由块体半导体衬底52的部分所提供的单晶半导体材料(例如,单晶硅)所构成的主动区。各内侧壁间隙件26的部分27在块体半导体衬底52的顶部表面48与外侧壁间隙件30之间沿直立方向设置,且在一个实施例中,可直接接触块体半导体衬底52的顶部表面48设置。可通过提供介电层14的浅沟槽隔离区在块体半导体衬底52中定义该主动区。
作为另一个例子并如图10中所示,各场效应晶体管50可包括由绝缘体上半导体(semiconductor-on-insulator;SOI)晶圆54的装置层56的部分所提供的单晶半导体材料(例如,单晶硅)构成的主动区。除装置层56以外,SOI晶圆54还包括埋置绝缘体层58以及衬底60。装置层56通过中间埋置绝缘体层58与衬底60隔开,且可远薄于衬底60。装置层56与衬底60可由单晶半导体材料组成,例如单晶硅,且埋置绝缘体层58可为埋置氧化物(buriedoxide;BOX)层。各内侧壁间隙件26的部分27沿直立方向在外侧壁间隙件30与装置层56的顶部表面57之间沿直立方向设置,且在一个实施例中,可直接接触装置层56的顶部表面57设置。可通过提供介电层14的浅沟槽隔离区在该装置层中定义该主动区,且该浅沟槽隔离区可穿过装置层56的全部厚度至埋置绝缘体层58。
如上所述的方法用于集成电路芯片的制造中。制造者可以原始晶圆形式(例如作为具有多个未封装芯片的单个晶圆)、作为裸芯片,或者以封装形式分配所得的集成电路芯片。可将该芯片与其它芯片、分立电路组件和/或其它信号处理装置集成,作为中间产品或最终产品的部分。该最终产品可为包括集成电路芯片的任意产品,例如具有中央处理器的电脑产品或智能手机。
本文中引用的由近似语言例如“大约”、“大致”及“基本上”所修饰的术语不限于所指定的精确值。该近似语言可对应于用以测量该值的仪器的精度,且除非另外依赖于该仪器的精度,否则可表示所述值的+/-10%。
本文中引用术语例如“直立”、“水平”等作为示例来建立参考框架,并非限制。本文中所使用的术语“水平”被定义为与半导体衬底的传统平面平行的平面,而不论其实际的三维空间取向。术语“直立”及“正交”是指垂直于如刚刚所定义的水平面的方向。术语“横向”是指在该水平平面内的方向。
与另一个特征“连接”或“耦接”的特征可与该另一个特征直接连接或耦接,或者可存在一个或多个中间特征。如果不存在中间特征,则特征可与另一个特征“直接连接”或“直接耦接”。如存在至少一个中间特征,则特征可与另一个特征“非直接连接”或“非直接耦接”。在另一个特征“上”或与其“接触”的特征可直接在该另一个特征上与其直接接触,或者可存在一个或多个中间特征。如果不存在中间特征,则特征可直接在另一个特征“上”或与其“直接接触”。如存在至少一个中间特征,则特征可“不直接”在另一个特征“上”或与其“不直接接触”。
对本发明的各种实施例所作的说明是出于示例目的,而非意图详尽无遗或限于所揭露的实施例。许多修改及变更对于本领域的普通技术人员将显而易见,而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进,或者使本领域的普通技术人员能够理解本文中所揭露的实施例。
Claims (20)
1.一种结构,包括:
主动区,由半导体材料组成;
栅极结构,位于该主动区上方;
第一侧壁间隙件,与该栅极结构相邻,该第一侧壁间隙件由低k介电材料组成;以及
第二侧壁间隙件,包括设置于该第一侧壁间隙件与该主动区之间的部分。
2.如权利要求1所述的结构,其中,该低k介电材料包含碳,且该第二侧壁间隙件的该部分由氮化硅组成。
3.如权利要求1所述的结构,其中,该低k介电材料为碳掺杂氧化硅,且该第二侧壁间隙件的该部分由氮化硅组成。
4.如权利要求1所述的结构,其中,该第二侧壁间隙件的该部分由具有第一介电常数的介电材料组成,且该低k介电材料具有小于该第一介电常数的第二介电常数。
5.如权利要求1所述的结构,其中,该第一侧壁间隙件具有与该栅极结构直接接触的内边缘,以及外边缘,且该第二侧壁间隙件的该部分自该内边缘延伸至该外边缘。
6.如权利要求5所述的结构,其中,该第二侧壁间隙件的该部分具有均匀的厚度。
7.如权利要求5所述的结构,其中,该第二侧壁间隙件的该部分与位于该第一侧壁间隙件的该内边缘下方的该栅极结构直接接触。
8.如权利要求5所述的结构,其中,该第二侧壁间隙件的该部分终止于该第一侧壁间隙件的该外边缘。
9.如权利要求1所述的结构,还包括:
源/漏区,与该主动区关联,
其中,该第二侧壁间隙件的该部分设置于该第一侧壁间隙件与该源/漏区之间。
10.如权利要求1所述的结构,其中,该主动区包括半导体鳍件,且该栅极结构与该半导体鳍件具有叠置关系。
11.如权利要求1所述的结构,其中,该主动区包括块体半导体衬底的部分或绝缘体上半导体晶圆的装置层的部分。
12.一种方法,包括:
在由半导体材料构成的主动区上方形成第一栅极结构;
形成邻近该第一栅极结构的第一侧壁间隙件;以及
形成设置于该第一侧壁间隙件与该主动区之间的第二侧壁间隙件的第一部分,
其中,该第一侧壁间隙件由低k介电材料组成。
13.如权利要求12所述的方法,其中,形成设置于该第一侧壁间隙件与该主动区之间的该第二侧壁间隙件的该第一部分包括:
在该主动区上及该第一栅极结构的侧壁上沉积共形层。
14.如权利要求13所述的方法,还包括:
自该第一栅极结构的该侧壁移除该共形层。
15.如权利要求13所述的方法,还包括:
蚀刻该共形层,以在该第一栅极结构的该侧壁上形成该第二侧壁间隙件的该第一部分及第二部分;
移除该第一栅极结构,以定义暴露该第二侧壁间隙件的该第二部分的开口;
在移除该第一栅极结构以后,通过蚀刻制程移除该第二侧壁间隙件的该第二部分;以及
在该开口中形成第二栅极结构。
16.如权利要求12所述的方法,其中,形成邻近该第一栅极结构的该第一侧壁间隙件包括:
在该第一栅极结构及该主动区上方沉积第一共形层;
在该第一共形层上方沉积由该低k介电材料组成的第二共形层;以及
蚀刻该第二共形层,以形成该第一侧壁间隙件。
17.如权利要求16所述的方法,其中,形成设置于该第一侧壁间隙件与该主动区之间的该第二侧壁间隙件的该第一部分包括:
在形成该第一侧壁间隙件以后,蚀刻该第一共形层,以形成该第二侧壁间隙件。
18.如权利要求12所述的方法,其中,该低k介电材料包含碳,且该第二侧壁间隙件的该第一部分由氮化硅组成。
19.如权利要求12所述的方法,其中,该低k介电材料为碳掺杂氧化硅,且该第二侧壁间隙件的该第一部分由氮化硅组成。
20.如权利要求12所述的方法,其中,该第二侧壁间隙件的该第一部分由具有第一介电常数的介电材料组成,且该低k介电材料具有小于该第一介电常数的第二介电常数。
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