JP2009032822A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can optimally drive a plurality of loads, having respectively different required currents, without increasing the switching loss and degrading the switching speed. <P>SOLUTION: The semiconductor device 100 is so formed as to divide a switching element that constitutes a switching power-supply into a plurality of power elements P1-P3, having respectively different allowable currents and as to connect the first current terminals of the power elements P1-P3, with a common power-supply terminal D and as to connect the second current terminals of the power elements P1-P3, with a common output terminal T and as to connect the respective gate terminals of the power elements P1-P3, with a common gate terminal G via switches S1-S3 comprising transistors and as to integrate an output circuit K1 comprising the power elements P1-P3 and the switches S1-S3 into a first semiconductor chip 10 and as to use the power elements P1-P3, while switching them to each other by the switches S1-S3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a switching element constituting a switching power supply is formed.

  A load driving circuit used as a switching power supply is disclosed in, for example, Japanese Patent No. 3633522 (Patent Document 1).

  FIG. 7 is an example of the load driving circuit disclosed in Patent Document 1, and is a diagram illustrating an electrical configuration of the load driving circuit 80.

  The load drive circuit 80 shown in FIG. 7 is configured as an IC, and is used in an electronic control unit (ECU) mounted on a vehicle to load a load 81 such as a solenoid coil, a relay coil, a lamp, or a light emitting diode of a solenoid valve. To drive. The load 81 is connected between the output terminal 82 and the negative terminal of the battery 83 (corresponding to a power source).

  In the load drive circuit 80 of FIG. 7, between the power supply terminal 84 and the output terminal 82, between the drain and source of the N-channel MOS transistor 85 that functions as a high-side switch for the load 81, and a diode of the illustrated polarity. 86 is connected in parallel. Further, in the load drive circuit 80 of FIG. 7, the portion 87 surrounded by a dotted line connected to the gate of the MOS transistor 85 is an ON drive circuit, and the portion 88 surrounded by a dotted line is a constant current circuit. (Corresponding to a current supply circuit).

  When the load driving circuit 80 shown in FIG. 7 is mounted on a semiconductor chip, for example, the structure of a semiconductor device disclosed in Japanese Patent No. 2839088 (Patent Document 1) can be used.

  FIG. 8 is a cross-sectional view showing a semiconductor device 90 as an example of the semiconductor device disclosed in Patent Document 2. As shown in FIG.

In the semiconductor device 90 shown in FIG. 8, a single crystal semiconductor N-epitaxial layer 92 is formed on the surface of the Si substrate 91, and a drain electrode 93 is formed on the back surface of the Si substrate 91. A single crystal semiconductor N-epitaxial layer 94 is formed in a predetermined portion on the N-epitaxial layer 92. A vertical power MOS transistor 95 is formed in the N− epitaxial layer 94. In addition, a bipolar transistor 99 for controlling the power MOS transistor 95 is formed in an SOI region composed of an N-type Si substrate 98 surrounded and insulated by an SiO ₂ film 96 and an oxide film 97.
Japanese Patent No. 3633522 Japanese Patent No. 2839088

  The load driving circuit 80 shown in FIG. 7 is designed as a circuit that drives one load 81. However, for example, in an in-vehicle switching power supply, it is necessary to drive various loads as described above, and a switching element and a switching power supply are designed according to the maximum load current. For this reason, when driving a load having a small required current, the gate-source capacitance of the switching element is too large, the impedance of the path for extracting charge from the gate capacitance is increased, the switching speed is reduced, and the switching loss is reduced. Will increase.

  Further, as a structural problem, for example, in the semiconductor device 90 shown in FIG. 8, the output circuit unit composed of the power MOS transistor 95 and the control circuit unit composed of the bipolar transistor 99 are formed on the same Si substrate 91. For this reason, if the switching element is designed in accordance with the maximum load current, the area occupied by the switching element becomes large, the gate wiring from the control circuit to the switching element becomes long, and the gate resistance increases. As the switching speed becomes slower, the switching loss increases.

  Therefore, the present invention is a semiconductor device in which switching elements constituting a switching power supply are formed, and it is not accompanied by deterioration in switching speed or increase in switching loss even when driving a plurality of loads having different required currents. An object of the present invention is to provide a semiconductor device that can be optimally adapted.

  The semiconductor device according to claim 1 is configured such that a switching element constituting a switching power supply is divided into a plurality of power elements having different allowable currents, and each of the first current terminals of the plurality of power elements has one. Connected to two common power supply terminals, the second current terminals of the plurality of power elements are respectively connected to one common output terminal, and the gate terminals of the plurality of power elements are respectively connected to the transistors. And an output circuit unit composed of the plurality of power elements and the switch is formed on one first semiconductor chip, and is connected to one common gate signal terminal through the switch. The plurality of power elements are used by being switched by the switch.

  In the semiconductor device described above, the switching elements constituting the switching power supply are divided into a plurality of power elements having different allowable currents. Therefore, when driving a plurality of loads having different required currents using the semiconductor device, power elements having optimum allowable currents corresponding to the required currents of the respective loads are formed on the same first semiconductor chip. It can be selected by a switch connected to the gate terminal of the power element. Therefore, the gate-source capacitance is more appropriate than the conventional semiconductor device in which the switching element and the switching power supply are designed according to the maximum load current, and the impedance of the path for extracting charges from the gate capacitance is increased. Can be suppressed. Thus, according to the semiconductor device, it is possible to optimally cope with driving of a plurality of loads having different required currents without deteriorating switching speed and increasing switching loss.

  The semiconductor device can be configured such that, for example, the plurality of power elements are switched during operation of the switching power supply. As a result, a plurality of loads having different required currents can be simultaneously driven in an optimum state.

  As the structure of the semiconductor device, for example, as in claim 3, the first semiconductor chip is an SOI substrate having a buried oxide film, and each of the plurality of power elements is the buried oxide film. It is preferable that the structure is formed by being insulated and separated by an insulating isolation trench reaching the thickness of the SOI layer of the SOI substrate.

  According to this, in the semiconductor device, mutual interference between the divided power elements can be suppressed.

  According to a fourth aspect of the present invention, when the insulating isolation trench has a structure in which polycrystalline silicon is embedded inside through a sidewall oxide film, the polycrystalline silicon has a ground (ground) potential. It is preferable to be fixed to.

  According to this, since the insulation isolation trench can be used as a shield, the noise resistance of each of the divided power elements can be improved in the semiconductor device.

  In the semiconductor device, for example, the control circuit unit for generating a gate signal to be input to the gate signal terminal, which is a control signal of the output circuit unit, is provided in the second semiconductor chip. Can be formed. In this case, it is preferable that the second semiconductor chip is stacked on a power element having the smallest allowable current among the plurality of power elements in the first semiconductor chip.

  According to this, the output circuit unit and the control circuit unit are formed on different first and second semiconductor chips, respectively. Therefore, the above-described semiconductor device in which these are laminated is a small-sized semiconductor device that occupies a small area as a whole, compared to a conventional semiconductor device in which the output circuit portion and the control circuit portion are laid out in a plane on the same semiconductor chip. It can be. In the semiconductor device, since the second semiconductor chip on which the control circuit portion is formed is stacked on the power element having the smallest allowable current, the plurality of divided power elements are connected to the second semiconductor chip. Thermal effects can be minimized.

  Also, in this case, the semiconductor device may be a conductor connected to the gate signal terminal in the first semiconductor chip and exposed to the surface of the first semiconductor chip. In the second semiconductor chip, a conductor connected to the output wiring of the control circuit unit, the second conductor exposed on the surface of the second semiconductor chip is formed, and the first semiconductor chip The second semiconductor chip may be arranged such that the first conductor and the second conductor face each other, and the first conductor and the second conductor are connected via a third conductor.

  According to this, the gate wiring of the plurality of power elements formed in the first semiconductor chip and the output wiring from the control circuit unit formed in the second semiconductor chip are the first conductor, the third conductor and the first conductor. The two conductors are connected at the shortest distance. Accordingly, the wiring resistance (gate resistance) can be reduced as compared with the conventional semiconductor device in which the output circuit section and the control circuit section composed of the power elements are laid out in a plane on the same semiconductor chip, and this also enables the switching speed. Therefore, the semiconductor device can be made faster and switching loss can be reduced.

  In addition, when the semiconductor device is resin-molded, as described in claim 7, a heat sink is disposed on the surface of the first semiconductor chip opposite to the first conductor, and the second semiconductor chip The surface opposite to the second conductor is preferably exposed on the surface of the mold resin. Accordingly, heat generated by the plurality of power elements formed on the first semiconductor chip can be preferentially released to the heat sink. Further, the second semiconductor chip on which the control circuit portion is formed can also dissipate heat from the surface exposed on the surface of the mold resin.

  Further, in the case where a plurality of power elements are insulated and separated in the semiconductor device, a cavity penetrating the first semiconductor chip is disposed around the plurality of power elements as described in claim 8. It is preferable that According to this, the said cavity becomes a heat insulation area | region, and the heat which a power element generate | occur | produces becomes difficult to be transmitted around. Thereby, in the first semiconductor chip of the semiconductor device, other elements such as the switch formed in a region around the power element can also be prevented from adversely affecting the characteristics of the element due to the heat generated by the power element. it can.

  As described above, the semiconductor device is a semiconductor device in which the switching elements constituting the switching power supply are formed. Even when driving a plurality of loads having different required currents, the switching speed is deteriorated and the switching loss is reduced. This is a semiconductor device that can be optimally handled without increasing.

  Therefore, as described in claim 9, the semiconductor device is used in an electronic control unit (ECU) mounted on a vehicle and has different required currents such as solenoid coils, relay coils, lamps, and light emitting diodes of solenoid valves. It is suitable as an in-vehicle semiconductor device that drives a plurality of loads.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a circuit configuration of a semiconductor device 100 as an example of the semiconductor device of the present invention.

  A semiconductor device 100 shown in FIG. 1 is a semiconductor device used as a pre-regulator for a series power supply that supplies a plurality of voltages, and a switching power supply is configured. The semiconductor device 100 has a function of reducing the voltage VB from the battery to 6 V, for example, and supplying a bias to the next series power supply (for example, 5 V output).

  The switching element in the semiconductor device 100 of FIG. 1 is made of LDMOS (Lateral Diffused Metal Oxide Semiconductor) or the like, and is divided into three power elements P1 to P3 having different allowable currents. The first current terminals (drain terminals) of the three power elements P1 to P3 are connected to one common power supply terminal D, respectively. The second current terminals (source terminals) of the three power elements P1 to P3 are respectively connected to one common output terminal T. The three power elements P1 to P3 are driven by the battery power supply voltage VB via the power supply terminal D. The gate terminals of the three power elements P1 to P3 are connected to one common gate signal terminal G via switches S1 to S3 made of transistors, respectively.

  In the semiconductor device 100 of FIG. 1, an output (driver) circuit unit K1 including three power elements P1 to P3 and switches S1 to S3 is formed in one first semiconductor chip 10. In addition, a control (predriver) circuit unit K2 for generating a gate signal to be input to the gate signal terminal G, which is a control signal of the output circuit unit K1, is formed in the second semiconductor chip 20. The control circuit unit K2 is driven by a predetermined voltage VA (for example, 3V) generated inside the IC.

  As described above, in the semiconductor device 100, the output circuit unit K1 and the control circuit unit K2 are formed in different first semiconductor chip 10 and second semiconductor chip 20, respectively. Therefore, the first semiconductor chip 10 and the second semiconductor chip 20 can be stacked as will be described later, and the output circuit section (power MOS transistor 95) and the control circuit section (bipolar transistor 99) shown in FIG. Compared with the conventional semiconductor device 90 laid out planarly on the semiconductor chip 91, the semiconductor device can be a small semiconductor device with a reduced occupation area as a whole.

  In the semiconductor device 100 of FIG. 1, three power elements P1 to P3 are used by being switched by switches S1 to S3. In the semiconductor device 100, the switching element constituting the switching power supply is divided into three power elements P1 to P3 having different allowable currents. Therefore, when driving a plurality of loads having different required currents using the semiconductor device 100, power elements having optimum allowable currents corresponding to the required currents of the respective loads are formed on the same first semiconductor chip 10. Selection can be made by switches S1 to S3 connected to the gate terminals of the power elements P1 to P3. Therefore, the gate-source capacitance is more appropriate than the conventional semiconductor device in which the switching element and the switching power supply are designed according to the maximum load current, and the impedance of the path for extracting charges from the gate capacitance is increased. Can be suppressed. As a result, according to the semiconductor device 100, it is possible to optimally cope with driving of a plurality of loads having different required currents without deteriorating the switching speed and increasing the switching loss.

  The semiconductor device 100 of FIG. 1 can be configured such that, for example, three power elements P1 to P3 are switched during operation of the switching power supply. As a result, a plurality of loads having different required currents can be simultaneously driven in an optimum state.

  FIG. 2 is a diagram illustrating an example of a structure when the circuit configuration of the semiconductor device 100 illustrated in FIG. 1 is mounted on a semiconductor chip, and is a schematic cross-sectional view of the semiconductor device 101. In the semiconductor device 101 of FIG. 2, the same reference numerals are given to the same parts as those of the semiconductor device 100 of FIG.

  In the structure of the semiconductor device 101 shown in FIG. 2, the first semiconductor chip 11 is made of an SOI substrate having the buried oxide film 2, and the three power elements P <b> 1 to P <b> 3 are the SOI layer 1 on the buried oxide film 2. Is formed. The three power elements P1 to P3 are each insulated and isolated by an insulating isolation trench 30 that includes the sidewall oxide film 3a and the buried polycrystalline silicon 3b and reaches the buried oxide film 2. Thus, by carrying out insulation isolation, the mutual interference of each power element P1-P3 can be suppressed.

  In the semiconductor device 101 of FIG. 2, an SOI substrate having a buried oxide film is also used for the second semiconductor chip 21. The second semiconductor chip 21 on which the control circuit unit K2 is formed is stacked on the power element P1 having the smallest allowable current among the three power elements P1 to P3 in the first semiconductor chip 11. As a result, in the semiconductor device 101, it is possible to minimize the thermal influence on the second semiconductor chip 21 from the three divided power elements P1 to P3.

  FIG. 3 is a schematic cross-sectional view showing an enlarged connection portion between the first semiconductor chip 11 and the second semiconductor chip 21 in the semiconductor device 101 of FIG.

  In the structure shown in FIG. 3, in the first semiconductor chip 11, a first conductor H <b> 1 that is connected to the gate signal terminal G in FIG. 1 and is exposed on the surface of the first semiconductor chip 11 is formed. In the second semiconductor chip 21, a second conductor H <b> 2 that is a conductor connected to the output wiring of the control circuit unit K <b> 2 and exposed on the surface of the second semiconductor chip 21 is formed. The first semiconductor chip 11 and the second semiconductor chip 21 are arranged so that the first conductor H1 and the second conductor H2 face each other, and the first conductor H1 and the second conductor H2 are the third conductor (solder bump) H3. Connected through.

  According to the structure shown in FIGS. 2 and 3, the gate wiring of the three power elements P <b> 1 to P <b> 3 formed on the first semiconductor chip 11 and the output from the control circuit unit K <b> 2 formed on the second semiconductor chip 21. The wiring can be connected at the shortest distance by the first conductor H1, the third conductor H3, and the second conductor H2. Therefore, compared with the conventional semiconductor device 90 in which the output circuit section (power MOS transistor 95) and the control circuit section (bipolar transistor 99) shown in FIG. ) Can be reduced, and this also makes it possible to provide a semiconductor device with a high switching speed and reduced switching loss.

  In the semiconductor devices 100 and 101 shown in FIGS. 1 to 3, the switching element is divided into the three power elements P1 to P3 having different allowable currents. It is possible to divide the element into a plurality of power elements having different allowable currents.

  FIG. 4 is a diagram illustrating a modification of the semiconductor device 101 illustrated in FIG. 2, and is a schematic cross-sectional view of the semiconductor device 102.

  In the semiconductor device 102 shown in FIG. 4, the polycrystalline silicon 3b embedded inside through the sidewall oxide film 3a in the insulating isolation trench 30 is fixed to the ground (ground) potential. As a result, the insulating isolation trench 30 can be used as a shield. For this reason, in the semiconductor device 102, the noise tolerance of each of the divided power elements P1 to P3 can be improved.

  Next, a more preferable structure relating to the thermal effect of the semiconductor devices 100 to 102 will be described.

  FIG. 5 is a schematic top view of the first semiconductor chip 12, showing a preferred example when a plurality of power elements are insulated and separated.

  In the first semiconductor chip 12 shown in FIG. 5, cavities penetrating the first semiconductor chip 12 are arranged around the plurality of power elements P1 to P3. As a result, the cavity becomes a heat insulating region, and the heat generated by the power elements P1 to P3 is hardly transmitted to the surroundings. Accordingly, in the first semiconductor chip 12, other elements such as the switches S1 to S3 in FIG. 1 formed in regions around the power elements P1 to P3 also have characteristics of those elements due to the heat generated by the power elements P1 to P3. The adverse effect on can be suppressed.

  FIGS. 6A and 6B are diagrams showing structural examples when the semiconductor device 101 of FIG. 2 is resin-molded, and are schematic cross-sectional views of the semiconductor devices 103 and 104, respectively.

  In both of the semiconductor devices 103 and 104 shown in FIGS. 6A and 6B, the first semiconductor chip 11 connected to the second semiconductor chip 21 is on the surface opposite to the first conductor H1 shown in FIG. The heat sink 40 is disposed. Thereby, heat generated by the three power elements P <b> 1 to P <b> 3 formed on the first semiconductor chip 11 can be preferentially released to the heat sink 40.

  Further, the semiconductor device 104 of FIG. 6B has a structure in which a surface of the second semiconductor chip 21 opposite to the second conductor H2 shown in FIG. Accordingly, the second semiconductor chip 21 on which the control circuit unit K2 is formed can also dissipate heat from the surface exposed on the surface of the mold resin 50.

  As described above, the semiconductor device of the present invention illustrated in FIGS. 1 to 6 is a semiconductor device in which the switching elements constituting the switching power supply are formed, and is used for driving a plurality of loads having different required currents. However, it is a semiconductor device that can be optimally handled without deteriorating the switching speed and increasing the switching loss.

  Therefore, the above semiconductor device is used in an electronic control unit (ECU) mounted on a vehicle and drives a plurality of loads having different required currents such as solenoid coils, relay coils, lamps, and light emitting diodes of solenoid valves. It is suitable as a semiconductor device.

1 is a diagram illustrating a circuit configuration of a semiconductor device 100 as an example of the semiconductor device of the present invention. FIG. 2 is a diagram illustrating an example of a structure when the circuit configuration of the semiconductor device 100 of FIG. 1 is mounted on a semiconductor chip, and is a schematic cross-sectional view of the semiconductor device 101. FIG. 3 is a schematic cross-sectional view showing an enlarged connection portion between a first semiconductor chip 11 and a second semiconductor chip 21 in the semiconductor device 101 of FIG. 2. FIG. 6 is a view showing a modification of the semiconductor device 101 shown in FIG. 2 and a schematic cross-sectional view of the semiconductor device 102. FIG. 4 is a diagram showing a preferred example in the case of insulating and separating a plurality of power elements, and is a schematic top view of a first semiconductor chip 12. (A), (b) is the figure which showed the structural example in the case of resin-molding the semiconductor device 101 of FIG. 2, and is typical sectional drawing of the semiconductor devices 103 and 104, respectively. FIG. 3 is a diagram illustrating an electrical configuration of a load driving circuit 80 as an example of a load driving circuit disclosed in Patent Document 1. 10 is a cross-sectional view showing a semiconductor device 90 as an example of the semiconductor device disclosed in Patent Document 2. FIG.

Explanation of symbols

90, 100-104 Semiconductor device 10-12 First semiconductor chip K1 Output (driver) circuit part P1-P3 Power element S1-S3 Switch 20, 21 Second semiconductor chip K2 Control (pre-driver) circuit part 1 SOI layer 2 buried Embedded oxide film 30 Insulation isolation trench 3a Side wall oxide film 3b Embedded polycrystalline silicon H1 First conductor H2 Second conductor H3 Third conductor (solder bump)
40 Heat sink 50 Mold resin

Claims (9)

The switching element constituting the switching power supply is divided into a plurality of power elements having different allowable currents,
The first current terminals of the plurality of power elements are each connected to a common power supply terminal;
A second current terminal of each of the plurality of power elements is connected to one common output terminal;
Each gate terminal of the plurality of power elements is connected to one common gate signal terminal through a switch made of a transistor,
An output circuit unit composed of the plurality of power elements and the switch is formed on one first semiconductor chip,
The semiconductor device, wherein the plurality of power elements are used by being switched by the switch.   The semiconductor device according to claim 1, wherein the plurality of power elements are switched and used during operation of the switching power supply. The first semiconductor chip is an SOI substrate having a buried oxide film;
3. The plurality of power elements are formed in an SOI layer of the SOI substrate by being insulated and isolated by insulating isolation trenches that reach the buried oxide film, respectively. Semiconductor device. The insulating isolation trench has a structure in which polycrystalline silicon is embedded inside through a sidewall oxide film,
The semiconductor device according to claim 3, wherein the polycrystalline silicon is fixed to a ground potential. A control circuit unit for generating a gate signal to be input to the gate signal terminal, which is a control signal of the output circuit unit, is formed on the second semiconductor chip,
5. The semiconductor according to claim 3, wherein the second semiconductor chip is stacked on a power element having the smallest allowable current among the plurality of power elements in the first semiconductor chip. 6. apparatus. In the first semiconductor chip, a first conductor exposed to the surface of the first semiconductor chip, which is a conductor connected to the gate signal terminal, is formed.
In the second semiconductor chip, a second conductor exposed to the surface of the second semiconductor chip, which is a conductor connected to the output wiring of the control circuit unit, is formed.
The first semiconductor chip and the second semiconductor chip are arranged so that the first conductor and the second conductor face each other;
The semiconductor device according to claim 5, wherein the first conductor and the second conductor are connected via a third conductor. A heat sink is disposed on the surface of the first semiconductor chip opposite to the first conductor,
The semiconductor device according to claim 6, wherein a surface of the second semiconductor chip opposite to the second conductor is exposed on a surface of the mold resin.   The semiconductor device according to claim 3, wherein a cavity penetrating the first semiconductor chip is arranged around the plurality of power elements.   The semiconductor device according to claim 1, wherein the semiconductor device is for in-vehicle use.

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