JP2009025412A - Active matrix type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type display device which eliminates a deficiency in writing of a signal current in low-gradation display and suppresses an increase in luminance in low gradations to thereby provide excellent display. <P>SOLUTION: The active matrix type display device has: a plurality of pixel portions (8) disposed on a substrate in a matrix form; signal lines which are provided for each column and connected to respective pixel portions in the respective columns to supply a current signal corresponding to a video signal to the pixel portions; and a plurality of control signal lines (Sga, Sgb, and Sgc) which are provided for each row and connected to respective pixel portions in the respective rows, and causes the above pixel portion to select pixel portions in row units corresponding to the video signal and to write the current signal corresponding to the video signal to the pixel portions and to hold it and which supply control signals to control light emission periods of display elements of the pixel portions, each of the pixel portions is configured in such a manner that a light emission current value (Iel) supplied to the display element (31) is the value obtained by multiplying a current signal value (Isig) corresponding to the video signal by a predetermined rate of <1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device in which a display screen is configured by arranging display pixels including display elements such as organic electroluminescence (hereinafter referred to as EL) elements in a matrix.

  2. Description of the Related Art Planar active matrix display devices are widely used as display devices for personal computers, portable information terminals, and televisions. In recent years, as such a flat-type active matrix display device, an organic EL display device using a self-luminous element such as an organic EL element has attracted attention and has been actively researched and developed. This organic EL display device does not require a backlight that obstructs the reduction in thickness and weight, is suitable for moving image reproduction because of its high-speed response, and further has a feature that it can be used even in cold regions because the luminance does not decrease at low temperatures. .

  In general, an organic EL display device includes a plurality of display pixels arranged in a plurality of rows and a plurality of columns and constituting a display screen, a plurality of scanning lines extending along each row of display pixels, and a column of display pixels. A plurality of extended signal lines, a scanning line driving circuit for driving each scanning line, a signal line driving circuit for driving each signal line, and the like are provided (for example, Patent Document 1).

Each display pixel includes an organic EL element that is a self-light-emitting element and a pixel circuit that supplies a drive current to the organic EL element. Each pixel circuit includes a pixel switch arranged in the vicinity of the intersection of the scanning line and the signal line, a driving transistor configured by a thin film transistor connected in series with an organic EL element between a pair of power supply lines, and a gate control voltage of the driving transistor Has a holding capacity. The pixel switch is turned on in response to the scanning signal supplied from the corresponding scanning line, and takes in the video signal supplied from the corresponding signal line. The gate-to-source potential of the drive transistor corresponding to this video signal is written as a gate control voltage in the storage capacitor and held for a predetermined period. Then, the driving transistor supplies a current amount corresponding to the gate control voltage written in the storage capacitor to the organic EL element to perform a light emitting operation.
US Pat. No. 6,373,454

In Patent Document 1, a current copy type circuit is adopted as a pixel circuit, and a current mirror circuit or the like is used to supply current to the pixel circuit as a video signal.
The current copy type pixel circuit is supplied with the video signal as the current signal I _sig in the writing period. In the holding period following the writing period, a driving current having a magnitude substantially equal to the current _Isig flows between the drain and the source of the driving transistor. Therefore, not only the threshold value V _{th of the} driving transistor but also the influence of mobility and dimensions on the driving current can be eliminated.

  By the way, the pixel circuit holds pixel information of one frame before. Therefore, when a large current signal, that is, a bright (high gradation) signal current is held, the signal line capacitance, the capacitance in the pixel, and the wiring resistance are included in a time called a writing time in 1H. It can be rewritten to a video signal. However, when the current becomes small and the signal becomes dark (low gradation), the above-described signal line capacitance or the like becomes a burden and insufficient writing of the signal current occurs, and the gate voltage of the driving transistor is set to a desired value. It becomes difficult to do. For this reason, an increase in luminance occurs at a low gradation.

  The present invention has been made in view of the above circumstances, and is an active matrix type capable of solving a shortage of signal current writing in low gradation display and realizing good display by suppressing an increase in luminance at low gradation. An object is to provide a display device.

  In order to achieve the above object, the present invention provides a plurality of pixel portions arranged in a matrix on a substrate, and is provided for each column, and is connected to each pixel portion of each column to output a video signal to the pixel portion. A signal line for supplying a corresponding current signal and a line provided for each row, connected to each pixel portion of each row, and a pixel unit in a row unit corresponding to the video signal is selected for the pixel portion to be used as the video signal. A plurality of control signal lines for writing and holding a corresponding current signal in the pixel portion and supplying a control signal for controlling a light emission period of a display element of the pixel portion. In the active matrix display device, the light emission current value to be supplied is a value obtained by multiplying a current signal value corresponding to the video signal by a predetermined ratio smaller than 1.

  According to the active matrix display device of the present invention, insufficient writing of signal current in low gradation display can be solved, and good display can be realized by suppressing an increase in luminance at low gradation.

Hereinafter, an active matrix organic EL display device according to a first embodiment of the present invention will be described in detail with reference to the drawings.
As shown in FIG. 1, the organic EL display device includes an organic EL panel 1 and a controller 3 that controls the organic EL panel 1.

The organic EL panel 1 is arranged in a matrix on a light-transmitting insulating substrate 2 such as a glass plate, and is connected to each row of display pixels, each of which is connected to each row of the display pixels mx that constitutes a display region 7. A first control signal line Sga (1 to m), a second control signal line Sgb (1 to m) and a third control signal line Sgc (1 to m) provided independently for each m lines, and a column of display pixels A control signal output circuit 5 for sequentially driving the n signal lines X (1 to n), the first and second control signal lines Sga, Sgb, and Sgc connected to each row of display pixels, A signal line drive circuit 6 for driving the signal lines X1 to Xn is provided.
Each display pixel PX includes an organic EL element 31 that is a self-luminous element and a pixel circuit 8 that supplies a drive current to the organic EL element 31.

FIG. 2 is a diagram illustrating an equivalent circuit of the display pixel PX.
The pixel circuit 8 is a current signal circuit that controls light emission of the organic EL element 31 in accordance with a video signal including a current signal.

This pixel circuit includes a driving transistor 11, an input transistor 12, a first switch 21, a second switch 22, a third switch 23, a fourth switch 24, a fifth switch 25, a sixth switch 26, a seventh switch 27, and a storage capacitor. Cs1, a storage capacitor Cs2, a storage capacitor Cs3, a storage capacitor Cs4, and an organic EL element 31 are provided.
Here, the drive transistor 11, the input transistor 12, and each switch are constituted by thin film transistors of the same conductivity type, for example, a P-channel type.

The sizes of the driving transistor 11 and the input transistor 12 are the same. Here, “the transistors have the same size” means that the channel length and the channel width of the transistors are the same. Further, the storage capacitors Cs1 and Cs3 have the same capacitance value C1, and the storage capacitors Cs2 and Cs4 have the capacitance values C2.
In this embodiment, the thin film transistors constituting the pixel circuit 8 are all formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as a semiconductor layer.

  The drive transistor 11, the seventh switch 27, and the organic EL element 31 are connected in series between the first voltage power line Vss and the second voltage power line Vdd. The first and second voltage power supply lines Vss and Vdd are set to potentials of 0 V and +10 V, for example. The drive transistor 11 has a first terminal, here a source, connected to the second voltage power supply line Vdd. The organic EL element 31 has one electrode, here the cathode, connected to the first voltage power supply line Vss. The source of the seventh switch 27 is connected to the second terminal of the driving transistor 11, here the drain. The seventh switch 27 has a drain connected to the anode of the organic EL element 31 and a gate connected to the third control signal line Sgc.

  The drive transistor 11 outputs a current having a magnitude corresponding to the video signal to the organic EL element 31. The seventh switch 27 is ON (conductive state) and OFF (non-conductive state) controlled by the control signal Sb from the third control signal line Sgc, and controls connection / disconnection between the drive transistor 11 and the organic EL element 31. .

  A holding capacitor Cs3, a fifth switch 25, and a holding capacitor Cs4 are connected in series from the second power supply line Vdd side between the constant potential terminal and the control terminal of the driving transistor 11, here the source and gate of the driving transistor 11. ing. The fifth switch 25 is ON (conductive state) and OFF (non-conductive state) controlled by the control signal Sa from the first control signal line Sga, and controls connection / disconnection of the storage capacitor Cs3 and the storage capacitor Cs4. To do.

  A sixth switch 26 is connected between the gate and drain of the driving transistor 11. The sixth switch 26 is ON (conductive state) and OFF (non-conductive state) controlled by the control signal Sa from the first control signal line Sga, and controls connection and disconnection between the gate and drain of the drive transistor 11. To do.

  On the other hand, the input transistor 12 and the first switch 21 are connected in series between the second voltage power supply line Vdd and the signal line X. The input transistor 12 has its first terminal, here the source, connected to the second voltage power supply line Vdd, and the first switch 21 has its source connected to the second terminal of the input transistor 12, here the drain. The first switch 21 has a drain connected to the signal line X and a gate connected to the first control signal line Sga.

  A holding capacitor Cs1, a third switch 23, and a holding capacitor Cs2 are connected in series from the second power supply line Vdd side between the constant potential terminal and the control terminal of the input transistor 12, in this case, between the source and gate of the input transistor 12. ing. The third switch 23 is ON (conductive state) and OFF (non-conductive state) controlled by the control signal Sa from the first control signal line Sga, and controls connection / disconnection of the storage capacitor Cs1 and the storage capacitor Cs2. To do.

  A second switch 22 is connected between the gate and drain of the input transistor 12. The second switch 22 is ON (conductive state) and OFF (non-conductive state) controlled by a control signal Sa from the first control signal line Sga, and controls connection and disconnection between the gate and drain of the input transistor 12. To do.

  A fourth switch 24 is connected between a terminal connected to the third switch of the storage capacitor Cs1 and a terminal connected to the fifth switch of the storage capacitor Cs4. The fourth switch 24 is ON (conductive state) and OFF (non-conductive state) controlled by the control signal Sb from the second control signal line Sgb, and controls connection / disconnection of the storage capacitor Cs1 and the storage capacitor Cs4. To do.

  On the other hand, the controller 3 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 1 and controls the control signal output circuit 5 and the signal line driving circuit 6. The controller 3 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The scanning control signal and the horizontal scanning control signal are supplied to the control signal output circuit 5 and the signal line driving circuit 6, respectively, and the digital video signal is supplied to the signal line driving circuit 6 in synchronization with the horizontal and vertical scanning timings.

  The signal line driving circuit 6 converts the video signals Data1 to Dataan sequentially obtained in each horizontal scanning period under the control of the horizontal scanning control signal into an analog format and supplies them in parallel to the plurality of signal lines X as current signals. The control signal output circuit 5 includes a shift register, an output buffer, and the like. The control signal output circuit 5 sequentially transfers an externally supplied vertical scanning start pulse to the next stage, and outputs three types of control signals to the display pixels PX in each row through the output buffer. That is, the control signals Sa, Sb, and Sc are supplied. Accordingly, the first, second, and third control signal lines Sga, Sgb, and Sgc are driven by the control signal Sa, the control signal Sb, and the control signal Sc, respectively, in one horizontal scanning period different from each other.

Hereinafter, the operation of the pixel circuit 8 based on the output signals of the control signal output circuit 5 and the signal line drive circuit 6 will be described.
FIG. 3 is a time chart of the control signals Sa, Sb, and Sc. The control signals Sa, Sb, and Sc change corresponding to each period of the pixel circuit 8, that is, the writing period, the holding period, and the light emitting period.

FIG. 4 is a diagram for explaining the operation of the pixel circuit 8 in the writing period. In the writing period, the first switch 21, the second switch 22, the third switch 23, the fifth switch 25, and the sixth switch 26 are turned on by controlling the control signal Sa to the low level. On the other hand, when the control signal Sb is controlled to a high level, the fourth switch 24 is turned off, and when the control signal S3 is controlled to a high level, the seventh switch 27 is turned off.
As a result, the signal current Isig flows through the input transistor 12 in the direction of the arrow in the figure, and the gate voltage of the input transistor 12 corresponding to the signal current Isig is held in the holding capacitor Cs2. At the same time, the storage capacitor Cs4 is charged until the gate of the driving transistor 11 reaches the threshold voltage, and this threshold voltage is stored in the storage capacitor Cs4.

Assuming that the gate potential of the input transistor 12 at this time is Vg, the potential Va of the storage capacitor Cs1 is expressed by Expression (1).
Va = Vdd− (Vdd−Vg) × C2 / (C1 + C2)
= (C1 × Vdd + C2 × Vg) / (C1 + C2) (1)
Further, when the threshold voltage of the drive transistor 11 is Vth, the potential Vb on the side of the storage capacitor Cs4 of the storage capacitor Cs3 is expressed by Expression (2).
Vb = Vdd−Vth × C2 / (C1 + C2) (2)
Further, the potential Vc on the gate terminal side of the driving transistor of the storage capacitor Cs4 is expressed by Expression (3).
Vc = Vdd−Vth (3)
Therefore, the potential difference ΔVbc across the storage capacitor Cs4 is expressed by Expression (4).
ΔVbc = Vb−Vc = Vth × C1 / (C1 + C2) (4)
Next, FIG. 5 is a diagram illustrating the operation of the pixel circuit 8 in the holding period.
By maintaining the control signal Sc at the high level, the seventh switch 27 remains off. When the control signal Sa changes to a high level, the first switch 21, the second switch 22, the third switch 23, the fifth switch 25, and the sixth switch 26 are turned off. At the same time, the fourth switch 24 is turned on when the control signal Sb changes to a low level.

  As a result, the storage capacitor Cs1 and the storage capacitor Cs4 are connected, and the potential of the terminal on the storage capacitor Cs1 side of the storage capacitor Cs4 is the same as the potential of the storage capacitor Cs1. Since the voltage between the terminals of the holding capacitor Cs4 is held, the gate potential of the driving transistor 11 is lower than the potential of the holding capacitor Cs1 by the voltage difference held between the terminals of the holding capacitor Cs4.

Therefore, the potential Vd of the gate of the driving transistor 11 is expressed by the formula (5).
Vd = Va−ΔVbc
= (C1 * Vdd + C2 * Vg-C1 * Vth) / (C1 + C2)
... Formula (5)
Next, FIG. 6 is a diagram illustrating the operation of the pixel circuit 8 during the light emission operation period.
By maintaining the control signal Sb at the low level, the fourth switch 24 continues to be in the ON state. By maintaining the control signal Sa at the high level, the first switch 21, the second switch 22, the third switch 23, the fifth switch 25, and the sixth switch 26 continue to be in the off state. The seventh switch 27 is turned on when the control signal Sc changes to the low level.

    As a result, a current flows in the drive transistor 11 in the direction of the arrow in the figure due to the potential held in the holding capacitor Cs4, and the organic EL element 31 emits light by this current.

Here, the drain current of the driving transistor 11, that is, the light emission current IEL is expressed by the equation (6) from the current equation of the transistor.
IEL = β × (Vdd−Vd−Vth) ² Formula (6)
By substituting equation (5) into the gate potential Vd of equation (6), equation (7) is obtained.

IEL = β × {(Vdd−Vg−Vth) × C2 / (C1 + C2)} ²
... Formula (7)
Further, since the drive transistor 11 and the input transistor 12 have the same size, the signal current Isig is expressed by Expression (8).
Isig = β × (Vdd−Vg−Vth) ² Formula (8)
Therefore, the light emission current IEL is expressed by the equation (9).
IEL = Isig × {C2 / (C1 + C2)} ²
= Isig / N (9)
Here, N is a real number of 1 or more.

This equation indicates that the light emission current is 1 / N times the signal current regardless of the threshold value and mobility of the transistor.
That is, N times the signal current is passed to cause the organic EL element to emit light with a desired light emission current.

  Conventionally, in the case of a small signal current such as low gradation display, writing is insufficient due to the influence of the load capacity of the signal line, and a current larger than a desired light emission current flows, resulting in an increase in luminance. However, in the embodiment of the present invention, even in a low gradation display, a signal current that is N times larger than a conventional signal current is allowed to flow in order to pass a desired light emission current. Brightness increase can be reduced.

  In addition, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In the above-described embodiment, the case where all the thin film transistors constituting the pixel circuit are formed of the same conductivity type, here, the P channel type is described. However, the present invention is not limited to this, and all the thin film transistors are formed of N channel type thin film transistors. Is also possible. In addition, the pixel circuit can be formed by mixing thin film transistors of different conductivity types.

  Furthermore, the semiconductor layer of the thin film transistor is not limited to polysilicon, but may be composed of amorphous silicon. The self-luminous elements constituting the display pixels are not limited to organic EL elements, and various display elements capable of self-luminance are applicable.

1 is a plan view schematically showing a display device according to one embodiment of the present invention. The figure which shows the equivalent circuit of the display pixel PX. The time chart of a control signal. FIG. 14 illustrates operation of a pixel circuit in a writing period. FIG. 10 illustrates operation of a pixel circuit in a holding period. 4A and 4B illustrate operation of a pixel circuit during a light emission operation period.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 3 ... Controller, 5 ... Control signal output circuit, 6 ... Signal line drive circuit, 31 ... Organic EL element, 8 ... Pixel circuit, 11 ... Drive transistor, 12 ... Input transistor, 21 ... 1st switch, 22 ... 2nd switch , 23 ... 3rd switch, 24 ... 4th switch, 25 ... 5th switch, 26 ... 6th switch, 27 ... 7th switch, Cs1 ... holding capacity, Cs2 ... holding capacity, Cs3 ... holding capacity, Cs4 ... holding capacity , PX ... display pixel, Vdd ... second voltage power line, Vss ... first voltage power line, Sga ... first control signal line, Sgb ... second control signal line, Sgc ... third control signal line, X ... signal line Sa ... 1st control signal, S2 ... 2nd control signal, S3 ... 3rd control signal.

Claims (5)

A plurality of pixel portions arranged in a matrix on the substrate;
A signal line provided for each column and connected to each pixel portion of each column to supply a current signal corresponding to the video signal to the pixel portion;
Provided for each row, connected to each pixel portion of each row, and selects a pixel unit in a row unit corresponding to the video signal in the pixel unit, and writes a current signal corresponding to the video signal to the pixel unit; A plurality of control signal lines for holding and supplying a control signal for controlling the light emission period of the display element of the pixel portion;
Each pixel unit is configured such that a light emission current value supplied to the display element is a value obtained by multiplying a current signal value corresponding to the video signal by a predetermined ratio smaller than 1. Matrix type display device. Each display pixel is
An input transistor having a first terminal connected to a first power supply; a first switch connected between the second terminal of the input transistor and the signal line; a control terminal of the input transistor; A second switch connected between two terminals, a first capacitor connected in series from the first terminal side between the first terminal and the control terminal of the input transistor, a third capacitor A switch and a second capacitor;
A driving transistor having a first terminal connected to a first power source, and a second terminal of the display element having a first terminal connected to a second power source and the first terminal of the driving transistor. A seventh switch connected to the drive transistor, a sixth switch connected between the control terminal and the second terminal of the drive transistor, and a first switch between the first terminal and the control terminal of the drive transistor. A third capacitor, a fifth switch, and a fourth capacitor connected in series from one terminal side;
A fourth switch connected between the terminal on the third switch side of the first capacitor and the terminal on the fifth switch side of the fourth capacitor;
The input transistor and the drive transistor have the same size, and the first capacitor and the third capacitor, and the second capacitor and the fourth capacitor have the same capacitance value. 2. An active matrix display device according to 1.   3. The active matrix display device according to claim 2, wherein a capacitance value of the first capacitor is larger than a capacitance value of the second capacitor. The plurality of control lines are provided in three rows,
The first control line controls conduction and non-conduction of the first switch, the second switch, the third switch, the fifth switch, and the sixth switch,
The second control line controls conduction and non-conduction of the fourth switch,
4. The active matrix display device according to claim 3, wherein the third control line controls conduction and non-conduction of the seventh switch. A control signal output unit for supplying a control signal for conducting and non-conducting each switch connected to the plurality of control lines;
The control signal output unit is
When writing a current signal corresponding to the video signal to each pixel unit, a control signal for turning on each switch to the first control line, and a control signal for turning off each switch to the second and third control lines Supply
When each pixel unit holds a current signal corresponding to the video signal, a control signal that makes each switch non-conductive to the first and third control lines, and a control signal that makes each switch conductive to the second control line Supply
When the display element is caused to emit light, a control signal for turning off each switch is supplied to the first control line, and a control signal for turning on each switch is supplied to the second and third control lines. Item 5. The active matrix display device according to Item 4.

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