JP2009016571A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of remarkably reducing on-resistance. <P>SOLUTION: This semiconductor device 11 is provided with: an n-type epitaxial layer 2 having trenches 3; embedded electrodes 5 embedded in the trenches 3; and upper surface electrode layers 7 formed on the upper surface of the n-type epitaxial layer 2. The semiconductor device is composed such that current passages 9 are blocked by closing respective regions between the adjacent trenches 3 of the n-type epitaxial layer 2 by depletion layers 10 formed around the trenches 3, and the current passages 9 are opened by extinguishing at least a part of the depletion layers 10 formed around the trenches 3. An upper surface of a predetermined region within each region between the adjacent trenches 3 of the n-type epitaxial layer 2 comes into Schottky contact with the upper surface electrode layer 7. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a switching function.

  Conventionally, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is known as a semiconductor device having a switching function (see, for example, Patent Document 1). This Patent Document 1 discloses a trench gate type MOSFET (semiconductor device) in which a gate electrode is embedded in a trench formed in a semiconductor layer.

FIG. 19 is a cross-sectional view showing the structure of a conventional MOSFET (semiconductor device) disclosed in Patent Document 1. Referring to FIG. 19, in a conventional MOSFET (semiconductor device), an epitaxial layer (semiconductor layer) 102 is formed on the upper surface of an n ⁺ type semiconductor substrate 101. In this epitaxial layer 102, an n ⁻ -type impurity region (drain region) 102a, a p-type impurity region 102b, and an n ⁺ -type impurity region (source region) 102c are formed in this order from the semiconductor substrate 101 side.

In addition, trench 103 is formed in epitaxial layer 102 so as to penetrate n ⁺ -type impurity region 102 c and p-type impurity region 102 b and reach a depth in the middle of n ⁻ -type impurity region 102 a. A gate electrode 105 is embedded in the trench 103 via a gate insulating film 104. An interlayer insulating film 106 that closes the opening end of the trench 103 is formed on the upper surface of the epitaxial layer 102.

  A source electrode 107 is formed on the upper surface of the epitaxial layer 102 so as to cover the interlayer insulating film 106. A drain electrode 108 is formed on the back surface of the semiconductor substrate 101.

  In the conventional MOSFET configured as described above, ON / OFF control is performed by changing the voltage applied to the gate electrode 105.

Specifically, when a predetermined positive potential is applied to the gate electrode 105, minority carriers (electrons) in the p-type impurity region 102b are attracted to the trench 103 side, whereby an n ⁻ -type impurity region (drain region) 102a. An inversion layer 109 is formed to connect the n ⁺ type impurity region (source region) 102c. As a result, a current can flow between the source electrode 107 and the drain electrode 108 via the inversion layer 109. As a result, the MOSFET is turned on.

Thus, in the conventional MOSFET, the inversion layer 109 formed so as to connect the n ⁻ type impurity region (drain region) 102a and the n ⁺ type impurity region (source region) 102c functions as a channel.

  Further, when the application of a predetermined positive potential to the gate electrode 105 is canceled from the above state, the inversion layer (channel) 109 disappears, so that the current flowing between the source electrode 107 and the drain electrode 108 can be cut off. . As a result, the MOSFET is turned off.

JP 2001-7149 A

  However, in the conventional structure shown in FIG. 19, since the inversion layer (channel) 109 formed at the time of ON is very thin, it is difficult to reduce the resistance to the current flowing through the inversion layer (channel) 109. There is. As a result, there is a problem that it is difficult to improve the on-resistance.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device based on a new operating principle capable of greatly reducing the on-resistance. .

  In order to achieve the above object, a semiconductor device according to an aspect of the present invention includes a plurality of trenches arranged at predetermined intervals from each other and having a plurality of trenches, each open end being located on the upper surface side. A semiconductor layer of a type, a plurality of embedded electrodes embedded in each of the plurality of trenches, and an electrode layer formed on the upper surface of the semiconductor layer. Each region between adjacent trenches in the semiconductor layer serves as a current path, and the current path is blocked by blocking each region between adjacent trenches in the semiconductor layer with a depletion layer formed around the trench. On the other hand, the current path is configured to be opened when at least part of the depletion layer formed around the trench disappears, and the upper surface of a predetermined region of each region between adjacent trenches of the semiconductor layer is The Schottky contact is made to the electrode layer.

  In the semiconductor device according to this aspect, as described above, each region between adjacent trenches of the semiconductor layer is blocked by a depletion layer formed around the trench, thereby causing a current path (between adjacent trenches of the semiconductor layer). The current path (each region between adjacent trenches in the semiconductor layer) is opened when at least part of the depletion layer formed around the trench disappears. For example, if a buried electrode is formed on the inner surface of a trench through an insulating film, the formation state of a depletion layer formed around the trench changes according to the voltage applied to the buried electrode, so that the application to the buried electrode By controlling the voltage, switching from the on state (the current path is open) to the off state (the current path is blocked) is performed. It is possible, can also switches the reverse. That is, the semiconductor device can be used as a switch device (switching transistor). In the above-described configuration, since the current can flow through all the portions where the depletion layer of the current path (each region between adjacent trenches of the semiconductor layer) disappears at the time of ON, a very thin inversion layer As compared with a conventional MOSFET (semiconductor device) that functions as a channel (current path), the resistance to current can be greatly reduced. As a result, the on-resistance can be greatly reduced as compared with a conventional MOSFET (semiconductor device) in which a very thin inversion layer functions as a channel (current path).

  Further, in the semiconductor device according to one aspect, as described above, the upper surface of the predetermined region of each region between adjacent trenches of the semiconductor layer is configured to be in Schottky contact with the electrode layer. A contact portion between a predetermined region of each region between adjacent trenches of the semiconductor layer and the electrode layer can function as a Schottky barrier diode, so that the Schottky barrier diode and the switching transistor can be integrated. It becomes. This eliminates the need to separately provide a wiring member forming region for connecting the Schottky barrier diode and the switching transistor, thereby reducing the area of the circuit including the Schottky barrier diode and the switching transistor connected to each other. be able to.

  In the above-described configuration, each region between adjacent trenches in the semiconductor layer can be blocked with a depletion layer formed around the trench. It becomes possible to block the junction with the electrode layer (the part in Schottky contact) with the depletion layer. Thereby, generation | occurrence | production of the leakage current in a Schottky barrier diode can be suppressed.

  In the semiconductor device according to the above aspect, preferably, the electrode layer is adjacent to the first portion in Schottky contact with the upper surface of a predetermined region of each region between adjacent trenches of the semiconductor layer, and the semiconductor layer. And a second portion in ohmic contact with the upper surface of the region other than the predetermined region among the regions between the trenches. With this configuration, by electrically separating the first and second portions of the electrode layer from each other, one of the source / drain electrodes of the switching transistor and the anode of the Schottky barrier diode are electrically separated. Circuit can be obtained. On the other hand, if the first part and the second part of the electrode layer are electrically connected to each other, a circuit in which one of the source / drain electrodes of the switching transistor and the anode of the Schottky barrier diode are electrically connected can be obtained. Can do.

  In the configuration in which the electrode layer includes the first portion and the second portion, the first portion of the electrode layer and the second portion of the electrode layer may be electrically separated from each other. With this configuration, it is possible to easily obtain a circuit in which one of the source / drain electrodes of the switching transistor and the anode of the Schottky barrier diode are electrically separated.

  In the configuration in which the electrode layer includes the first portion and the second portion, the first portion of the electrode layer and the second portion of the electrode layer may be electrically connected to each other. With this configuration, a circuit in which one of the source / drain electrodes of the switching transistor and the anode of the Schottky barrier diode are electrically connected can be easily obtained.

  In the semiconductor device according to the above aspect, at least one predetermined region of the semiconductor layer that is in Schottky contact with the electrode layer is provided in each region between adjacent trenches of the semiconductor layer. If comprised in this way, a Schottky barrier diode and a switching transistor can be integrated easily.

  In this case, in each region between adjacent trenches of the semiconductor layer, a predetermined region that makes a Schottky contact with the electrode layer and a region other than the predetermined region that makes a Schottky contact with the electrode layer are alternately provided. It is preferable that

  In the semiconductor device according to the above aspect, the current path is blocked by blocking each region between adjacent trenches in all the depletion layers formed around each of the plurality of trenches. The current path may be opened when all the depletion layers formed around each of them disappear.

  In the semiconductor device according to the above aspect, the plurality of embedded electrodes are divided into two types, a first embedded electrode and a second embedded electrode to which a voltage is separately applied, and all of the plurality of trenches A current path is blocked by blocking each region between adjacent trenches with a depletion layer formed at the periphery of the trench, while the first buried electrode of the plurality of trenches is formed around the trench embedded therein. Alternatively, the current path may be opened when the depletion layer disappears.

  In this case, the second embedded electrode may be in Schottky contact with the semiconductor layer inside the trench.

  In the semiconductor device according to the above aspect, the semiconductor device further includes a reverse conductivity type diffusion layer formed in each region between adjacent trenches of the semiconductor layer and disposed at a predetermined interval with respect to the trench, the trench and the diffusion layer Each of the regions between adjacent trenches is blocked by a depletion layer formed around each of the trenches, while the current path is blocked, while the depletion layer formed around the trenches disappears to open the current pathway. It may be configured as follows.

  In the semiconductor device according to the above aspect, when the current flowing through each region between adjacent trenches of the semiconductor layer is cut off, the depletion layers formed around each of the adjacent trenches are connected to each other. You may be comprised so that it may be in a state. If comprised in this way, each area | region between the adjacent trenches of a semiconductor layer can be reliably block | closed with a depletion layer.

  In the semiconductor device according to the above aspect, the distance between adjacent trenches may be set such that a part of depletion layers formed around each adjacent trench overlap each other. If comprised in this way, the depletion layer formed in the circumference | surroundings of each adjacent trench can be connected mutually easily.

  The semiconductor device according to one aspect further includes an interlayer insulating film for performing insulation between the buried electrode and the electrode layer, and the buried electrode is buried to a depth in the middle of the trench, and the interlayer insulating film May be buried in the remaining portion of the trench where the buried electrode is not buried so that the upper surface of the interlayer insulating film is flush with the upper surface of the semiconductor layer. With this configuration, even if the distance between adjacent trenches is reduced, the upper surface side portion of the semiconductor layer (the upper end portion of the region between adjacent trenches of the semiconductor layer) is covered with the interlayer insulating film. There is no. Thereby, since the distance between adjacent trenches can be reduced, depletion layers formed around each of adjacent trenches can be easily connected to each other.

  As described above, according to the present invention, it is possible to easily obtain a semiconductor device based on a new operation principle capable of greatly reducing the on-resistance.

(First embodiment)
FIG. 1 is a cross-sectional perspective view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view for explaining the connection position of the buried electrode of the semiconductor device according to the first embodiment shown in FIG. FIG. 3 is an equivalent circuit of the semiconductor device according to the first embodiment shown in FIG. First, the structure of the semiconductor device according to the first embodiment will be described with reference to FIGS.

  As shown in FIG. 1, the semiconductor device 11 according to the first embodiment has a structure in which a region functioning as a normally-off type switching transistor and a region functioning as a Schottky barrier diode are integrally provided. .

As a specific structure, in the semiconductor device 11 according to the first embodiment, the n-type epitaxial layer 2 made of n-type silicon having a thickness of about 1 μm to about 10 μm is formed on the upper surface of the n ⁺ -type silicon substrate 1. ing. In the n ⁺ -type silicon substrate 1, n-type impurities are introduced at a high concentration in order to obtain a good ohmic contact with the back electrode layer 8 described later. Further, n-type impurities are introduced into the n-type epitaxial layer 2 at a lower concentration (about 5 × 10 ¹⁵ cm ⁻³ to about 1 × 10 ¹⁸ cm ⁻³ ) than the n ⁺ -type silicon substrate 1. The n ⁺ -type silicon substrate 1 and the n-type epitaxial layer 2 are examples of the “one-conductivity-type semiconductor layer” in the present invention.

  The n-type epitaxial layer 2 has a plurality of trenches 3 dug in the thickness direction. The plurality of trenches 3 are formed by etching the n-type epitaxial layer 2 from the upper surface (main surface) side. That is, the open ends of the plurality of trenches 3 are located on the upper surface side of the n-type epitaxial layer 2.

The plurality of trenches 3 are formed in an elongated shape so that each of the trenches 3 extends along a predetermined direction (A direction) parallel to the upper surface of the n-type epitaxial layer 2. In addition, the plurality of trenches 3 are parallel to the upper surface of the n-type epitaxial layer 2 and about 0.05 μm to about 0.00 mm from each other in the direction (B direction) orthogonal to the direction (A direction) in which the trench 3 extends. They are arranged with an interval of 3 μm. Further, the depth of each of the plurality of trenches 3 is set to about 0.5 μm to about 12 μm. The groove depth of the trench 3 of the first embodiment is set to be smaller than the thickness (about 1 μm to about 10 μm) of the n-type epitaxial layer 2. Although not shown, the trench 3 may penetrate the n-type epitaxial layer 2 and reach the n ⁺ -type silicon substrate 1. The width in the B direction of each of the plurality of trenches 3 is set to about 0.1 μm to about 1 μm.

  A silicon oxide film (insulating film) 4 obtained by thermally oxidizing silicon constituting the n-type epitaxial layer 2 is formed on the inner surface of each of the plurality of trenches 3 with a thickness of about 10 nm to about 100 nm. Has been.

  A buried electrode 5 made of p-type polysilicon is formed on the inner surface of each of the plurality of trenches 3 with a silicon oxide film 4 interposed therebetween. Each of the plurality of embedded electrodes 5 is embedded up to the middle depth of the corresponding trench 3. In addition to the p-type polysilicon, a metal or the like can be used as a constituent material of the embedded electrode 5.

  In the first embodiment in which the plurality of embedded electrodes 5 are provided as described above, if a voltage applied to the plurality of embedded electrodes 5 is controlled, a depletion layer is formed or formed around each of the plurality of trenches 3. It is possible to eliminate the depletion layer. In the first embodiment, the distance between the adjacent trenches 3 is a part of the depletion layer formed around each of the adjacent trenches 3 when the depletion layer is formed around each of the plurality of trenches 3. Are set to overlap each other. That is, when a depletion layer is formed around each of the plurality of trenches 3, the depletion layers formed around each of the adjacent trenches 3 are connected to each other. For this reason, in the first embodiment, if a depletion layer is formed around each of the plurality of trenches 3, each region between adjacent trenches 3 of the n-type epitaxial layer 2 is closed by the depletion layer. be able to.

  An interlayer insulating film 6 made of a silicon oxide film is embedded in the remaining portion (portion above the embedded electrode 5) where each embedded electrode 5 of the plurality of trenches 3 is not embedded. Each of the plurality of interlayer insulating films 6 is provided to insulate between the corresponding embedded electrode 5 and an upper surface electrode layer 7 described later. The thickness of each of the plurality of interlayer insulating films 6 is set to be the same as the depth of the remaining portion (the portion above the embedded electrode 5) where the embedded electrode 5 of the corresponding trench 3 is not embedded. ing. Therefore, the upper surface of each of the plurality of interlayer insulating films 6 is flush with the upper surface of the n-type epitaxial layer 2 (the upper surface of the upper end portion of each region between the adjacent trenches 3).

  A plurality of high-concentration regions 2a arranged at predetermined intervals along the A direction are formed on the upper surface side of the n-type epitaxial layer 2 (upper end portions of the regions between adjacent trenches 3). Is formed. The concentration of the high concentration region 2 a of the n-type epitaxial layer 2 is higher than the concentration of other portions of the n-type epitaxial layer 2. That is, the high-concentration regions 2a and the low-concentration regions are alternately provided one by one along the A direction in the upper surface portion of the n-type epitaxial layer 2 (the upper end portion of each region between the adjacent trenches 3). Will be. Further, the thickness of the high concentration region 2 a of the n-type epitaxial layer 2 is set to be smaller than the thickness of the interlayer insulating film 6. For this reason, the lower end portion of the high concentration region 2 a of the n-type epitaxial layer 2 is located above the upper end portion of the buried electrode 5.

  On the upper surface of n-type epitaxial layer 2, upper electrode layer 7 made of a metal layer (for example, an Al layer) and including a predetermined number of portions 7a and 7b is formed. The portions 7a and 7b of the upper surface electrode layer 7 are electrically separated from each other. Furthermore, the portions 7a and 7b of the top electrode layer 7 are formed in an elongated shape so as to extend along the B direction, and are alternately arranged one by one in the A direction. The top electrode layer 7 is an example of the “electrode layer” in the present invention. The portions 7a and 7b are examples of the “second portion” and the “first portion” in the present invention, respectively.

  The portion 7a of the upper surface electrode layer 7 is in ohmic contact with the high concentration region 2a of the n-type epitaxial layer 2 so as to function as a source electrode of the switching transistor. On the other hand, the portion 7 b of the top electrode layer 7 is in Schottky contact with the low concentration region of the n-type epitaxial layer 2. That is, the junction between the portion 7b of the upper electrode layer 7 and the low concentration region of the n-type epitaxial layer 2 functions as a Schottky barrier diode. In this case, the portion 7b of the upper electrode layer 7 becomes the anode of the Schottky barrier diode, and the low concentration region of the n-type epitaxial layer 2 becomes the cathode of the Schottky barrier diode.

Further, on the back surface of the n ⁺ -type silicon substrate 1, a back surface electrode layer 8 having a multilayer structure in which a plurality of metal layers are laminated is formed. The back electrode layer 8 is in ohmic contact with the n ⁺ type silicon substrate 1. The back electrode layer 8 functions as a drain electrode of the switching transistor.

  In the configuration described above, the current flowing between the top electrode layer 7 and the back electrode layer 8 (current flowing in the thickness direction of the n-type epitaxial layer 2) passes through each region between the adjacent trenches 3 of the n-type epitaxial layer 2. Will pass. That is, in the above-described configuration, each region between the adjacent trenches 3 of the n-type epitaxial layer 2 functions as the current path 9.

  Incidentally, in the first embodiment, the plurality of embedded electrodes 5 are divided into two types of embedded electrodes 5a and 5b to which voltages are applied separately from each other. Specifically, as shown in FIG. 2, the embedded electrode 5a is configured to be applied with a voltage corresponding to a predetermined control signal (signal for switching on / off). On the other hand, the embedded electrode 5b is electrically connected to a portion (source electrode) 7a of the upper surface electrode layer 7. That is, the embedded electrode 5b is configured to have the same potential as the portion (source electrode) 7a of the upper surface electrode layer 7. The embedded electrodes 5a and 5b are examples of the “first embedded electrode” and the “second embedded electrode” in the present invention, respectively.

  In the first embodiment, the embedded electrodes 5a and 5b are alternately arranged one by one in the B direction. That is, one embedded electrode 5b (5a) is arranged between the two embedded electrodes 5a (5b).

  The semiconductor device 11 of the first embodiment described above can be represented by an equivalent circuit as shown in FIG. That is, the semiconductor device 11 of the first embodiment is a circuit in which the source of the switching transistor and the cathode of the Schottky barrier diode are electrically connected to each other, as shown in FIG. In FIG. 3, the switching transistor portion of the semiconductor device 11 is represented by a MOSFET circuit symbol for convenience.

  4 and 5 are cross-sectional views for explaining the operation of the semiconductor device according to the first embodiment of the present invention. FIG. 4 illustrates the case where the semiconductor device (switching transistor) is in an off state, and FIG. 5 illustrates the case where the semiconductor device (switching transistor) is in an on state. Next, the operation of the semiconductor device according to the first embodiment will be described with reference to FIGS.

  First, as shown in FIGS. 4 and 5, assuming that a negative potential and a positive potential are applied to each of the upper electrode layer 7 portion (source electrode) 7a and the back electrode layer (drain electrode) 8, the embedded electrode Since 5b is electrically connected to the portion (source electrode) 7a of the upper surface electrode layer 7, a negative potential is applied to the embedded electrode 5b. Therefore, the majority carriers are reduced around the trench 3 in which the embedded electrode 5b is embedded (hereinafter referred to as the trench 3b). That is, the depletion layer 10 (10b) is formed around the trench 3b regardless of the on state and the off state.

  As shown in FIG. 4, when the semiconductor device (switching transistor) 11 is in an off state, the majority carriers existing around the trench 3 in which the embedded electrode 5a is embedded (hereinafter referred to as the trench 3a) are reduced. Thus, the voltage applied to the embedded electrode 5a is controlled. Thus, a depletion layer 10 (10a) similar to the depletion layer 10b formed around the trench 3b is formed around the trench 3a.

  At this time, in the region between the trenches 3a and 3b, the depletion layers 10a and 10b formed around the trenches 3a and 3b partially overlap each other. That is, in the region between trench 3a and trench 3b, depletion layers 10a and 10b are connected to each other. As a result, the current path 9 is blocked by the depletion layers 10a and 10b, so that the current flowing through the current path 9 can be cut off. Therefore, the semiconductor device (switching transistor) 11 is turned off.

  Next, as shown in FIG. 5, when the semiconductor device (switching transistor) 11 is switched from the off state to the on state, a predetermined positive potential is applied to the embedded electrode 5 a so as to surround the trench 3 a. The formed depletion layer 10a (see FIG. 4) is extinguished. That is, the depletion layer 10a that has blocked the portion of the current path 9 on the buried electrode 5a side is eliminated. Thus, current can flow in the direction of the arrow in FIG. 5 through the portion of the current path 9 on the embedded electrode 5a side, so that the semiconductor device (switching transistor) 11 can be turned on.

  When the semiconductor device (switching transistor) 11 is switched from the on state to the off state, the application of a predetermined positive potential to the embedded electrode 5a is canceled. As a result, the state shown in FIG. 4 is restored, and the semiconductor device (switching transistor) 11 can be turned off.

  In the first embodiment, as described above, each region between the adjacent trenches 3 of the n-type epitaxial layer 2 is blocked by the depletion layer 10 formed around the trench 3, so that the n-type epitaxial layer 2 While the current flowing through each region between adjacent trenches 3 is cut off, at least a part of the depletion layer 10 formed around the trench 3 (depletion layer 10a formed around the trench 3a) disappears. Thus, the current is allowed to flow through the regions between the adjacent trenches 3 of the n-type epitaxial layer 2, whereby the formation state of the depletion layer 10 formed around the trench 3 is applied to the buried electrode 5. Since it changes according to the voltage, the on-state (between adjacent trenches 3 of the n-type epitaxial layer 2 is controlled by controlling the voltage applied to the buried electrode 5. It is possible to switch from the state in which current flows through the region) to the off state (state in which the current flowing through each region between adjacent trenches 3 of the n-type epitaxial layer 2 is blocked) and vice versa. Can also be switched. That is, the semiconductor device 11 can be used as a switching device (switching transistor). In the above-described configuration, since all the portions where the depletion layer 10 in each region between the adjacent trenches 3 of the n-type epitaxial layer 2 disappears can function as the current path 9 when turned on, the structure is very thin. Compared to a conventional MOSFET (semiconductor device) in which the inversion layer functions as a channel (current path), the resistance to current can be greatly reduced. As a result, the on-resistance can be greatly reduced as compared with a conventional MOSFET (semiconductor device) in which a very thin inversion layer functions as a channel (current path).

  Further, in the first embodiment, as described above, the upper surface of a predetermined region in each region between adjacent trenches 3 of the n-type epitaxial layer 2 is configured to be in Schottky contact with the upper surface electrode layer 7. By doing so, a contact portion between a predetermined region of each region between adjacent trenches 3 of the n-type epitaxial layer 2 and the upper surface electrode layer 7 can function as a Schottky barrier diode. It becomes possible to integrate the switching transistor. This eliminates the need to separately provide a wiring member forming region for connecting the Schottky barrier diode and the switching transistor, thereby reducing the area of the circuit including the Schottky barrier diode and the switching transistor connected to each other. be able to.

  Further, in the above-described configuration, each region between the adjacent trenches 3 of the n-type epitaxial layer 2 can be blocked by the depletion layer 10 formed around the trench 3, so that the adjacent trenches 3 of the n-type epitaxial layer 2 can be closed. A depletion layer 10 can block a junction (a Schottky contact portion) between a predetermined region of each region in between and the upper surface electrode layer 7. Thereby, generation | occurrence | production of the leakage current in a Schottky barrier diode can be suppressed.

  In the first embodiment, as described above, the portions 7a and 7b of the upper surface electrode layer 7 are electrically separated from each other, whereby one of the source / drain electrodes of the switching transistor, the anode of the Schottky barrier diode, Can be easily obtained. In this case, the semiconductor device 11 can be used as a part of components constituting the DC / DC converter (see FIGS. 6 and 7). The DC / DC converter shown in FIG. 6 is a step-down type, and the DC / DC converter shown in FIG. 7 is a step-up / step-down type. Moreover, the code | symbol 31 of FIG. 6 and FIG. 7 is a coil.

  In the first embodiment, as described above, the depletion layer 10 formed around each of the adjacent trenches 3 is connected to each other at the time of off, so that A current path (each region between adjacent trenches 3 of the n-type epitaxial layer 2) 9 can be closed with a depletion layer 10.

  In the first embodiment, as described above, the distance between the adjacent trenches 3 is set so that the depletion layers 10 formed around each of the adjacent trenches 3 overlap each other. The depletion layers 10 formed around the adjacent trenches 3 can be easily connected to each other.

  In the first embodiment, as described above, the interlayer insulating film 6 is buried in the trench 3 so that the upper surface of the interlayer insulating film 6 is flush with the upper surface of the n-type epitaxial layer 2. Even if the distance between the trenches 3 to be reduced is reduced, the upper surface side portion of the n-type epitaxial layer 2 (the upper end portion of the region between the adjacent trenches 3) is not covered with the interlayer insulating film 6. Thereby, since the distance between the adjacent trenches 3 can be reduced, the depletion layers 10 formed around each of the adjacent trenches 3 can be easily connected to each other.

(Second Embodiment)
FIG. 8 is a cross-sectional perspective view showing a semiconductor device according to the second embodiment of the present invention. FIG. 9 is a cross-sectional view for explaining the connection position of the buried electrode of the semiconductor device according to the second embodiment shown in FIG. FIG. 10 is an equivalent circuit of the semiconductor device according to the second embodiment shown in FIG. Next, the structure of the semiconductor device according to the second embodiment will be described with reference to FIGS.

  As shown in FIGS. 8 and 9, the semiconductor device 12 according to the second embodiment has a structure in which a region 12a functioning as a normally-off type switching transistor and a region 12b functioning as a Schottky barrier diode are arranged in parallel. have.

  In the region 12a functioning as a switching transistor, a low concentration region is exposed on the upper surface of the n-type epitaxial layer 2 at a portion on the upper surface side of the n-type epitaxial layer 2 (upper end portion of each region between adjacent trenches 3). In order to avoid this, a high concentration region 2a in which n-type impurities are ion-implanted at a high concentration is formed. On the other hand, in the region 12b functioning as a Schottky barrier diode, the high-concentration region 2a as described above is provided in a portion on the upper surface side of the n-type epitaxial layer 2 (upper end portion of each region between adjacent trenches 3). It is not done. That is, in the region 12b functioning as a Schottky barrier diode, the upper surface side portion of the n-type epitaxial layer 2 (the upper end portion of each region between the adjacent trenches 3) is a low concentration region.

  An upper surface electrode layer 27 made of a metal layer (for example, an Al layer) is formed on the upper surface of the n-type epitaxial layer 2 so as to cover the open ends of the plurality of trenches 3. The upper electrode layer 27 includes a portion 27a located in the region 12a functioning as a switching transistor and a portion 27b located in the region 12b functioning as a Schottky barrier diode. The top electrode layer 27 is an example of the “electrode layer” in the present invention. The portions 27a and 27b are examples of the “second portion” and the “first portion” in the present invention, respectively.

  The upper surface electrode layer 27 of the second embodiment is not separated from each other at the boundary between the region 12a functioning as a switching transistor and the region 12b functioning as a Schottky barrier diode, and is composed of only one metal layer. . In the region 12a functioning as a switching transistor, one metal layer constituting the upper electrode layer 27 is in ohmic contact with the high concentration region 2a of the n-type epitaxial layer 2 so as to function as a source electrode of the switching transistor. is doing. On the other hand, in the region 12 b functioning as a Schottky barrier diode, one metal layer constituting the upper electrode layer 27 is in Schottky contact with the low concentration region of the n-type epitaxial layer 2. That is, the junction between the portion 27b of the upper electrode layer 27 and the low concentration region of the n-type epitaxial layer 2 is a Schottky barrier diode. Therefore, one metal layer constituting the upper electrode layer 27 of the second embodiment has both a function as a source electrode of the switching transistor and a function as an anode of the Schottky barrier diode.

  In the second embodiment, the embedded electrode 5 located in the region 12a functioning as a switching transistor includes two types of embedded electrodes (first embedded electrodes) 5a to which voltages are separately applied and embedded electrodes (second embedded electrodes). Electrode) 5b. The embedded electrode 5a is configured to be applied with a voltage corresponding to a predetermined control signal (signal for switching on / off). On the other hand, the embedded electrode 5 b is electrically connected to the upper surface electrode layer 27. That is, the embedded electrode 5 b is configured to have the same potential as that of the upper surface electrode layer 27.

  Furthermore, in the second embodiment, the embedded electrode 5 (hereinafter referred to as embedded electrode 5 c) located in the region 12 b functioning as a Schottky barrier diode is electrically connected to the upper surface electrode layer 27. That is, the embedded electrode 5 c is configured to have the same potential as the upper surface electrode layer 27.

  In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment.

  The semiconductor device 12 of the second embodiment described above can be represented by an equivalent circuit as shown in FIG. That is, in the semiconductor device 12 of the second embodiment, as shown in FIG. 10, a Schottky barrier diode is electrically connected between the source and drain of the switching transistor.

  In the second embodiment, as described above, the Schottky barrier diode is electrically connected between the source and the drain of the switching transistor by electrically connecting the portions 27a and 27b of the top electrode layer 27 to each other. A circuit can be easily obtained. In this case, the semiconductor device 12 can be used as a part of components constituting the DC / DC converter (see FIG. 11). In addition, the codes | symbols 31 and 32 in FIG. 11 are a coil and a capacitor | condenser, respectively. Reference numeral 33 in FIG. 11 is a MOS transistor.

  The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

  FIG. 12 is a cross-sectional perspective view showing a semiconductor device according to a modification of the second embodiment of the present invention. Referring to FIG. 12, in the semiconductor device 13 according to the modification of the second embodiment, each region between adjacent trenches 3 of the n-type epitaxial layer 2 is in an ohmic contact with the upper surface electrode layer 27 (high concentration). Regions 2a) and regions (low concentration regions) in Schottky contact with the upper surface electrode layer 27 are alternately provided in the A direction. That is, the high concentration region 2 a of the n-type epitaxial layer 2 is intermittently provided in the A direction in each region between the adjacent trenches 3 of the n-type epitaxial layer 2.

  In addition, the other structure of the modification of 2nd Embodiment is the same as that of the said 2nd Embodiment.

(Third embodiment)
FIG. 13 is a cross-sectional view for explaining the structure of the semiconductor device according to the third embodiment of the present invention. Next, with reference to FIG. 13, the structure of the semiconductor device according to the third embodiment will be explained.

  In the semiconductor device 14 of the third embodiment, as shown in FIG. 13, a buried electrode 5 (5a) to which a predetermined control signal (signal for switching on / off) is applied to the n-type epitaxial layer 2 is formed. Only trenches 3 (3a) in which are embedded) are provided.

  In the third embodiment, when a voltage is applied between the top electrode layer 7 and the back electrode layer 8, the current flowing between the top electrode layer 7 and the back electrode layer 8 is between the adjacent trenches 3a. It will pass through each area. That is, in the third embodiment, each region between the adjacent trenches 3 a functions as the current path 49.

  The remaining structure of the third embodiment is the same as that of any one of the first and second embodiments described above.

  FIG. 14 is a cross-sectional view for explaining the operation of the semiconductor device according to the third embodiment of the present invention. Next, with reference to FIGS. 13 and 14, the operation of the semiconductor device of the third embodiment will be described.

  First, in the off state, as shown in FIG. 13, a negative potential is applied to all the embedded electrodes 5a so that the depletion layer 10 (10a) is formed around all the trenches 3a. Yes. As a result, the current path 49 is blocked by the depletion layer 10a, so that the current flowing through the current path 49 can be cut off.

  When switching from the off state to the on state, as shown in FIG. 14, all the depletion layers 10a shown in FIG. 13 are extinguished by applying a positive potential to all the buried electrodes 5a. As a result, if a negative potential and a positive potential are applied to each of the top electrode layer 7 and the back electrode layer 8, a current can flow in the direction of the arrow in FIG.

  The effect of the third embodiment is the same as the effect of the first embodiment.

(Fourth embodiment)
FIG. 15 is a cross-sectional view for explaining the structure of the semiconductor device according to the fourth embodiment of the present invention. Next, with reference to FIG. 15, the structure of the semiconductor device according to the fourth embodiment will be explained.

  In the semiconductor device 15 of the fourth embodiment, as shown in FIG. 15, a trench 3 (3a) in which a buried electrode 5 (5a) to which a predetermined control signal is applied is buried in an n-type epitaxial layer 2, and A trench 3 (3d) is provided in which a part of the portion 57a functioning as a source electrode of the upper surface electrode layer 57 (hereinafter referred to as a buried portion 57b) is buried. The trenches 3a and 3d are alternately arranged one by one at a predetermined interval. The buried portion 57b of the upper surface electrode layer 57 is in Schottky contact with the epitaxial layer 2 inside the trench 3d. The upper electrode layer 57 is an example of the “electrode layer” in the present invention, and the portion 57a is an example of the “second portion” in the present invention. The embedded portion 57b is an example of the “embedded electrode” and the “second embedded electrode” in the present invention.

  In the fourth embodiment, when a voltage is applied between the upper surface electrode layer 57 and the rear surface electrode layer 8, the current flowing between the upper surface electrode layer 57 and the rear surface electrode layer 8 is the trench 3 a and the trench 3 d. Will pass through each area. That is, in the fourth embodiment, each region between the trench 3 a and the trench 3 d functions as the current path 59.

  The remaining structure of the fourth embodiment is the same as that of any one of the first and second embodiments described above.

  FIG. 16 is a cross-sectional view for explaining the operation of the semiconductor device according to the fourth embodiment of the present invention. Next, with reference to FIGS. 15 and 16, the operation of the semiconductor device according to the fourth embodiment will be described.

  In the following description of the operation, it is assumed that a negative potential and a positive potential are applied to each of the top electrode layer 57 and the back electrode layer 8. That is, the depletion layer 10 (10d) is formed around the trench 3d in which the buried portion 57b of the upper surface electrode layer 57 is buried regardless of the on state and the off state.

  First, in the off state, as shown in FIG. 15, a negative potential is applied to the buried electrode 5a so that the depletion layer 10 (10a) is formed around the trench 3a. As a result, the current path 59 is blocked by the depletion layers 10a and 10d, so that the current flowing through the current path 59 can be cut off.

  When switching from the off state to the on state, as shown in FIG. 16, the depletion layer 10a shown in FIG. 15 is extinguished by applying a positive potential to the buried electrode 5a. As a result, a current can flow in the direction of the arrow in FIG. 16 through the portion of the current path 59 on the embedded electrode 5a side.

  The effect of the fourth embodiment is the same as the effect of the first embodiment.

(Fifth embodiment)
FIG. 17 is a cross-sectional view for explaining the structure of the semiconductor device according to the fifth embodiment of the present invention. Next, with reference to FIG. 17, the structure of the semiconductor device according to the fifth embodiment will be explained.

In the semiconductor device 16 of the fifth embodiment, as shown in FIG. 17, in addition to the trench 3 (3a) in which the buried electrode 5 (5a) to which a predetermined control signal is applied is buried in the n-type epitaxial layer 2. A p ⁺ -type diffusion layer 61 into which p-type impurities are introduced at a high concentration is further provided. One p ⁺ -type diffusion layer 61 is disposed in each region between adjacent trenches 3a with a predetermined distance from trench 3a. The p ⁺ -type diffusion layer 61 is in ohmic contact with the upper surface electrode layer 7. The p ⁺ -type diffusion layer 61 is an example of the “reverse conductivity type diffusion layer” in the present invention.

In the fifth embodiment, when a voltage is applied between the top electrode layer 7 and the back electrode layer 8, the current flowing between the top electrode layer 7 and the back electrode layer 8 causes the trench 3 a and p ⁺ It passes through each region between the mold diffusion layer 61. That is, in the fifth embodiment, each region between the trench 3 a and the p ⁺ type diffusion layer 61 functions as the current path 69.

  The remaining structure of the fifth embodiment is the same as that of any one of the first and second embodiments described above.

  FIG. 18 is a cross-sectional view for explaining the operation of the semiconductor device according to the fifth embodiment of the present invention. Next, with reference to FIGS. 17 and 18, the operation of the semiconductor device according to the fifth embodiment will be explained.

In the following description of the operation, it is assumed that a negative potential and a positive potential are applied to each of the top electrode layer 7 and the back electrode layer 8. That is, the depletion layer 10 (10e) is formed around the p ⁺ -type diffusion layer 61 regardless of the on state and the off state.

  First, in the off state, as shown in FIG. 17, a negative potential is applied to the buried electrode 5a so that the depletion layer 10 (10a) is formed around the trench 3a. As a result, the current path 69 is blocked by the depletion layers 10a and 10e, so that the current flowing through the current path 69 can be cut off.

  When switching from the off state to the on state, as shown in FIG. 18, the depletion layer 10a shown in FIG. 17 is extinguished by applying a positive potential to the buried electrode 5a. As a result, current can flow in the direction of the arrow in FIG. 18 through the portion of the current passage 69 on the embedded electrode 5a side.

  The effect of the fifth embodiment is the same as the effect of the first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above embodiment, a plurality of trenches are formed in the n-type epitaxial layer, and each region between adjacent trenches of the n-type epitaxial layer functions as a current path. However, the present invention is not limited to this. A plurality of trenches may be formed in the p-type epitaxial layer, and each region between adjacent trenches of the p-type epitaxial layer may function as a current path.

  In the above embodiment, the upper surface of the interlayer insulating film is flush with the upper surface of the n-type epitaxial layer. However, the present invention is not limited to this, and the upper surface of the interlayer insulating film is the n-type epitaxial layer. The upper surface of the interlayer insulating film may be positioned lower than the upper surface of the n-type epitaxial layer.

1 is a cross-sectional perspective view showing a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view for explaining a connection position of a buried electrode of the semiconductor device according to the first embodiment shown in FIG. 1. 2 is an equivalent circuit of the semiconductor device according to the first embodiment shown in FIG. FIG. 6 is a cross-sectional view for explaining the operation of the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view for explaining the operation of the semiconductor device according to the first embodiment of the present invention. 1 is a circuit diagram showing an example of a DC / DC converter using a semiconductor device according to a first embodiment of the present invention. 1 is a circuit diagram showing an example of a DC / DC converter using a semiconductor device according to a first embodiment of the present invention. FIG. 6 is a cross-sectional perspective view showing a semiconductor device according to a second embodiment of the present invention. FIG. 9 is a cross-sectional view for explaining a connection position of a buried electrode of the semiconductor device according to the second embodiment shown in FIG. 8. 9 is an equivalent circuit of the semiconductor device according to the second embodiment shown in FIG. It is the circuit diagram which showed an example of the DC / DC converter using the semiconductor device by 2nd Embodiment of this invention. It is the cross-sectional perspective view which showed the semiconductor device by the modification of 2nd Embodiment of this invention. It is sectional drawing for demonstrating the structure of the semiconductor device by 3rd Embodiment of this invention. It is sectional drawing for demonstrating operation | movement of the semiconductor device by 3rd Embodiment of this invention. It is sectional drawing for demonstrating the structure of the semiconductor device by 4th Embodiment of this invention. It is sectional drawing for demonstrating operation | movement of the semiconductor device by 4th Embodiment of this invention. It is sectional drawing for demonstrating the structure of the semiconductor device by 5th Embodiment of this invention. It is sectional drawing for demonstrating operation | movement of the semiconductor device by 5th Embodiment of this invention. It is sectional drawing which showed the structure of the conventional MOSFET (semiconductor device).

Explanation of symbols

1 n ⁺ type silicon substrate (semiconductor layer)
2 n-type epitaxial layer (semiconductor layer)
3, 3a, 3b, 3c, 3d trench 5, 5c buried electrode 5a buried electrode (first buried electrode)
5b Embedded electrode (second embedded electrode)
7, 27, 57 Upper surface electrode layer (electrode layer)
7a, 27a, 57a part (second part)
7b, 27b part (first part)
9, 49, 59, 69 Current path 10, 10a, 10b, 10c, 10d, 10e Depletion layer 11, 12, 13, 14, 15, 16 Semiconductor device 57b Embedded portion (embedded electrode, second embedded electrode)
61 p ⁺ type diffusion layer (diffusion layer)

Claims (10)

A semiconductor layer of one conductivity type having a plurality of trenches arranged at predetermined intervals from each other and each opening end being located on the upper surface side;
A plurality of embedded electrodes embedded in each of the plurality of trenches;
An electrode layer formed on the upper surface of the semiconductor layer,
Each region between the adjacent trenches of the semiconductor layer serves as a current path, and each region between the adjacent trenches of the semiconductor layer is blocked by a depletion layer formed around the trench. While the passage is blocked, the current passage is configured to be opened when at least part of the depletion layer formed around the trench disappears,
The semiconductor device according to claim 1, wherein an upper surface of a predetermined region of each region between the adjacent trenches of the semiconductor layer is in Schottky contact with the electrode layer.   The electrode layer includes a first portion that is in Schottky contact with an upper surface of a predetermined region of the regions between the adjacent trenches of the semiconductor layer, and a region of the semiconductor layer between the adjacent trenches. The semiconductor device according to claim 1, further comprising: a second portion in ohmic contact with an upper surface of a region other than the predetermined region.   The semiconductor device according to claim 2, wherein the first portion of the electrode layer and the second portion of the electrode layer are electrically separated from each other.   The semiconductor device according to claim 2, wherein the first portion of the electrode layer and the second portion of the electrode layer are electrically connected to each other.   The predetermined region of the semiconductor layer that is in Schottky contact with the electrode layer is provided at least one in each region between the adjacent trenches of the semiconductor layer. The semiconductor device according to any one of the above.   In each region between the adjacent trenches of the semiconductor layer, a predetermined region that makes a Schottky contact with the electrode layer and a region other than the predetermined region that makes a Schottky contact with the electrode layer alternately The semiconductor device according to claim 5, wherein the semiconductor device is provided.   All the depletion layers formed around each of the plurality of trenches are blocked by the regions between the adjacent trenches, thereby blocking the current path, while being formed around each of the plurality of trenches. The semiconductor device according to claim 1, wherein the current path is opened when all the depletion layers thus formed disappear. The plurality of embedded electrodes are divided into two types, a first embedded electrode and a second embedded electrode to which a voltage is applied separately from each other,
The current path is blocked by blocking each region between the adjacent trenches with a depletion layer formed around all of the plurality of trenches, while the one of the plurality of trenches is 7. The semiconductor according to claim 1, wherein the current path is opened when a depletion layer formed around a trench in which the first embedded electrode is embedded disappears. apparatus.   9. The semiconductor device according to claim 8, wherein the second buried electrode is in Schottky contact with the semiconductor layer inside the trench. A diffusion layer of a reverse conductivity type formed in each region between the adjacent trenches of the semiconductor layer and disposed at a predetermined interval with respect to the trench;
A depletion layer formed around each of the trench and the diffusion layer blocks the current path by blocking each region between the adjacent trenches, while a depletion layer formed around the trench. 7. The semiconductor device according to claim 1, wherein the current path is opened when the current disappears.

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