JP2009004411A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can accelerate switching speed. <P>SOLUTION: The semiconductor device 20 is provided with an n-type epitaxial layer 2 having a plurality of trenches 3 that are arranged at specified spacing (b) with each other, an embedded electrode 5 that is formed inside the trench 3 with a silicon oxide film 4 interposed so that each of the trenches 3 may be embedded, and a metal layer 7 that is provided above the embedded electrode 5 with a silicon oxide film 6 interposed and is capacitance-coupled with the embedded electrode 5. In addition, the semiconductor device 20 is constructed so that a region among the adjoining trenches 3 may be a channel (current passage) 11. Current running in the channel 11 is blocked by covering the area with a depletion layer formed in the periphery of the trench 3, and current may flow through the channel 11 by dissolving the depletion layer in the periphery of the trench 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a switching function.

  Conventionally, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is known as a semiconductor device having a switching function (see, for example, Patent Document 1). This Patent Document 1 discloses a trench gate type MOSFET (semiconductor device) in which a gate electrode is embedded in a trench formed in a semiconductor layer of one conductivity type.

FIG. 22 is a cross-sectional view showing the structure of a conventional MOSFET (semiconductor device) disclosed in Patent Document 1. Referring to FIG. 22, in the conventional MOSFET, an epitaxial layer 102 is formed on the upper surface of an n ⁺ type semiconductor substrate 101. In this epitaxial layer 102, an n ⁻ -type impurity region (drain region) 102a, a p-type impurity region 102b, and an n ⁺ -type impurity region (source region) 102c are formed in this order from the semiconductor substrate 101 side.

In addition, trench 103 is formed in epitaxial layer 102 so as to penetrate n ⁺ -type impurity region 102 c and p-type impurity region 102 b and reach a depth in the middle of n ⁻ -type impurity region 102 a. A gate electrode 105 is formed inside the trench 103 via a gate insulating film 104. An interlayer insulating film 106 that closes the opening of the trench 103 is formed in a predetermined region on the upper surface of the epitaxial layer 102.

  A source electrode 107 is formed on the upper surface of the epitaxial layer 102 so as to cover the interlayer insulating film 106. A drain electrode 108 is formed on the back surface (lower surface) of the semiconductor substrate 101. A capacitor (capacitor) is parasitically formed between the gate electrode 105 and the source electrode 107 and the drain region 102a.

In the conventional MOSFET configured as described above, on / off control is performed by changing the voltage applied to the gate electrode 105. Specifically, when a predetermined positive potential is applied to the gate electrode 105, minority carriers (electrons) in the p-type impurity region 102b are attracted to the trench 103 side, whereby an n ⁻ -type impurity region (drain region) 102a. An inversion layer 109 is formed to connect the n ⁺ type impurity region (source region) 102c. As a result, a current can flow between the source electrode 107 and the drain electrode 108 via the inversion layer 109. As a result, the MOSFET is turned on. That is, in the conventional MOSFET, the inversion layer 109 formed so as to connect the n ⁻ -type impurity region (drain region) 102a and the n ⁺ -type impurity region (source region) 102c functions as a channel.

  On the other hand, when the application of a predetermined positive potential to the gate electrode 105 is canceled, the inversion layer (channel) 109 disappears, so that the current flow between the source electrode 107 and the drain electrode 108 can be blocked. As a result, the MOSFET is turned off.

JP 2001-7149 A

  Here, when a capacitor (capacitor) is formed between the gate electrode 105 and the source electrode 107 and the drain region 102a, the voltage applied to the gate electrode 105 is controlled to control the MOSFET (semiconductor device). When performing the on / off control, the formed capacitor (capacitor) is charged and discharged at the same time. For this reason, the on / off switching speed (switching speed) is reduced by the time required for charging and discharging the capacitor. In order to increase the on / off switching speed (switching speed), it is necessary to shorten the time required for charging and discharging the capacitor. That is, it is necessary to reduce the capacitance (input capacitance) of the capacitor (capacitor).

  However, in the conventional MOSFET shown in FIG. 22, the capacitor formed between the gate electrode 105 and the source electrode 107 and between the gate electrode 105 and the drain region 102a is formed parasitically. Therefore, it is difficult to reduce the capacitance of the capacitor. For this reason, there is a problem that it is difficult to increase the switching speed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of increasing the switching speed.

  In order to achieve the above object, a semiconductor device according to an aspect of the present invention includes a one-conductivity-type semiconductor layer having a plurality of trenches arranged at predetermined intervals and embedded in each of the plurality of trenches. A plurality of buried electrodes, and a conductor layer capacitively coupled to the buried electrodes by being formed in at least one of the plurality of trenches and disposed above the buried electrodes via a first insulating film, It has. Note that the semiconductor layer of the present invention includes a semiconductor substrate.

  In the semiconductor device according to this aspect, as described above, a conductor layer formed above the buried electrode through the first insulating film and capacitively coupled to the buried electrode is provided inside the trench, so that the inside of the trench is provided. Since a capacitor (capacitor) connected in series with the buried electrode can be formed, the total capacitance (input capacitance) of the buried electrode inside the trench can be reduced. Thus, by controlling the voltage applied to the embedded electrode, the on / off switching speed can be increased when switching from the off state to the on state or vice versa. That is, the switching speed can be increased.

  In the semiconductor device according to the above aspect, the semiconductor layer is preferably configured such that each region between adjacent trenches serves as a current path, and is adjacent to each other by a depletion layer formed around the plurality of trenches. Each region between the matching trenches is blocked to block the current path, while at least part of the depletion layer formed around the trench disappears to open the current path. When such a configuration is applied to the semiconductor device according to the above aspect, a semiconductor device based on a new operation principle capable of increasing the switching speed and significantly reducing the on-resistance can be obtained. be able to. That is, if a buried electrode is formed on the inner surface of the trench through an insulating film, the formation state of the depletion layer formed around the trench changes according to the voltage applied to the buried electrode. Can be switched from an off state (a state in which the current flowing through the channel is interrupted) to an on state (a state in which current flows through the channel), and vice versa. it can. That is, the semiconductor device can have a switching function. In the above-described configuration, since all of the regions where the depletion layer in each region between adjacent trenches is not formed can function as a channel (current path) when turned on, a very thin inversion layer is used as a channel. Compared with a conventional semiconductor switch device (MOSFET) that functions as a (current path), it is possible to significantly reduce the resistance to the current flowing through the channel. As a result, the on-resistance can be significantly reduced as compared with the conventional semiconductor switch device (MOSFET) while increasing the switching speed.

  In the semiconductor device according to the above aspect, the conductor layer is preferably formed inside each of the plurality of trenches and is capacitively coupled to the buried electrode. With this configuration, the total capacitance (input capacitance) of each embedded electrode can be reduced, so that the switching speed can be easily increased.

  In the semiconductor device according to the above aspect, the second insulating film is formed on the upper surface of the conductor layer, and the second insulating film is formed in the trench so that the upper surface is flush with the upper surface of the semiconductor layer. May be.

  In the semiconductor device according to the above aspect, the predetermined embedded electrode of the plurality of embedded electrodes is preferably formed on the inner surface of the trench via the third insulating film, and the thickness of the first insulating film is It is not less than the thickness of the third insulating film. With this configuration, since the dielectric breakdown in the first insulating film can be suppressed, even if the conductor layer is formed in the trench via the first insulating film, the dielectric breakdown of the first insulating film is prevented. As a result, it is possible to suppress the disadvantage that the breakdown voltage characteristics of the semiconductor device are deteriorated.

  In the semiconductor device according to the above aspect, the width of the conductor layer in the trench arrangement direction is preferably smaller than the width of the buried electrode. If comprised in this way, since the plane area of a conductor layer can be made small, the electrostatic capacitance between a buried electrode and a conductor layer can be made small. For this reason, the total capacitance (input capacitance) of the buried electrode in the trench can be easily reduced.

  In the semiconductor device according to the aforementioned aspect, the conductor layer is preferably made of a metal material. If comprised in this way, since a conductor layer can be easily formed in a trench, a capacitor (capacitor) connected in series with a buried electrode can be easily formed in the trench.

  In the semiconductor device according to the above aspect, the conductor layer is preferably made of at least one metal material selected from W, Ti, and TiN. With this configuration, the conductor layer can be more easily formed in the trench, and thus a capacitor (capacitor) connected in series with the buried electrode can be more easily formed in the trench. .

  In the semiconductor device according to the above aspect, each of the plurality of trenches may be formed in an elongated shape so as to extend in parallel with each other in a direction parallel to the upper surface of the semiconductor layer and perpendicular to the arrangement direction of the trenches. .

  In the semiconductor device configured such that each region between the adjacent trenches serves as a current path, each region between adjacent trenches is blocked by all the depletion layers formed around each of the plurality of trenches. While the current path is interrupted by this, all the depletion layers formed around each of the plurality of trenches may disappear so that the current path is opened.

  In the semiconductor device configured such that each region between the adjacent trenches serves as a current path, the plurality of embedded electrodes are divided into two types, a first embedded electrode and a second embedded electrode to which a voltage is applied separately. The current path is blocked by blocking each region between adjacent trenches by a depletion layer formed around all of the plurality of trenches, while The current path may be configured to be opened when the depletion layer formed around the trench in which the first embedded electrode is embedded disappears.

  In this case, the second embedded electrode may be in Schottky contact with the semiconductor layer inside the trench.

  In the semiconductor device configured such that each region between the adjacent trenches serves as a current path, the semiconductor device is formed in each region between the adjacent trenches of the semiconductor layer, and is reversely arranged at a predetermined interval with respect to the trench. A conduction type diffusion region is further provided, and a depletion layer formed in the periphery of each of the trench and the diffusion region blocks each region between adjacent trenches, thereby blocking a current path, while surrounding the trench. The current path may be configured to be opened when the depletion layer formed on the substrate disappears.

  As described above, according to the present invention, it is possible to easily obtain a semiconductor device capable of increasing the switching speed.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments embodying the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment of the present invention. First, the structure of the semiconductor device 20 according to the first embodiment of the present invention will be described with reference to FIG. Note that the semiconductor device 20 according to the first embodiment is configured to function as a normally-off type switching device.

In the semiconductor device 20 according to the first embodiment, the n type epitaxial layer 2 made of n type silicon having a thickness (a) of about 1 μm to about 10 μm is formed on the upper surface of the n ⁺ type silicon substrate 1. . An n-type impurity is introduced into the n ⁺ -type silicon substrate 1 at a high concentration in order to obtain a good ohmic contact with a drain electrode 10 described later. In addition, n-type impurities are introduced into the n-type epitaxial layer 2 at a lower concentration than the n ⁺ -type silicon substrate 1 (for example, about 5 × 10 ¹⁵ cm ⁻³ to about 1.0 × 10 ¹⁸ cm ⁻³ ). ing. The n-type epitaxial layer 2 is an example of the “one conductivity type semiconductor layer” in the present invention.

  The n-type epitaxial layer 2 has a plurality of trenches 3 dug in the thickness direction. The plurality of trenches 3 are formed by etching a predetermined region of the n-type epitaxial layer 2 from the upper surface (main surface) side. That is, the open ends of the plurality of trenches 3 are located on the upper surface side of the n-type epitaxial layer 2.

  The plurality of trenches 3 are formed in an elongated shape so that each of them extends along a predetermined direction parallel to the upper surface of the n-type epitaxial layer 2. In addition, the plurality of trenches 3 are parallel to the upper surface of the n-type epitaxial layer 2 and are spaced apart from each other by about 0.05 μm to about 0.3 μm in the direction (A direction) orthogonal to the direction in which the trenches 3 extend (A direction). b). Furthermore, the groove depth (c) of each of the plurality of trenches 3 is set to about 0.5 μm to about 5 μm so as to be smaller than the thickness (a) of the n-type epitaxial layer 2. The width (d) in the A direction of the plurality of trenches 3 is set to about 0.1 μm to about 1 μm.

  A silicon oxide film 4 obtained by thermally oxidizing n-type silicon constituting the n-type epitaxial layer 2 is formed on each inner surface of the plurality of trenches 3 with a thickness of about 10 nm to about 100 nm. ing. The silicon oxide film 4 is an example of the “third insulating film” in the present invention.

  A buried electrode (gate electrode) 5 made of p-type polysilicon is formed on the inner surface of each of the plurality of trenches 3 with a silicon oxide film 4 interposed therebetween. Each of the plurality of buried electrodes (gate electrodes) 5 is buried to a depth in the middle of the corresponding trench 3.

  In the first embodiment, by providing a plurality of embedded electrodes (gate electrodes) 5 as described above and controlling the voltage applied to the plurality of embedded electrodes (gate electrodes) 5, the periphery of each of the plurality of trenches 3 is provided. It is possible to form a depletion layer or to eliminate the formed depletion layer. In the first embodiment, the interval (b) between the trenches 3 adjacent to each other is such that the depletion layer formed in each of the adjacent trenches 3 when the depletion layer is formed around each of the plurality of trenches 3. Are set to overlap each other. That is, when a depletion layer is formed around each of the plurality of trenches 3, the depletion layers formed around each of the adjacent trenches 3 are connected to each other. For this reason, in the first embodiment, if a depletion layer is formed around each of the plurality of trenches 3, it is possible to block each region between adjacent trenches 3 with the depletion layer.

  In the first embodiment, the metal layer 7 made of W (tungsten) is formed above the buried electrode (gate electrode) 5 in each of the plurality of trenches 3 with the silicon oxide film 6 interposed therebetween. . The metal layer 7 is formed so that the width in the A direction is smaller than the width in the A direction of the buried electrode (gate electrode) 5, and the trench 3 is opposed to the buried electrode (gate electrode) 5. Is disposed inside. On the other hand, a gate pad electrode (not shown) is formed in a predetermined region on the upper surface of the n-type epitaxial layer 2, and the metal layer 7 provided in each of the plurality of trenches 3 passes through a wiring layer (not shown). Are electrically connected to gate pad electrodes (not shown). That is, the metal layer 7 is capacitively coupled to the buried electrode (gate electrode) 5. Thereby, in each of the plurality of trenches 3, a capacitor (capacitor) having the silicon oxide film 6 as a dielectric layer is embedded in the buried electrode (gate electrode) 5 by the metal layer 7 and the buried electrode (gate electrode) 5. And is formed in series.

  In the first embodiment, as described above, the gate input capacitance is greatly reduced by providing the metal layer 7 capacitively coupled to the buried electrode (gate electrode) 5 in each of the plurality of trenches 3. It becomes possible to do. In other words, when the embedded electrode (gate electrode) 5 and the metal layer 7 are capacitively coupled, a capacitor (capacitor) is connected in series to the embedded electrode (gate electrode) 5. The total capacitance (gate input capacitance) C is expressed by the following equation (1).

ここで、Ｃ_GMは、埋め込み電極（ゲート電極）５とメタル層７によって形成されるキャパシタ（コンデンサ）の静電容量を、Ｃ_Gは、埋め込み電極（ゲート電極）５との間に寄生的に形成されるキャパシタ（コンデンサ）の静電容量（ただし、Ｃ_GMを除く）をそれぞれ示している。

Here, C _GM is the capacitance of the buried electrode capacitor formed by (gate electrode) 5 and the metal layer 7 (capacitor), C _G is parasitically between the embedded electrode (gate electrode) 5 the capacitance of the capacitor (condenser) is formed (except for C _GM) respectively show.

When showing a specific numerical value, for example, C _G is at 2000 pF, C _GM is the case of 100pF, from equation (1), the buried electrode total capacitance of (gate electrode) 5 (Gate The input capacitance (C) is about 95 pF. Thus, by capacitively coupling the metal layer 7 with the buried electrode (gate electrode) 5, the gate input capacitance can be greatly reduced. From the above equation (1), the smaller the capacitance C _GM of the capacitor (capacitor) formed by the embedded electrode (gate electrode) 5 and the metal layer 7, the smaller the total electrostatic capacity of the embedded electrode (gate electrode) 5. The capacity C is reduced.

  In the first embodiment, the silicon oxide film 6 is formed to have a thickness equal to or greater than the thickness of the silicon oxide film 4. The silicon oxide film 6 is an example of the “first insulating film” in the present invention, and the metal layer 7 is an example of the “conductor layer” in the present invention.

Further, an interlayer insulating film 8 made of SiO ₂ is formed in a portion above each of the metal layers 7 in each of the plurality of trenches 3. The upper surface of each interlayer insulating film 8 is flush with the upper surface of the n-type epitaxial layer 2 (the upper surface of the upper end of each region between adjacent trenches 3). The interlayer insulating film 8 is an example of the “second insulating film” in the present invention.

  In addition, n-type impurities are high in a portion on the upper surface side of the n-type epitaxial layer 2 (upper end portion of each region between adjacent trenches 3) so that a low concentration region is not exposed on the upper surface of the n-type epitaxial layer 2. A high concentration region 2a ion-implanted at a concentration is formed. The impurity concentration of the high concentration region 2a of the n-type epitaxial layer 2 is set so as to obtain a good ohmic contact with the source electrode 9 described later. The impurity concentration is higher than that of the portion.

A source electrode 9 made of an Al layer is formed on the upper surface of the n-type epitaxial layer 2 so as to cover the open ends of the plurality of trenches 3. The source electrode 9 is in ohmic contact with the high concentration region 2a (the upper end portion of each region between adjacent trenches 3) 2a of the n-type epitaxial layer 2. On the back surface (lower surface) of the n ⁺ -type silicon substrate 1, a drain electrode 10 made of a multilayer structure in which a plurality of metal layers are stacked is formed. The drain electrode 10 is in ohmic contact with the n ⁺ type silicon substrate 1.

  In the configuration described above, when a voltage is applied between the source electrode 9 and the drain electrode 10, the current flowing between the source electrode 9 and the drain electrode 10 (current flowing in the thickness direction of the n-type epitaxial layer 2) is , Each region between the adjacent trenches 3 of the n-type epitaxial layer 2 is passed. That is, in the above-described configuration, each region between adjacent trenches 3 of the n-type epitaxial layer 2 functions as a channel (current path) 11.

  2 and 3 are cross-sectional views for explaining the operation of the semiconductor device according to the first embodiment of the present invention. 2 illustrates a case where a semiconductor device functioning as a switch device is in an off state, and FIG. 3 illustrates a case where a semiconductor device functioning as a switch device is in an on state. ing. Next, the operation of the semiconductor device 20 functioning as the switch device according to the first embodiment will be described with reference to FIGS.

  In the following description, it is assumed that a negative potential is applied to the source electrode 9 and a positive potential is applied to the drain electrode 10. That is, when the semiconductor device 20 functioning as a switch device is in an on state, a current flows from the drain electrode 10 to the source electrode 9 (in the arrow direction in FIG. 3).

  First, when the semiconductor device 20 functioning as a switch device is in an OFF state, as shown in FIG. 2, the majority carriers existing around the trench 3 in which the buried electrode (gate electrode) 5 is buried are reduced. The voltage applied to the buried electrode (gate electrode) 5 is controlled. Here, since the metal layer 7 and the buried electrode (gate electrode) 5 are capacitively coupled, the voltage applied to the buried electrode (gate electrode) 5 is controlled by controlling the voltage applied to the metal layer 7. Is called. Thereby, a depletion layer 12 is formed around the trench 3.

  At this time, in the region between the adjacent trenches 3, part of the depletion layers 12 formed around each of the adjacent trenches 3 overlap each other. That is, in the region between the adjacent trenches 3, the depletion layers 12 formed around the adjacent trenches 3 are connected to each other. As a result, the channel 11 is blocked by the depletion layer 12, so that the current flowing through the channel 11 is blocked. Therefore, the semiconductor device 20 functioning as a switch device is turned off.

  Next, when the semiconductor device 20 functioning as a switch device is switched from the off state to the on state, as shown in FIG. 3, a predetermined positive potential (with respect to the embedded electrode (gate electrode) 5 (metal layer 7)) By applying a predetermined voltage, the depletion layer 12 (see FIG. 2) formed around the trench 3 is extinguished. As a result, current can flow through the channel 11, so that the semiconductor device 20 functioning as a switch device can be turned on.

  When the semiconductor device 20 functioning as a switch device is switched from an on state to an off state, the application of a predetermined positive potential (predetermined voltage) to the embedded electrode (gate electrode) 5 (metal layer 7) is canceled. As a result, the state shown in FIG. 2 is restored, so that the semiconductor device 20 functioning as a switch device can be turned off.

  In the first embodiment, as described above, the metal layer 7 that is capacitively coupled to the buried electrode (gate electrode) 5 is formed inside each of the plurality of trenches 3, whereby the inside of each of the plurality of trenches 3 is formed. Since a capacitor (capacitor) connected in series with the buried electrode (gate electrode) 5 can be formed in the first electrode, the total capacitance (gate input) of the buried electrode (gate electrode) 5 inside each of the plurality of trenches 3 can be formed. (Capacity) can be reduced. Thus, by controlling the voltage applied to the buried electrode (gate electrode) 5, the on / off switching speed can be increased when switching from the off state to the on state or vice versa. it can. That is, the switching speed can be increased. In addition, since the total capacitance (gate input capacitance) of the buried electrode (gate electrode) 5 can be reduced, the threshold voltage of the buried electrode (gate electrode) 5 can be increased.

  Further, in the first embodiment, the channel (the adjacent trenches 3) is closed by closing the channel (each region between the adjacent trenches 3) 11 with all the depletion layers 12 formed around each of the plurality of trenches 3. While the current flowing through each of the plurality of trenches 3 is interrupted, all the depletion layers 12 formed around each of the plurality of trenches 3 are eliminated, whereby the channel (each region between the adjacent trenches 3) 11. In this way, the formation state of the depletion layer 12 formed around the trench 3 changes according to the voltage applied to the buried electrode (gate electrode) 5, so that the buried electrode (gate electrode) ) By controlling the applied voltage to 5, the current flows through the channel 11 from the off state (the state where the current flowing through the channel 11 is interrupted). It is possible to switch to a state) that can be carried out switching the reverse. That is, the semiconductor device 20 can have a switching function. In the above-described configuration, since all the portions where the depletion layer 12 in each region between the adjacent trenches 3 disappears can function as the channel (current path) 11 at the time of ON, a very thin inversion layer can be formed. Compared to a conventional semiconductor switch device (MOSFET) that functions as a channel (current path), the resistance to the current flowing through the channel 11 can be greatly reduced. As a result, the on-resistance can be significantly reduced as compared with the conventional semiconductor switch device (MOSFET) while increasing the switching speed.

  In the first embodiment, the interlayer insulating film 8 is formed on the upper surface of the metal layer 7, and the interlayer insulating film 8 is formed in each trench so that the upper surface is flush with the upper surface of the n-type epitaxial layer 2. In the interlayer insulating film 8 formed in the trenches 3 adjacent to each other, the interlayer insulating film 8 formed in the other trench 3 adjacent to the interlayer insulating film 8 formed in the one trench 3 is formed. Can be prevented from coming into contact with each other. For this reason, when the depletion layer 12 is formed in the periphery of each of the plurality of trenches 3 with the space (b) between the adjacent trenches 3, a part of the depletion layer 12 formed in each of the adjacent trenches 3 is It can be easily set to overlap each other.

  In the first embodiment, since the thickness of the silicon oxide film 6 is set to be equal to or greater than the thickness of the silicon oxide film 4, dielectric breakdown in the silicon oxide film 6 can be suppressed. It is possible to suppress the inconvenience that the breakdown voltage characteristics of the semiconductor device 20 are deteriorated due to the dielectric breakdown.

  In the first embodiment, the metal layer 7 in the arrangement direction (A direction) of the trenches 3 is configured so that the width of the buried electrode (gate electrode) 5 is smaller than the width in the A direction. Since the plane area of the layer 7 can be reduced, the capacitance between the buried electrode (gate electrode) 5 and the metal layer 7 can be reduced. Therefore, the total capacitance (gate input capacitance) of the embedded electrode (gate electrode) can be easily reduced.

  In the first embodiment, since the metal layer 7 is made of W (tungsten), the metal layer 7 can be easily formed inside the trench 3. Therefore, the metal layer 7 can be easily formed inside the trench 3. A capacitor (capacitor) connected in series with the buried electrode (gate electrode) 5 can be formed.

  4 to 13 are cross-sectional views for explaining a method of manufacturing the semiconductor device according to the first embodiment of the present invention shown in FIG. Next, with reference to FIGS. 1 and 4 to 13, a method for manufacturing the semiconductor device 20 according to the first embodiment of the present invention will be described.

First, a thickness (a) (see FIG. 1) of about 1 μm to about 10 μm is formed on the upper surface of the n ⁺ type silicon substrate 1 into which n-type impurities are introduced at a high concentration by an epitaxial growth method or the like, and the n ⁺ type is also used. Growing an n-type epitaxial layer 2 made of n-type silicon into which an n-type impurity is introduced at a concentration lower than that of the silicon substrate 1 (for example, about 5 × 10 ¹⁵ cm ⁻³ to about 1.0 × 10 ¹⁸ cm ⁻³ ). Let Next, as shown in FIG. 4, a plurality of trenches 3 are formed in a predetermined region of the n-type epitaxial layer 2 by using a photolithography technique and an etching technique. At this time, the plurality of trenches 3 are formed in an elongated shape so that each of them extends along a predetermined direction parallel to the upper surface of the n-type epitaxial layer 2. Further, as shown in FIG. 1, the plurality of trenches 3 are approximately 0.05 μm from each other in a direction (A direction) that is parallel to the upper surface of the n-type epitaxial layer 2 and orthogonal to the direction in which the trenches 3 extend. They are arranged with an interval (b) of about 0.3 μm. Further, the plurality of trenches 3 are formed to have a groove depth (c) of about 0.5 μm to about 5 μm so as to be smaller than the thickness (a) of the n-type epitaxial layer 2. The width (d) in the A direction of the trench 3 is formed to be about 0.1 μm to about 1 μm.

Next, defects added to the n-type epitaxial layer 2 by etching are removed. Specifically, sacrificial oxidation is performed, and a surface oxide layer (SiO ₂ layer: not shown) formed by the sacrificial oxidation is removed by etching.

Subsequently, by subjecting the n ⁺ type silicon substrate 1 to a thermal oxidation treatment, a surface oxide (SiO ₂ ) layer 4a is grown as shown in FIG. Thus, the silicon oxide film 4 made of SiO ₂ (4a) is formed so as to cover the inner wall of the trench 3 (bottom and side surfaces). At this time, the silicon oxide film 4 (4a) is grown to a thickness of about 10 nm to about 100 nm.

  Next, as shown in FIG. 6, a polysilicon layer 5a made conductive by introducing impurities is formed on the entire surface by CVD or the like. Then, as shown in FIG. 7, a predetermined region of the polysilicon layer 5a is removed by etch back. Thereby, the upper surface (etch back surface) of the polysilicon layer 5a in each trench 3 is formed below the upper surface of the n-type epitaxial layer 2, and a buried electrode (gate electrode) made of polysilicon is formed in the trench 3. ) 5 is formed.

Thereafter, as shown in FIG. 8, a SiO ₂ layer 6a is formed on the entire surface. Then, as shown in FIG. 9, a metal layer 7a made of W (tungsten) is formed on the entire surface by vapor deposition or the like.

Subsequently, as shown in FIG. 10, the metal layer 7 is formed inside the trench 3 by removing a predetermined region of the metal layer 7 a by metal etch back. Next, as shown in FIG. 11, the SiO ₂ layer 8a is formed on the entire surface. Then, the SiO ₂ layer 8a, the SiO ₂ layer 6a and the surface oxide layer 4a are removed by etch back until the upper surface of the n-type epitaxial layer 2 is exposed. Thereby, as shown in FIG. 12, an interlayer insulating film 8 whose upper surface is substantially flush with the upper surface of the n-type epitaxial layer 2 is formed on the upper surface of the buried electrode (gate electrode) 5. The upper surface of the n-type epitaxial layer 2 is planarized. A metal layer 7 is formed above the buried electrode (gate electrode) 5 with a silicon oxide film 6 interposed therebetween.

Next, as shown in FIG. 13, a high concentration region 2 a in which n type impurities are ion-implanted at a high concentration is formed so that the low concentration region is not exposed on the upper surface of the n type epitaxial layer 2. Then, as shown in FIG. 1, a source electrode 9 made of an Al layer is formed on the upper surface of the n-type epitaxial layer 2 so as to cover the open ends of the plurality of trenches 3. Finally, on the back surface (lower surface) of the n ⁺ -type silicon substrate 1, a drain electrode 10 made of a multilayer structure in which a plurality of metal layers are stacked is formed. Thus, the semiconductor device 20 according to the first embodiment of the present invention shown in FIG. 1 is formed.

(Second Embodiment)
FIG. 14 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. Next, the structure of the semiconductor device 30 according to the second embodiment of the present invention will be described with reference to FIG.

  In the semiconductor device 30 according to the second embodiment, the buried electrode 5 made of p-type polysilicon is formed on the inner surface of each of the plurality of trenches 3 with the silicon oxide film 4 interposed therebetween. The plurality of embedded electrodes 5 are divided into two types of embedded electrodes 5a and 5b to which voltages are separately applied. One embedded electrode 5a is configured to be applied with a voltage corresponding to a predetermined control signal (signal for switching on / off). The other embedded electrode 5 b is electrically connected to the source electrode 9. That is, the other embedded electrode 5 b is configured to have the same potential as the source electrode 9. The embedded electrodes 5a and 5b are alternately arranged one by one in the A direction. Therefore, one embedded electrode 5b (5a) is arranged between the two embedded electrodes 5a (5b). The embedded electrodes 5a and 5b are examples of the “first embedded electrode” and the “second embedded electrode” in the present invention, respectively.

In the trench 3 in which the embedded electrode 5a is embedded (hereinafter referred to as the trench 3a), a metal layer 7 made of W (tungsten) is formed above the embedded electrode 5a with the silicon oxide film 6 interposed therebetween. Yes. This metal layer 7 is capacitively coupled to the buried electrode 5a. Further, an interlayer insulating film 8 (8a) made of a silicon oxide film is formed in a portion above the metal layer 7 in the trench 3a. On the other hand, in the trench 3 in which the embedded electrode 5b is embedded (hereinafter referred to as the trench 3b), the interlayer insulating film 8 (8b) made of SiO ₂ is formed in the portion above the embedded electrode 5b without forming the metal layer 7. Is formed. The remaining structure of the semiconductor device 30 according to the second embodiment is the same as the structure of the semiconductor device 20 according to the first embodiment described above.

  FIG. 15 is a cross-sectional view for explaining the operation of the semiconductor device according to the second embodiment of the present invention. Next, the operation of the semiconductor device 30 according to the second embodiment of the present invention will be described with reference to FIGS. In the following description of the operation, it is assumed that a negative potential and a positive potential are applied to each of the source electrode 9 and the drain electrode 10.

  First, in the off state, as shown in FIG. 14, since the embedded electrode 5b is electrically connected to the source electrode 9, a negative potential is applied to the embedded electrode 5b. Therefore, majority carriers are reduced around the trench 3 (3b) in which the buried electrode 5b is buried. That is, the depletion layer 12 (12b) is formed around the trench 3b regardless of the on state and the off state. In the off state, the voltage applied to the buried electrode 5a is controlled so that the majority carriers existing around the trench 3 (3a) in which the buried electrode 5a is buried are reduced. As a result, a depletion layer 12 (12a) similar to the depletion layer 12 (12b) formed around the trench 3b is also formed around the trench 3a.

  At this time, in the region between the trench 3a and the trench 3b, part of the depletion layers 12a and 12b formed around the trenches 3a and 3b overlap each other. That is, in the region between trench 3a and trench 3b, depletion layers 12a and 12b are connected to each other. Thus, the channel (current path) 31 is blocked by the depletion layers 12a and 12b, so that the current flowing through the channel (current path) 31 can be blocked. Therefore, the semiconductor device 30 is turned off.

  When switching from the off state to the on state, as shown in FIG. 15, a depletion layer 12a (FIG. 14) formed around the trench 3a by applying a predetermined positive potential to the buried electrode 5a. See). That is, current can flow in the direction of the arrow in FIG. 15 through the portion of the channel (current path) 31 on the buried electrode 5a side (trench 3a side), so that the semiconductor device 30 can be turned on. Become.

  In addition, when switching the semiconductor device 30 from the on state to the off state, the application of a predetermined positive potential to the embedded electrode 5a is canceled. As a result, the state shown in FIG. 14 is restored, so that the semiconductor device 30 can be turned off.

  The effect of the second embodiment is the same as the effect of the first embodiment.

(Third embodiment)
FIG. 16 is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment of the present invention. Next, the structure of the semiconductor device 40 according to the third embodiment of the present invention will be described with reference to FIG.

  In the semiconductor device 40 according to the third embodiment, the trench 3 (3a) in which the buried electrode 5 (5a) to which a predetermined control signal is applied is buried, and a part of the source electrode 41 (hereinafter referred to as the buried portion 41a). And a trench 3 (3c) embedded therein. The trenches 3a and 3c are alternately arranged one by one at a predetermined interval. The buried portion 41a of the source electrode 41 is in Schottky contact with the epitaxial layer 2 inside the trench 3c. The buried portion 41a of the source electrode 41 is an example of the “second buried electrode” in the present invention.

  In the third embodiment, when a voltage is applied between the source electrode 41 and the drain electrode 10, the current flowing between the source electrode 41 and the drain electrode 10 is between the trench 3a and the trench 3c. It will pass through each area. That is, in the third embodiment, each region between the trench 3 a and the trench 3 c functions as a channel (current path) 42.

  In the trench 3a, a metal layer 7 made of W (tungsten) is formed above the buried electrode 5a, as in the second embodiment.

  The other structure of the semiconductor device 40 according to the third embodiment is the same as the structure of the semiconductor device 20 according to the first embodiment.

  FIG. 17 is a cross-sectional view for explaining the operation of the semiconductor device according to the third embodiment of the present invention. Next, with reference to FIG. 16 and FIG. 17, the operation of the semiconductor device 40 according to the third embodiment of the present invention will be described.

  In the following description of the operation, it is assumed that a negative potential and a positive potential are applied to the source electrode 41 and the drain electrode 10, respectively. That is, the depletion layer 12 (12c) is formed around the trench 3c in which the buried portion 41a of the source electrode 41 is buried regardless of the on state and the off state.

  First, in the off state, as shown in FIG. 16, a negative potential is applied to the buried electrode 5a so that the depletion layer 12 (12a) is formed around the trench 3a. As a result, the channel (current path) 42 is blocked by the depletion layers 12a and 12c, so that the current flowing through the channel (current path) 42 can be cut off.

  When switching from the off state to the on state, as shown in FIG. 17, the depletion layer 12a shown in FIG. 16 is extinguished by applying a positive potential to the buried electrode 5a. As a result, current can flow in the direction of the arrow in FIG. 17 through the portion of the channel (current path) 42 on the embedded electrode 5a side (trench 3a side).

  When the semiconductor device 40 is switched from the on state to the off state, the application of a predetermined positive potential to the embedded electrode 5a is canceled. As a result, the state shown in FIG. 16 is restored, so that the semiconductor device 40 can be turned off.

  The effect of the third embodiment is the same as the effect of the first embodiment.

(Fourth embodiment)
FIG. 18 is a sectional view showing the structure of a semiconductor device according to the fourth embodiment of the present invention. Next, the structure of the semiconductor device 50 according to the fourth embodiment of the present invention will be described with reference to FIG.

In the semiconductor device 50 according to the fourth embodiment, in addition to the trench 3 (3a) in which the buried electrode 5 (5a) to which a predetermined control signal is applied is buried, p in which p-type impurities are introduced at a high concentration. ^{A +} type diffusion region 51 is further provided. The p ⁺ -type diffusion regions 51 are arranged one by one in each region between adjacent trenches 3 (3a) at a predetermined interval with respect to the trench 3 (3a). The p ⁺ -type diffusion region 51 is in ohmic contact with the source electrode 9. The p ⁺ -type diffusion region 51 is an example of the “reverse conductivity type diffusion region” in the present invention.

In the fourth embodiment, when a voltage is applied between the source electrode 9 and the drain electrode 10, the current flowing between the source electrode 9 and the drain electrode 10 flows between the trench 3 (3 a) and p ^+. Each region between the mold diffusion region 51 and the mold diffusion region 51 is passed. That is, in the fourth embodiment, each region between the trench 3 (3 a) and the p ⁺ -type diffusion region 51 functions as a channel (current path) 52.

  In the trench 3 (3a), a metal layer 7 made of W (tungsten) is formed above the buried electrode 5a, as in the second and third embodiments.

  The other structure of the semiconductor device 50 according to the fourth embodiment is the same as the structure of the semiconductor device 20 according to the first embodiment.

  FIG. 19 is a cross-sectional view for explaining the operation of the semiconductor device according to the fourth embodiment of the present invention. Next, with reference to FIGS. 18 and 19, the operation of the semiconductor device 50 according to the fourth embodiment of the present invention will be described.

In the following description of the operation, it is assumed that a negative potential and a positive potential are applied to each of the source electrode 9 and the drain electrode 10. That is, the depletion layer 12 (12d) is formed around the p ⁺ -type diffusion region 51 regardless of the on state and the off state.

  First, in the off state, as shown in FIG. 18, a negative potential is applied to the buried electrode 5a so that the depletion layer 12 (12a) is formed around the trench 3a. As a result, the channel (current path) 52 is blocked by the depletion layers 12a and 12d, so that the current flowing through the channel (current path) 52 can be cut off.

  When switching from the off state to the on state, as shown in FIG. 19, the depletion layer 12a shown in FIG. 18 is extinguished by applying a positive potential to the buried electrode 5a. As a result, current can flow in the direction of the arrow in FIG. 19 through the portion of the channel (current path) 52 on the embedded electrode 5a side (trench 3a side).

  In addition, when the semiconductor device 50 is switched from the on state to the off state, the application of a predetermined positive potential to the embedded electrode 5a is canceled. As a result, the state shown in FIG. 18 is restored, so that the semiconductor device 50 can be turned off.

  The effect of the fourth embodiment is the same as the effect of the first embodiment.

(Fifth embodiment)
FIG. 20 is a cross-sectional view showing the structure of a semiconductor device according to the fifth embodiment of the present invention. Next, referring to FIG. 20, the semiconductor device 60 according to the fifth embodiment is configured as a trench gate type MOSFET in which a buried electrode (gate electrode) 5 is buried inside the trench 3. That is, in the semiconductor device 60 according to the fifth embodiment, in each region between adjacent trenches 3, a high concentration region (source region) 2 a and a low concentration region (drain region) 2 c of the n-type epitaxial layer 2 are formed. A p-type impurity region 2b is formed therebetween.

  In the fifth embodiment, when a predetermined positive potential is applied to the metal layer 7, the metal layer 7 and the embedded electrode (gate electrode) 5 are capacitively coupled. Is applied. For this reason, since minority carriers (electrons) in the p-type impurity region 2b are attracted to the trench 3, the low-concentration region (drain region) 2c and the high-concentration region (source region) are formed around the trench 3 in the p-type impurity region 2b. ) An inversion layer 13 is formed so as to connect 2a. A current can flow between the source electrode 9 and the drain electrode 10 through the inversion layer 13, so that the semiconductor device 60 is turned on. On the other hand, when the application of the predetermined positive potential to the metal layer 7 is canceled, the application of the predetermined positive potential to the buried electrode (gate electrode) 5 is canceled, so that the inversion layer 13 disappears. As a result, the current flow between the source electrode 9 and the drain electrode 10 can be interrupted, so that the semiconductor device 60 is turned off.

  The other configuration of the semiconductor device 60 according to the fifth embodiment is the same as that of the semiconductor device 20 according to the first embodiment.

  In the fifth embodiment, as described above, the metal layer 7 that is capacitively coupled to the buried electrode (gate electrode) 5 is formed inside each of the plurality of trenches 3, whereby the inside of each of the plurality of trenches 3 is formed. Since a capacitor (capacitor) connected in series with the buried electrode (gate electrode) 5 can be formed in the first electrode, the total capacitance (gate input) of the buried electrode (gate electrode) 5 inside each of the plurality of trenches 3 can be formed. (Capacity) can be reduced. Thus, by controlling the voltage applied to the buried electrode (gate electrode) 5, the on / off switching speed can be increased when switching from the off state to the on state or vice versa. it can. That is, the switching speed can be increased.

  In the fifth embodiment, the interlayer insulating film 8 is formed on the upper surface of the metal layer 7, and the interlayer insulating film 8 is formed in each trench so that the upper surface is flush with the upper surface of the n-type epitaxial layer 2. In the interlayer insulating film 8 formed in the trenches 3 adjacent to each other, the interlayer insulating film 8 formed in the other trench 3 adjacent to the interlayer insulating film 8 formed in the one trench 3 is formed. Can be prevented from coming into contact with each other. For this reason, since the interval (b) between the adjacent trenches 3 can be easily shortened, the trench density per unit area is increased by reducing the interval (b) between the adjacent trenches 3. can do. As a result, since the total area of the inversion layer 13 can be increased, the on-resistance can be reduced while increasing the switching speed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes meanings equivalent to the scope of claims for patent and all modifications within the scope.

  For example, in the first to fifth embodiments, an example in which a trench or the like is formed in an epitaxial layer formed on a silicon substrate has been shown. However, the present invention is not limited to this, and a silicon substrate (semiconductor substrate) is formed. A trench or the like may be directly formed in a silicon substrate (semiconductor substrate) without forming an epitaxial layer. Further, after forming a trench or the like in the epitaxial layer formed on the silicon substrate, the silicon substrate may be removed by polishing or the like.

In the first to fifth embodiments, the configuration in which the n-type epitaxial layer is formed on the n ⁺ -type silicon substrate is shown. However, the present invention is not limited to this, and the p ⁺ -type silicon substrate is formed on the p ⁺ -type silicon substrate. A p-type epitaxial layer may be formed. In other words, all the conductivity types may be reversed.

  Moreover, in the said 1st-5th embodiment, although the example which formed one metal layer in the inside of a trench was shown, this invention is not restricted to this, As shown in FIG. Two metal layers 7 formed through the silicon oxide film 6 may be provided. Two or more metal layers 7 may be provided.

  In the first to fifth embodiments, the example in which the width of the metal layer is configured to be smaller than the width of the embedded electrode has been described. However, the present invention is not limited to this, and the width of the metal layer and the embedded layer are embedded. You may comprise so that the width | variety of an electrode may become the same magnitude | size.

  Moreover, although the example which comprised the metal layer from W (tungsten) was shown in the said 1st-5th embodiment, this invention is not restricted to this but comprises from electroconductive materials other than W (tungsten). Also good. For example, the metal layer may be made of Ti (titanium) or a laminated structure material of Ti and TiN. Further, instead of the metal layer, a conductive layer such as conductive polysilicon may be formed inside the trench.

  In the first to fifth embodiments, the embedded electrode is made of p-type polysilicon. However, the present invention is not limited to this, and a metal or the like may be used in addition to p-type polysilicon. it can. For example, as a metal material used for the embedded electrode, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), nickel (Ni), molybdenum (Mo), cobalt (Co), silver ( Ag), platinum (Pt), lead (Pb) and the like. Moreover, these metal materials can be used 1 type or in combination of 2 or more types. Furthermore, both polysilicon and metal materials may be included.

  In the first to fifth embodiments, the example in which the interlayer insulating film formed on the upper surface of the buried electrode is formed so that the upper surface is flush with the upper surface of the epitaxial layer is shown. The invention is not limited to this, and the interlayer insulating film formed on the upper surface of the buried electrode may be formed so that the upper surface protrudes from the upper surface of the epitaxial layer, or the upper surface is below the upper surface of the epitaxial layer. You may form so that it may be located (inside a trench).

Moreover, in the said 1st-5th embodiment, although it comprised so that the groove depth of a trench might become smaller than the thickness of an n-type epitaxial layer, this invention is not limited to this, A trench penetrates an n-type epitaxial layer. Then, it may be configured to reach the n ⁺ type silicon substrate. That is, the trench depth may be set to about 12 μm.

  In the first and fifth embodiments, the metal layer is formed in each of the plurality of trenches. However, the present invention is not limited to this, and the metal layer is formed in all of the plurality of trenches. It does not have to be.

It is sectional drawing which showed the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating operation | movement of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating operation | movement of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention shown in FIG. It is sectional drawing which showed the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing for demonstrating operation | movement of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing for demonstrating operation | movement of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which showed the structure of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing for demonstrating operation | movement of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing which showed the structure of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing which showed a part of structure of the semiconductor device by the modification of this invention. It is sectional drawing which showed the structure of the conventional MOSFET (semiconductor device) disclosed by patent document 1. FIG.

Explanation of symbols

1 n ⁺ type silicon substrate (one conductivity type semiconductor layer)
2 n-type epitaxial layer (one conductivity type semiconductor layer)
3, 3a, 3b, 3c trench 4 silicon oxide film (third insulating film)
5 Embedded electrode 5a Embedded electrode (first embedded electrode)
5b Embedded electrode (second embedded electrode)
6 Silicon oxide film (first insulating film)
7 Metal layer (conductor layer)
8, 8a, 8b Interlayer insulating film (second insulating film)
9, 41 Source electrode 10 Drain electrode 11, 31, 42, 52 Channel (current path)
12, 12a, 12b, 12c, 12d Depletion layer 13 Inversion layer 20, 30, 40, 50, 60 Semiconductor device 41a Embedded portion (second embedded electrode)
51 p ⁺ type diffusion region (reverse conductivity type diffusion region)

Claims (13)

A semiconductor layer of one conductivity type having a plurality of trenches arranged at predetermined intervals from each other;
A plurality of embedded electrodes embedded in each of the plurality of trenches;
And a conductive layer capacitively coupled to the buried electrode by being formed in at least one of the plurality of trenches and disposed via a first insulating film above the buried electrode. A semiconductor device.   The semiconductor layer is configured such that each region between adjacent trenches serves as a current path, and each region between adjacent trenches is blocked by a depletion layer formed around the plurality of trenches. The current path is interrupted by being peeled off, while the current path is configured to be opened when at least part of the depletion layer formed around the trench disappears, The semiconductor device according to claim 1.   3. The semiconductor device according to claim 1, wherein the conductor layer is formed inside each of the plurality of trenches and is capacitively coupled to the buried electrode. 4. A second insulating film is formed on the upper surface of the conductor layer,
The semiconductor device according to claim 1, wherein the second insulating film is formed in the trench so that an upper surface thereof is flush with an upper surface of the semiconductor layer. A predetermined embedded electrode of the plurality of embedded electrodes is formed on the inner surface of the trench via a third insulating film,
The semiconductor device according to claim 1, wherein a thickness of the first insulating film is equal to or greater than a thickness of the third insulating film.   6. The semiconductor device according to claim 1, wherein a width of the conductor layer in an arrangement direction of the trench is smaller than a width of the embedded electrode.   The semiconductor device according to claim 1, wherein the conductor layer is made of a metal material.   The semiconductor device according to claim 7, wherein the conductor layer is made of at least one metal material selected from W, Ti, and TiN.   The plurality of trenches are formed in an elongated shape so as to extend parallel to each other in a direction parallel to the upper surface of the semiconductor layer and perpendicular to the arrangement direction of the trenches. Item 9. The semiconductor device according to any one of Items 1 to 8.   All the depletion layers formed around each of the plurality of trenches are blocked by the respective regions between the adjacent trenches, thereby blocking the current path, while being formed around each of the plurality of trenches. 10. The semiconductor device according to claim 2, wherein the current path is opened when all the depletion layers thus formed disappear. 10. The plurality of embedded electrodes are divided into two types, a first embedded electrode and a second embedded electrode to which a voltage is applied separately from each other,
Each region between the adjacent trenches is blocked by a depletion layer formed around all of the plurality of trenches, thereby blocking the current path, 10. The structure according to claim 2, wherein the current path is opened when a depletion layer formed around a trench in which the first embedded electrode is embedded disappears. The semiconductor device according to item.   12. The semiconductor device according to claim 11, wherein the second buried electrode is in Schottky contact with the semiconductor layer inside the trench. A diffusion region of a reverse conductivity type formed in each region between the adjacent trenches of the semiconductor layer and disposed at a predetermined interval with respect to the trench;
The depletion layer formed around each of the trench and the diffusion region is blocked around each region between the adjacent trenches, thereby blocking the current path, and formed around the trench. The semiconductor device according to claim 2, wherein the current path is opened when the depletion layer disappears.

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