JP2009016017A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which circuit scale for improving timing margin of output data is small and power consumption is less in synchronous burst read-out of a nonvolatile memory. <P>SOLUTION: The circuit includes a clock delay control part 10 having a clock delay control circuit 15 and a mode register 20, and a clock input buffer 40. The clock delay control circuit 15 controls data output timing of a data output part 30 by controlling delay of an external clock signal CLK' outputted from the clock input buffer 40 based on information corresponded to a frequency stored in the mode register 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit that controls synchronous burst read data of a nonvolatile memory, and more particularly to a semiconductor integrated circuit that controls data output timing of a data output unit.

  A fixed time relationship is defined between the clock signal and the output data in the synchronous burst reading of the nonvolatile memory. FIG. 3 is a pulse train showing the time relationship between the clock signal and the output data. In FIG. 3, the output data OutPutData must be determined after the burst access time tBA after the first external clock signal CLK rises. In addition, after the data is determined, the data must be held for the data holding time tBDH after the next external clock signal CLK rises.

  FIG. 4 is a standard table showing the relationship between the frequency of the external clock signal CLK, the burst access time tBA, and the data holding time tBDH. For example, when the clock frequency is 54 MHz, the maximum value of the burst access time tBA is 14.5 ns, and the minimum value of the data holding time tBDH is 4 ns. When the clock frequency is 108 MHz, the maximum value of the burst access time tBA is 7 ns, and the minimum value of the data holding time tBDH is 2 ns. Also shown are recommended latencies for each clock frequency.

  FIG. 5 is a block diagram showing a relationship between a data output unit and a clock signal in conventional synchronous burst reading. The external clock signal CLK is input to the clock input buffer 40 via the clock pad 50 of the memory chip. The external clock signal CLK output from the clock input buffer 40 is input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30. Pipeline data that has been burst read from the memory array 70 is controlled by the external clock signal CLK input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30, and from the data output pad 60 to the outside. It is taken out. The mode register 20 exists on the same memory chip, but is not related to the data output unit 30.

  FIG. 6 is a timing margin diagram showing output timing of output data. In FIG. 6, white circles indicate the burst access time tBA and the data holding time tBDH of the output data extracted from the data output pad 60 of FIG. 5 for each clock frequency. Usually, the maximum timing margin is obtained at the maximum clock frequency. Therefore, at the clock frequency of 108 MHz, the data holding time tBDH and the burst access time tBA are designed to come to an intermediate value 4.5 ns between the minimum value 2 ns of the data holding time tBDH and the maximum value 7 ns of the burst access time tBA. The maximum timing margin is obtained.

For this reason, when the clock frequency is lowered, for example, at 54 MHz, only a timing margin of 0.5 ns remains with respect to the minimum value 4 ns of the data holding time tBDH, and the system design of the memory becomes difficult. Patent Document 1 discloses a DLL circuit having a phase comparison circuit that compares phases of an internal clock and a delay clock and a variable delay addition circuit that adjusts a delay amount by a signal from the phase comparison circuit in a synchronous burst read operation. There is a statement that the timing of output data is optimized. However, since this DLL circuit has a large circuit scale, there is a problem that it is difficult to reduce the chip size and the power consumption is large.
JP 2005-228427 A

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor integrated circuit with a small circuit scale and low power consumption for improving a timing margin of output data in synchronous burst reading of a nonvolatile memory. It is to provide a circuit.

  A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit that controls data output timing of a data output unit in synchronous burst reading of a nonvolatile memory, and includes a clock delay control unit having a clock delay control circuit and a mode register, The clock delay control circuit includes an input buffer, and controls the delay of the external clock signal input from the outside and output from the clock input buffer based on the information associated with the frequency stored in the mode register. The data output timing of the data output unit is controlled.

  According to the semiconductor integrated circuit of the present invention, it is possible to provide a semiconductor integrated circuit with a small circuit scale and low power consumption for improving the timing margin of output data in synchronous burst reading of a nonvolatile memory. It is possible to suppress an increase in size and an increase in power consumption.

  Embodiments of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the relationship between the clock delay control unit and the data output unit of the present invention. In FIG. 1, an external clock signal CLK ′ output from the clock input buffer 40 is input to the clock delay control circuit 15 of the clock delay control unit 10, and information (others) associated with the frequency stored in the mode register 20. FIG. 5 shows that the delay is controlled based on the latency information signal and is input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30. Is different.

  When the clock frequency is 54 MHz, the clock delay control circuit 15 obtains a 4-cycle signal that is the latency information signal of FIG. 4 from the mode register 20 and delays the external clock signal CLK ′ output from the clock input buffer 40. The delayed clock signal DelayCLK is input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30. As a result, pipeline data burst-read from the memory array 70 is controlled, and the controlled pipeline data is taken out from the data output pad 60 as output data. As indicated by the black circles in FIG. 6, the data holding time tBDH and burst access time tBA of the output data are 6 between the minimum value 4 ns of the data holding time tBDH and the maximum value 14.5 ns of the burst access time tBA. .5 ns, and the timing margin on the data holding time tBDH side is improved.

  Similarly, when the clock frequency is 66 MHz, 83 MHz, or 108 MHz, the clock delay control circuit 15 obtains the 5, 6 and 8 cycles of the latency information signal of FIG. The delay of the external clock signal CLK ′ output from 40 is controlled and input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30. As a result, the data holding time tBDH and burst access time tBA of the output data fetched from the data output pad 60 are shifted to the maximum value side of the burst access time tBA as shown by the black circles in FIG. 6, and the data holding time tBDH The timing margin on the side has been improved.

  FIG. 2 is a block diagram of a clock delay control circuit of the clock delay control unit of the present invention. In FIG. 2, the clock delay control circuit 15 includes delay circuits 15-1 to 15-1, a selector 16, and a buffer 17. The delay circuits 15-1 to 15-3 are cascade-connected to each other, one end is connected to the output end of the clock input buffer 40, and the other end is connected to one input end of the selector 16. The other input terminal of the selector 16 is connected to the output terminal of the clock input buffer 40 and the connection nodes of the cascaded delay circuits 15-1 to 15-3. Further, the control terminal of the selector 16 is connected to the output terminal of the mode register 20, and the output terminal is connected to the input terminal of the buffer 17. The output terminal of the buffer 17 is connected to the burst counter 30-1 of the data output unit 30 and the input terminal of the data output driver 30-2.

  The selector 16 receives a latency information signal corresponding to the frequency of the external clock signal CLK ′ output from the clock input buffer 40 from the mode register 20 as a control signal. Based on this signal, one of the delayed clock signals DelayCLK having delays of 0 ns, 1.0 ns, 2.0 ns, and 3.0 ns is selected, and the burst counter 30-1 and the data output driver 30 are passed through the buffer 17. -2.

  Thus, the pipeline data read out in burst from the memory array 70 is input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30, and the external clock signal output from the clock input buffer 40 is output. The data holding time tBDH and burst access time tBA of the output data fetched from the data output pad 60 are shifted to the maximum value side of the burst access time tBA as in the case of the black circle in FIG. 6 under the control of CLK ′ or the delayed clock signal DelayCLK. In addition, the timing margin on the data holding time tBDH side can be improved. The clock delay control circuit 15 has a smaller circuit scale and lower power consumption than a conventional DLL circuit.

  As described above, according to the present invention, in synchronous burst reading of a nonvolatile memory, it is possible to provide a semiconductor integrated circuit with a small circuit scale that improves the timing margin of output data and low power consumption. It is possible to suppress an increase in chip size and an increase in power consumption.

The block diagram which shows the relationship between the clock delay control part and data output part of this invention. The block diagram of the clock delay control circuit of the clock delay control part by this invention. A pulse train showing the time relationship between the clock signal and output data. A standard table showing the relationship between the frequency of a clock signal, burst access time tBA, and data holding time tBDH. The block diagram which shows the relationship between the conventional data output part and a clock signal. The timing margin figure which shows the output timing of output data.

Explanation of symbols

10 Delay controller
15 Clock delay control circuit
15-1-3 delay circuit
16 selector
17 buffers
20 Mode register
30 Data output section
30-1 Burst counter
30-2 Data output driver
40 clock input buffer
50 clock pads
60 Data output pad
70 Memory array CLK External clock signal CLK ′ External clock signal output from buffer DelayCLK Delay clock signal OutPutData output data tBA Burst access time tBDH Data holding time

Claims (1)

A semiconductor integrated circuit for controlling data output timing of a data output unit in synchronous burst reading of a nonvolatile memory,
A clock delay control unit having a clock delay control circuit and a mode register, and a clock input buffer;
The clock delay control circuit controls the delay of the external clock signal input from the outside and output from the clock input buffer based on information associated with the frequency stored in the mode register. A semiconductor integrated circuit which controls data output timing of an output unit.

Images