JP2008108023A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make high performance and low power consumption compatible by using a memory element of a DDR type. <P>SOLUTION: A memory module 12 outputs a data signal 62 and a strobe signal 44 showing timing of the data signal 62 when reading data. A delay circuit 40 having an operating lower limit frequency and a delay circuit 42 not having the operating lower limit frequency delay the strobe signal 44 from the memory module 12. Delay times of the delay circuits 40 and 42 are almost a quarter cycle of the strobe signal 44. A selection circuit 50 follows an instruction from a control circuit 70 and selects one of a strobe signal 46 and a strobe signal 48. A flip-flop (FF) 54 follows an output of the selection circuit 50 and latches a data signal 62. An FF 60 follows an inverse value of an output of the selection circuit 50 and latches the data signal 62. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory controller, and more specifically to a memory controller that operates with low power consumption and can read data from a memory module at high speed.

  In recent years, functions that require high performance, such as high-speed response, high-speed continuous shooting performance, and long-time video shooting, are becoming indispensable for digital cameras and digital video cameras.

  Along with this, necessary performance has been achieved by increasing the clock frequency and mounting a double-data-rate (hereinafter abbreviated as DDR) type memory capable of high-speed memory access.

  However, in order to obtain high performance, the power consumption of the entire camera tends to increase. For digital cameras that require battery operation, an increase in power consumption is a major problem.

  Recently, a MobileDDR type memory without a Delay-Locked-Loop (hereinafter abbreviated as DLL) circuit that can reduce the power consumption of the memory while maintaining high performance without any restriction on the operating frequency band has been developed. .

  Patent Document 1 describes a technique for reducing power consumption by switching the clock frequency of a memory in accordance with the amount of transferred data and operating at a frequency lower than the normal operating frequency in a period in which data transfer is small. ing.

In Patent Document 2, in a DDR type memory, two types of DLL circuits having different operating frequency bands are mounted in the memory, and the DLL return path is properly used according to the supplied clock, thereby achieving high performance and low power consumption. It is described to achieve both.
JP 2000-307534 A JP 2004-355081 A

  When a DDR type memory is used to achieve the best performance, a highly accurate timing adjustment circuit is required on the receiving side. As a result, a highly accurate delay adjustment circuit such as a DLL circuit is required on the controller side. While the DLL circuit can adjust the delay amount with high accuracy following the input frequency, the frequency band that can be followed is limited. A large occupied area is required when incorporating the LSI. The DLL circuit is a device that is not suitable for reducing power consumption, for example, when it is desired to operate at a low clock frequency.

  An object of the present invention is to provide a memory controller that can achieve both high performance and low power consumption by using a DDR type memory element.

  In order to solve the above-described problems, a memory controller according to the present invention is a memory controller that controls a memory module that outputs a strobe signal indicating the timing of data together with a data signal in synchronization with an external clock during a data read period. A first delay circuit having an operation lower limit frequency that delays the strobe signal, a second delay circuit that delays the strobe signal and does not have an operation lower limit frequency, and the first and second delays. A selection unit that selects one of the outputs of the circuit, and a latch circuit that captures the data signal from the memory module in accordance with an output signal of the selection unit are provided.

  In the present invention, a first delay circuit having an operation lower limit frequency and a second delay circuit not having an operation lower limit frequency are prepared, and these outputs are appropriately selected to capture a data signal from the memory module. Therefore, both high performance and low power consumption can be achieved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a schematic block diagram of an embodiment of the present invention. The memory device 10 according to the present embodiment includes a memory module 12 made up of a mobile DDR-SDRAM (Synchronous Random Access Memory) that does not have a restriction on the lower limit frequency of operation and does not have a DLL. In addition, the memory module 12 includes a memory controller 14 that reads / writes data, and the control circuit 70 instructs the memory controller 14 to read data and read / write operation. When the memory device 10 is used for an image processing device, for example, image data to be processed is temporarily written in the memory device 10.

  The memory controller 14 outputs a clock signal 16, an inverted clock signal 18, and a command signal 20 such as a read command, a write command, and an address to the memory module 12. The memory controller 14 is connected to the memory module 12 by a bidirectional data bus 22 and a bidirectional strobe signal line 24.

  The clock generation circuit 30 of the memory controller 14 supplies a clock signal 16 having a predetermined frequency to the memory module 12 in accordance with an instruction from the control circuit 70 and simultaneously supplies an inverted clock signal 18 obtained by inverting the clock signal 16 by the inverter 32. . The clock generation circuit 30 also generates an internal clock signal 34 for a circuit in the memory controller 14 and supplies the internal clock signal 34 to flip-flops (hereinafter abbreviated as FF) 36, 38 and the like. The clock generation circuit 30 can change the frequency of the clock supplied to the memory module 12 and the frequency of the clock supplied to the FF 36 and the FF 38 in the memory controller 14 according to the required performance.

  The memory controller 14 includes a delay circuit 40 having an operation lower limit frequency and a delay circuit 42 having no operation lower limit frequency. The delay circuit 40 is composed of, for example, a DLL circuit. The delay circuit 42 is composed of delay buffers having the number of stages corresponding to the delay time. The delay circuit 40 delays the strobe signal 44 from the memory module 12 and outputs a strobe signal 46. The delay circuit 42 delays the strobe signal 44 and outputs a strobe signal 48. The selection circuit 50 selects one of the strobe signals 46 and 48 in accordance with an instruction from the control circuit 70.

  The strobe signal 52 selected by the selection circuit 50 is applied to the clock input terminal of the FF 54, and is applied to the clock input terminal of the FF 60 via the inverter 56. A data signal 62 read from the memory module 12 is applied to the data terminals of the FFs 54 and 60. The FF 54 captures the data signal 62 in synchronization with the rising edge of the strobe signal 52, and the FF 60 captures the data signal 62 in synchronization with the falling edge of the strobe signal 52. That is, the FFs 54 and 60 function as a latch circuit or a storage circuit for the data signal 62.

  The FF 36 captures the output data of the FF 54 in synchronization with the clock 34 from the clock generation circuit 30, and the FF 38 captures the output data of the FF 60 in synchronization with the clock 34 from the clock generation circuit 30.

  For simplification of the drawing, the FFs 36, 38, 54, and 60 are shown for one bit, but actually, they are composed of a plurality of bits, and the plurality of bits are processed in parallel.

  As described above, the control circuit 70 controls the frequency of the clock generated by the clock generation circuit 30 and also controls the selection of the strobe signal by the selection circuit 50.

  A general relationship between the strobe signal 24 and the data signal 22 output from the memory module 12 will be described with reference to FIG.

  A data signal read from the memory module 12 to the bidirectional data signal line 22 changes in synchronization with a rising edge and a falling edge of a strobe signal on the bidirectional strobe signal line 24 (hereinafter referred to as a strobe signal 24).

  The memory controller 14 generates a signal 52 obtained by delaying the strobe signal 24 until the phase is shifted by about 90 degrees, and supplies the signal 52 to the FF 54 as a clock signal. Since the clock signal 52 rises at almost the center of the change point of the even-numbered data of the data signal 62, that is, the data D0 and D2, the FF 54 ensures the sufficient setup time Tsa and hold time Tha to ensure the data Incorporate

  Further, the inverter 56 generates a signal 58 obtained by inverting the clock signal 52 and supplies it to the FF 60 as a clock signal. Since the clock signal 58 rises at approximately the center of the odd-numbered data of the data signal 62, that is, the data D1 and D3, the FF 60 ensures sufficient setup time Tsb and hold time Thb to ensure the data Incorporate

  Thus, since the DDR type SDRAM can transfer two pieces of data in one cycle period, high-speed data transfer is possible.

  With reference to FIG. 3, the details of the timing adjustment in this embodiment between the strobe signal 24 and the data signal 22 output from the memory module 12 will be described.

  The data signal 22 output from the memory module 12 changes in synchronization with the rising edge and falling edge of the strobe signal 24.

  The delay circuit 40 constituted by a DLL circuit outputs a signal 46 whose phase is delayed by about 90 degrees from the strobe signal 24. The DLL circuit is less susceptible to variations in delay due to variations in operating voltage, ambient temperature, semiconductor process manufacturing, etc., and operates following the frequency of the input signal. Due to this characteristic, the delay circuit 40 outputs a signal 46 that is always delayed by a certain amount of phase with respect to the strobe signal 24.

  On the other hand, the delay circuit 42 constituted by a plurality of stages of delay buffers or the like similarly outputs a signal 48 whose phase is delayed by about 90 degrees from the strobe signal 24. However, since the delay circuit 42 is susceptible to variations in the delay amount due to operating voltage, ambient temperature, semiconductor process manufacturing variations, and the like, the delay amount of the delay circuit 42 is relatively smaller than the delay amount of the delay circuit 40. It is unstable.

  When the variation amount of the delay amount of the delay circuit 40 is Te1, and the variation amount of the delay amount of the delay circuit 42 is Te2, the relationship of Te1 <Te2 is established. However, Te1 is the amount of variation in the operating frequency band.

When the cycle of the operation clock is Tcyc,
Tcyc / 2−Te1 = Tsa + Tha> Ts (FF) + Th (FF) (1)
Tcyc / 2−Te2 = Tsb + Thb> Ts (FF) + Th (FF) (2)
The operating frequency 1 / Tcyc that satisfies the above becomes the respective limit maximum operating frequency. However, Ts (FF) is the setup time of FF, and Th (FF) is the hold time of FF.

When the maximum limit frequency of the delay circuit 42 is Tcyc_MAX2, the operation clock frequency is
Tcyc_MAX2 <Tcyc (3)
In the case of the high frequency 1 / Tcyc that satisfies the condition, the control circuit 70 causes the selection circuit 50 to select the output strobe signal 46 of the first delay circuit 40. As a result, the clock 52 generated from the strobe signal 46 is supplied to the FF 54, and the inverted clock 58 is supplied to the FF 60.

On the other hand, the operating clock frequency is
Tcyc_MAX2 ≧ Tcyc (4)
In the case of the low frequency 1 / Tcyc that satisfies the condition, the control circuit 70 causes the selection circuit 50 to select the strobe signal 48 output from the second delay circuit 42. As a result, the clock 52 generated from the strobe signal 48 is supplied to the FF 54, and the inverted clock 58 is supplied to the FF 60.

  In this embodiment, for simplification of explanation, it is assumed that there is no variation in delay time until the data signal 62 reaches the FF 54 and FF 60, and the duty ratio of the strobe signal is 50%. In practice, the maximum limit frequency is determined in consideration of variations in delay time due to variations in the operating voltage, ambient temperature, semiconductor process manufacturing, and wiring length between bits, and the strobe signal duty ratio. It goes without saying that you need to do it.

  The control circuit 70 determines the operation clock frequency of the memory device 10 and the frequency of the clock supplied to the memory module 12 according to the performance required for the memory device 10. The control circuit 70 controls the selection circuit 50 using the relationship of Expression (3) and Expression (4) according to the determined clock frequency. As described above, when the determined clock frequency satisfies Expression (4), the memory controller 14 follows the strobe signal 48 output from the second delay circuit 42 in order to reduce power consumption. Data output from the memory module 12 is captured. Conversely, when the determined clock frequency satisfies the expression (3) and further satisfies the operation lower limit frequency of the first delay circuit 40, the memory controller 14 outputs the strobe signal 46 output from the first delay circuit 40. The data output from the memory module 12 is captured.

Another switching criterion of the selection circuit 50 will be described. When the operation lower limit frequency of the first delay circuit 40 is 1 / Tcyc_MIN1, the control circuit 70 has an operation clock frequency of
Tcyc_MIN1 ≦ Tcyc (5)
In the case of a high frequency satisfying the above, the selection circuit 50 is made to select the strobe signal 46 output from the first delay circuit 40. As a result, the clock 52 generated from the strobe signal 46 is supplied to the FF 54, and its inverted clock 58 is supplied to the FF 60.

Conversely, the operating clock frequency is
Tcyc_MIN1> Tcyc (6)
In the case of a low frequency that satisfies the condition, the control circuit 70 causes the selection circuit 50 to select the strobe signal 48 output from the second delay circuit 42. As a result, the clock clock 52 generated from the strobe signal 48 is supplied to the FF 54, and the inverted clock 58 is supplied to the FF 60.

  The control circuit 70 determines the operation clock frequency of the memory device 10 and the frequency of the clock supplied to the memory module 12 according to the performance required for the memory device 10. The control circuit 70 controls the selection circuit 50 using the relationship of Expression (5) and Expression (6) according to the determined clock frequency. That is, as described above, when the determined clock frequency satisfies the expression (6) and satisfies the limit maximum frequency of the second delay circuit 42, power consumption is reduced. For this purpose, the memory controller 14 takes in the data output from the memory module 12 in accordance with the strobe signal 48 output from the second delay circuit 42. On the other hand, when the determined clock frequency satisfies Expression (5), the memory controller 14 takes in the data output from the memory module 12 in accordance with the strobe signal 46 output from the first delay circuit 40.

It is a schematic block diagram of one Example of this invention. It is a timing chart of the read timing from DDR-SDRAM. It is a detailed timing chart of a present Example.

Explanation of symbols

10: Memory device 12: Memory module 14: Memory controller 16: Clock signal 18: Inverted clock signal 20: Command signal 22: Bidirectional data bus (data signal)
24: Bidirectional strobe signal 30: Clock generation circuit 32: Inverter 34: Internal clock line 36, 38: FF
40: delay circuit 42: delay circuit 44: strobe signal 46: strobe signal 48 output from delay circuit 40: strobe signal output from delay circuit 42: selection circuit 52: strobe signal 54 output from selection circuit 50 : FF
56: Inverter 58: Inverted strobe signal 60: FF
62: Data signal

Claims (5)

A memory controller that controls a memory module that outputs a strobe signal indicating a timing of the data together with a data signal in synchronization with an external clock during a data reading period;
A first delay circuit (40) having an operating lower limit frequency for delaying the strobe signal;
A second delay circuit (42) that delays the strobe signal and does not have an operating lower limit frequency;
Selecting means (50) for selecting one of the outputs of the first and second delay circuits;
A latch circuit (54, 60) for fetching the data signal from the memory module according to the output signal of the selection means
And a memory controller.   2. The memory controller according to claim 1, wherein the data signal is synchronized with a rising edge and a falling edge of the strobe signal.   3. The memory controller according to claim 1, wherein the first delay circuit includes a DLL (Delay-Locked-Loop) circuit.   The memory controller according to claim 1, wherein the second delay circuit does not include a DLL (Delay-Locked-Loop) circuit.   The selection means selects the output of the first delay circuit when the frequency of the external clock is higher than a predetermined frequency, and selects the output of the second delay circuit when the frequency of the external clock is equal to or lower than the predetermined frequency. The memory controller according to claim 1, wherein the memory controller is selected.

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