JPH10247387A - Clock synchronization type semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change over the latency corresponding to frequencies of a CPU using a semiconductor memory, by connecting in series two registers to the next stage of a sense amplifier and making it possible to change with a switching mechanism the number of registers making data outputted from the sense amplifier pass through. SOLUTION: The next stage of a sense amplifier 3 is provided with registers 4, 5, and switches 8, 9, 10, and when the switch 8 is turned on, a data signal outputted from the sense amplifier 3 is inputted to an output buffer 6 via the registers 4 and 5, and latency 4 is set. When the switch 9 is turned on, the data signal outputted from the sense amplifier 3 inputted to the output buffer 6 via the register 5, and latency 3 is set. When the switch 10 is turned on, the data signal outputted from the sense amplifier 3 is directly inputted to the output buffer 6, and a test mode is set for measuring a reading rate for the data from a memory cell 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock synchronous semiconductor memory.

[0002]

2. Description of the Related Art In a clock synchronous semiconductor memory, C
After the address signal is input from the PU and the reference clock cycles by a predetermined number, data is continuously output from the memory cells. The above read timing is generally called latency. The case where data is continuously output in the third cycle of the reference clock is referred to as latency 3. The value of the latency is the CP using the semiconductor memory.
The processing capacity of U, more specifically, is determined by the operating frequency. Conventionally, latency 3 has been common. However, when the operating frequency of the CPU increases from 100 MHz to 200 MHz, for example, with the increase in the processing performance of the CPU, the period of three clock cycles becomes shorter than the time required to read data from the memory cell. I will. For this reason, in a CPU or the like having a high operating frequency, a latency of 4 is required in order to increase the response time. Even if CPUs have the same operating frequency, there are three types and four types of latency required depending on the manufacturer and the type.

[0003]

In the conventional clock-synchronous semiconductor memory, the above-mentioned latency is fixed. For this reason, C having a high operating frequency as described above
When a PU or the like is used, a semiconductor memory designed with a latency of 4 must be newly prepared. As described above, the conventional clock-synchronous memory has a problem that it lacks versatility. On the other hand, for example, it is conceivable to set a different latency by delaying a memory cell selection signal output from an address decoder to a memory cell. However, if the cycle of the internal clock becomes short, it becomes difficult to control so as to output a data signal accurately in four clock cycles. Therefore, the semiconductor memory having such a configuration cannot support a CPU having a high operating frequency.

An object of the present invention is to provide a clock-synchronous semiconductor memory which is more versatile.

[0005]

A first clock-synchronous semiconductor memory of the present invention reads data at a designated address from a memory cell in synchronization with a clock signal inputted from the outside, and reads this data from a sense amplifier. In a semiconductor memory that reads data via a register and an output buffer after amplification by:
A first register for receiving data output from the sense amplifier and outputting the data in response to an input of a first clock signal obtained by delaying the externally input clock signal by a predetermined time by a delay circuit; A second register connected to the first register and outputting data to an output buffer in response to the input of the clock signal naturally delayed by an internal circuit, wherein the data output from the sense amplifier is supplied to the first register; A switch circuit for switching to which of the second registers the signal is input.

A second clock-synchronous semiconductor memory of the present invention is the first clock-synchronous semiconductor memory, wherein the switch circuit further outputs data output from a sense amplifier directly to an output buffer. And a circuit for outputting to

A third clock-synchronous semiconductor memory according to the present invention is the first or second clock-synchronous semiconductor memory, wherein the switch circuit includes a transfer gate, and controls the transfer gate. It has a signal input terminal.

The fourth clock-synchronous semiconductor memory of the present invention synchronizes with a clock signal input from the outside,
Read the data at the specified address from the memory cell,
In a semiconductor memory in which data is read out through a register and an output buffer after amplifying the data by a sense amplifier, a mode in which data output from the sense amplifier is passed as it is by a switching signal input from the outside as the register is used as the register. A first register having a mode switching mechanism for outputting the data in response to an input of a first clock signal obtained by delaying the externally input clock signal by a predetermined time by a delay circuit;
A second register connected to the register and outputting data to an output buffer in response to the input of the clock signal naturally delayed by an internal circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock-synchronous semiconductor memory according to the present invention has two stages of registers connected in series after a sense amplifier, and switches the number of registers to be used by switching a switch to reduce latency. It has a configuration that can be changed. Hereinafter, the first to fifth embodiments of the semiconductor memory having this feature will be described in order.

(1) First Embodiment FIG. 1 is a schematic diagram of a position example showing a relationship between an arithmetic processing unit (hereinafter referred to as a CPU) 100 and a clock synchronous semiconductor memory 200 used by the CPU 100. . The CPU 100 stores the CP in the memory 200.
In addition to outputting a reference clock signal CLK0 according to the operating frequency of U, when reading and writing data, the memory outputs a control signal CS for controlling access to the memory and an address signal Add. As will be described later, the clock synchronous semiconductor memory 200 stores the address signal Ad specified by the CPU.
The data stored in the physical address of the memory cell array specified by d is read, and the data amplified to a predetermined level by the sense amplifier is output to the CPU 100 as an output data signal D _out .

FIG. 2 shows a clock synchronous type semiconductor memory 2.
FIG. 2 is a block diagram showing a configuration of a 00. Semiconductor memory 20
0 denotes a configuration in which two registers 4 and 5 are connected in series to the next stage of the sense amplifier 3 and the number of registers through which data output from the sense amplifier 3 is passed by the switching mechanisms 8, 9 and 10 can be changed. adopt. This makes it possible to switch the latencies 3 and 4 according to the operating frequency of the CPU using the semiconductor memory. The address decoder 1 receives a control signal CS and an address signal Add. The address decoder 1
In response to input of a predetermined pulse signal of control signal CS, a memory cell selection signal that specifies a physical address in memory cell 2 specified based on address signal Add is output. The memory cell 2 outputs data written in the cell selected by the input memory cell selection signal to the sense amplifier 3. The sense amplifier 3 amplifies and outputs the data signal read from the memory cell 2. Registers 4 and 5 and switches 8, 9 and 10 are provided at the next stage of the sense amplifier 3. When the switch 8 is turned on, the data signal output from the sense amplifier 3 is output to the output buffer 6 via the registers 4 and 5.
And the latency 4 is set. When the switch 9 is turned on, the data signal output from the sense amplifier 3 is input to the output buffer 6 via the register 5,
Latency 3 is set. When the switch 10 is turned on, a data signal output from the sense amplifier 3 is directly input to the output buffer 6, and a test mode for measuring a reading speed of data from the memory cell 2 is set.
The register 4 is controlled by the clock signal CLK1. The clock signal CLK1 is a signal obtained by delaying the reference clock signal CLK0 determined by the operating frequency of the CPU 100 by the delay circuit 7. When setting the latency 4, the register 4 outputs a data signal output from the sense amplifier 3 in synchronization with the clock signal CLK1 in the third cycle. The register 5 is controlled by the clock signal CLK2. The clock signal CLK2 is
The clock signal CLK0 is a signal naturally delayed in the circuit. When setting the latency 4, the register 5 outputs the input data in synchronization with the clock signal CLK2 in the fourth cycle. Latency 3
When the register 5 is set, the register 5 outputs the input data in synchronization with the clock signal CLK2 in the third cycle after the predetermined control signal CS is input.
The output buffer 6 outputs a data signal directly input from the register 5 or the sense amplifier 3 to the CPU 100 as an output data signal D _out .

FIG. 3 is a time chart showing the state of each signal and data signal when the latency 9 is set by turning on the switch 9 in the semiconductor memory 200 having the configuration shown in FIG. The top row is CPU
The reference clock signal CLK0 whose period is determined by the operation frequency of 100 is shown. In the case of this example, the reference clock CLK0
Is 9 ns. When data is read in a state where the latency 3 is set, the semiconductor memory 20
0 outputs data in the third cycle of the reference clock signal CLK0. The CPU 100 generates the reference clock signal C
With the output of the signal a1 in the first cycle of LK0,
A predetermined control signal C for the address decoder 1
And outputs an address signal Add (= Ai). Address decoder 1 outputs a memory cell selection signal to memory cell 2. The memory cell 2 outputs the data written to the physical address selected by the selection signal to the sense amplifier 3. The sense amplifier 3
The input data is amplified and output. After the address signal Add is input to the address decoder 1, the memory cell 2
The delay time D1 required until the selection signal is output to
5 ns, after the selection signal is input to the memory cell 2,
The delay time D2 required until data is output from the sense amplifier 3 is 5 ns. These delay times D1 and D2
Is determined by the characteristics of the address decoder 1 and the memory cell 2, respectively. When the switch 9 is turned on, the data output from the sense amplifier 3 is directly transferred to the register 5.
Is input to The register 5 has a reference clock signal CL
K0 is a clock signal CLK naturally delayed by an internal circuit
2 is input. The delay time D3 of the clock signal CLK2 with respect to the reference clock signal CLK0 is 2.5 ns. This delay time D3 is determined by the circuit configuration of the semiconductor memory 200. Further, the setup time S1 required from the input of data to the register 5 from the sense amplifier 3 to the input of the clock signal CLK2 in the third cycle is 0.5 ns. The register 5 outputs the read data input from the sense amplifier 3 to the next output buffer 6 in synchronization with the input of the clock signal CLK2 in the third cycle. The clock signal C in the third cycle
Delay time D from input of LK2 until data is output
4 is 0.5 ns. The output buffer 6 to which the read data is input from the register 5 is driven for a predetermined time D5 (=
After a delay of 0.5 ns), the data is output data D
Output as _out . In the case of the latency 3, the data must be output from the output buffer 6 during the three cycles of the reference clock signal CLK0. CPU10
Minimum period T of reference clock signal input from 0
₃ is obtained as 5.751 ns in the following equation (1).

T ₃ = (D1 + D2 + S1 + D4 + D5) / 2 = (5 + 5 + 0.5 + 0.5 + 0.5) /2=11.5/2=5.751 When the latency 3 is set, in the semiconductor memory 200 having the above configuration, the maximum value is obtained. Can cope with the input of the reference clock signal CLK0 up to f = 1 / T ₃ ≒ 174 MHz.

As described above, in the case of the latency 3, it can correspond to the input of the reference clock signal CLK0 up to 174 MHz, but the operating frequency of the CPU in recent years has become 200 MHz or more. When a CPU having such an operating frequency is used, the latency 4
Is required. FIG. 4 is a time chart showing states of signals and data when the latency 8 is set by turning on the switch 8 in the semiconductor memory 200 having the configuration shown in FIG. The top stage shows a reference clock signal CLK0 determined by the drive frequency of the CPU 100 using the semiconductor memory 200. In the case of this example, the cycle of the reference clock signal CLK0 is 5 ns. When reading data in a state where the latency 4 is set, the semiconductor memory 200 uses the reference clock signal C
Data is output in the fourth cycle of LK0. CPU1
00 outputs a predetermined control signal CS to the address decoder 1 and an address signal Add (= Ai) in response to the output of the signal a1 in the first cycle of the reference clock signal CLK0. Address decoder 1 outputs a predetermined memory cell selection signal to memory cell 2. The memory cell 2 outputs the data written to the physical address selected by the selection signal to the sense amplifier 3. The sense amplifier 3 amplifies and outputs data read from the memory cell 2. Delay time D10 required after the address signal Add is input to the address decoder 1 and the selection signal is output to the memory cell 2
Is 5 ns, and the delay time D11 required until data is output from the sense amplifier 3 after the selection signal is input to the memory cell 2 is 5 ns. This delay time D10
And D11 are determined by the characteristics of the address decoder 1 and the memory cell 2, respectively.
It does not change with the frequency of K0. The clock signal CLK1 delayed by the time D12 (= 5.5 ns) by the predetermined delay circuit 7 is input to the register 4. The delay time D12 by the delay circuit 7 is longer than a natural delay time (about 0.5 ns) generated in the circuit, and may be set in accordance with the timing at which data is output from the sense amplifier 3. The register 4 outputs the read data input from the sense amplifier 3 to the register 5 at the next stage in synchronization with the clock signal in the third cycle. Semiconductor memory 20
In the case of 0, the setup time S10 from when data is input to the register 4 to when the clock signal CLK1 in the third cycle is input to the register 4 is 0.5 ns.
The delay time D13 from when data is output from the register 4 to the register 5 in synchronization with the clock signal CLK1 in the third cycle is 0.5 ns. This delay time D1
3 is determined by the characteristics of the register 4. The register 5 receives the clock signal CLK2 obtained by naturally delaying the reference clock signal CLK0 by an internal circuit. The delay time D14 of the clock signal CLK2 with respect to the reference clock signal CLK0 is 2.5 ns. This delay time D14
Is determined by the circuit configuration of the semiconductor memory 200. Further, the setup time S11 required from the input of data to the register 5 from the register 4 to the input of the clock signal CLK2 in the fourth cycle is 0.5 ns. The register 5 stores the clock signal CLK in the fourth cycle.
2, the read data input from the register 4 is output to the output buffer 6 at the next stage. The delay time D15 until data is output from the register 5 in synchronization with the input of the clock signal CLK2 in the fourth cycle is 0.5 ns. This delay time D15 is determined by the characteristics of the register 5. The output buffer 6 to which the read data has been input from the register 5 outputs the data as output data D _out after a delay of a predetermined time D16 (= 0.5 ns). In the case of latency 4, data must be output from the output buffer 6 in the fourth cycle of the reference clock signal CLK0. The minimum period T ₄ of the reference clock signal input from the CPU 100 is 4.15n in the following equation (2).
s is required.

T ₄ = (D10 + D11 + S10 + D13 + S11 + D15 + D16) / 3 = (5 + 5 + 0.5 + 0.5 + 0.5 + 0.5 + 0.5) /3=12.5/3=4.15 In the semiconductor memory 200 having the above configuration, f = at most. 1 / T
₄ It can correspond to the input of the reference clock signal CLK0 up to @ 240 MHz.

In the conventional semiconductor memory, one register is provided between the sense amplifier and the output buffer. Here, for comparison, a register is provided between an address decoder and a memory cell of a conventional semiconductor memory, and a latency of 4 is provided.
Is considered. FIG. 5 is a diagram showing a configuration of a semiconductor memory 300 of a comparative example. As shown, the semiconductor memory 300 is characterized in that a register 302 is interposed between an address decoder 301 and a memory cell 303 of a conventional semiconductor memory. The data output through the memory cell 303 is amplified by the sense amplifier 304 and then amplified by the register 305 and the output buffer 3.
06 is output. Registers 302 and 305 respectively have clock signals CLK3 and CLK obtained by naturally delaying reference clock signal CLK0 by an internal circuit.
4 is input. FIG. 6 shows that the semiconductor memory 300 is
5 is a time chart of signals and data when a latency of 4 is realized by connecting to a PU 100. The top row shows a reference clock signal CLK0 determined by the drive frequency of the CPU 100 using the semiconductor memory 300. In the case of this example, the cycle of the reference clock signal CLK0 is 5
ns. The CPU 100 outputs the reference clock signal CLK0
Of the control signal CS to the address decoder 301 in response to the output of the signal a1 in the first cycle of
And outputs an address signal Add (= Ai). The address decoder 301 outputs a predetermined memory cell selection signal to the register 302. Here, after an address signal is input to the address decoder 301, a delay time D required for outputting a selection signal to the register 302 is calculated.
20 is 5 ns, which is the same as the delay time D10 in the semiconductor memory 200. The register 302 outputs a memory cell selection signal to the memory cell 303 in synchronization with the clock signal CLK3 in the third cycle input with a natural delay D21 (= 3 ns) in the circuit. This delay time D21 corresponds to the setup time S10 in the semiconductor memory 200. The delay time D22 (= 0.5 ns) from receiving the clock signal CLK3 in the third cycle to outputting data from the register 302 is the same as the delay time D13 in the semiconductor memory 200. The memory cell 303 outputs the data written to the physical address selected by the selection signal to the sense amplifier 304. The sense amplifier 304 amplifies and outputs data read from the memory cell 303. After the selection signal is input to the memory cell 303, the delay time D23 required until data is output from the sense amplifier 304 is 5 ns.
Is the same as the delay time D11. Register 305
Is the delay time D synchronized with the third cycle clock signal.
After 24 (= 0.5 ns), the read data input from the sense amplifier 304 is output to the output buffer 306. This delay time D24 is the same as that of the semiconductor memory 200.
Is the same as the delay time D15. The output buffer 6 to which the read data has been input is at a predetermined time D25 (=
After a delay of 0.5 ns), the data is output data D
Output as _out . The delay time D25 is the same as the delay time D16 in the semiconductor memory 200.
In the case of the latency 4, the output buffer 306 outputs the reference clock signal CLK0 as in the case of the semiconductor memory 200.
Data must be output in the cycle. In this comparative example, the reference clock signal minimum period T _'4, which is input from the CPU100 is calculated as 5ns the following equation 3.

T ′ ₄ = (D20 + D21 + D22 + D23 + S20 + D24 + D25) / 3 = (5 + 3 + 0.5 + 5 + 0.5 + 0.5 + 0.5) / 3 = 15/3 = 5 In the semiconductor memory 300 of the comparative example, f = 1 / max.
T ' ₄基準 Reference clock signal CLK0 up to 200 MHz
It can only respond to the input of. This is because, in the semiconductor memory 300 of the comparative example, the clock signal CLK3 input to the register 302 has a natural delay (D21
= 3 ns), the delay time of the delay circuit 7 can be adjusted in accordance with the timing at which data is read from the sense amplifier 3 in the semiconductor memory 200 of the first embodiment. 2.5 ns
This is because it can be shortened. From the above, it can be understood that the semiconductor memory 200 of the present invention can be used in synchronization with a CPU having a higher operating frequency, as well as the latency value can be switched.

(2) Second Embodiment FIG. 7 shows a second embodiment of a clock synchronous semiconductor memory.
FIG. 3 is a block diagram showing a configuration of a semiconductor memory 400 that is a. The semiconductor memory 400 is used by the CPU 100 like the semiconductor memory 200. The same components as those of the semiconductor memory 200 are denoted by the same reference numerals,
The duplicate description here is omitted. The semiconductor memory 400 includes:
The input destination of the data output from the sense amplifier 3 is switched using a switch mechanism including the transfer gates 43 and 44 and the inverter 48 in accordance with the LATENCY signal output from the CPU 100. L
When the ATENCY signal is “L”, the transfer gate 43 is turned on, the data output from the sense amplifier 3 is output to the output buffer 6 via the registers 4 and 5, and the latency 4 is set. Also, LATEN
When the CY signal is “H”, the transfer gate 44 is turned on, and the data output from the sense amplifier 3 is
The data is output to the output buffer 6 via the register 5 and the latency 3 is set. Thus, the semiconductor memory 400
In, the latency value can be changed as needed by switching the LATENCY signal. The register 4 is controlled by the clock signal CLK1 as in the case of the semiconductor memory 200. Clock signal CLK
1 is a signal obtained by delaying the reference clock signal CLK0 determined by the operating frequency of the CPU 100 by the delay circuit 7. The register 5 is controlled by the clock signal CLK2. The clock signal CLK2 is the clock signal CLK
0 is a signal naturally delayed in the circuit. When setting the latency 4, the register 5 outputs the input data in synchronization with the clock signal CLK2 in the fourth cycle. When the latency 3 is set, the register 5 outputs the input data in synchronization with the third cycle clock signal CLK2 after the predetermined control signal CS is input. The output buffer 6
After delaying the data signal directly input from register 5 or sense amplifier 3 by a predetermined time, output data signal D
Output to the CPU 100 as _out . Note that the flow of signals and data at the time of setting the latencies 3 and 4 is the same as that of the semiconductor memory 200, and a duplicate description will be omitted.

(3) Third Embodiment FIG. 8 shows a third embodiment of a clock synchronous semiconductor memory.
1 is a diagram showing a configuration of a semiconductor memory 500 which is a. The semiconductor memory 500 employs a configuration in which the latency 3 or 4 is set alternatively by bonding to the _Vcc power supply pad 70 or the GND pad 72 and fixing the value of the LATENCY signal during the chip assembly process. It is characterized by. The semiconductor memory 500 is used by the CPU 100 like the semiconductor memory 200. The same components as those of the semiconductor memory 200 are denoted by the same reference numerals, and the description thereof will not be repeated. The semiconductor memory 500 switches the input destination of the data output from the sense amplifier 3 by using a switching mechanism including the transfer gates 43 and 44 and the inverter 48, similarly to the semiconductor memory 400. In the case of the semiconductor memory 400, the pad 71 is bonded to the _Vcc power supply pad 70 or the GND pad 72 provided on the memory chip at the time of assembling the memory chip, and the LA 71
The value of the TENCY signal is set alternatively. When the pad 71 is connected to the _Vcc power supply pad 70, the LATENCY signal is fixed at "H" and the transfer gate 44 is turned on. As a result, data output from the sense amplifier 3 is output to the output buffer 6 via the register 5, and the latency 3 is set. When the pad 71 is bonded to the GND pad 72, L
The ATENCY signal is fixed at “L”, and the transfer gate 43 is turned on. This makes sense amplifier 3
The output data is output to the output buffer 6 via the registers 4 and 5, and the latency 4 is set. Note that the flow of signals and data at the time of setting the latencies 3 and 4 is the same as that of the semiconductor memory 200, and a duplicate description will be omitted.

(4) Fourth Embodiment FIG. 9 shows a fourth embodiment of a clock synchronous semiconductor memory.
FIG. 3 is a block diagram showing a configuration of a semiconductor memory 600 that is a. The semiconductor memory 600 is used by the CPU 100, like the semiconductor memory 200. The same components as those of the semiconductor memory 200 are denoted by the same reference numerals, and the description thereof will not be repeated. In the semiconductor memory 600, when the latency 3 is set, the value of the clock signal CLK1 'for controlling the register 4 is fixed to "H" or "L", and data input from the sense amplifier 3 passes through the register 4 as it is. It is characterized in that a configuration of inputting to the register 5 is adopted. The clock signal CLK1 and the LATENCY signal output from the CPU 100 are input to the AND gate 86 whose output terminal is connected to the clock signal input terminal of the register 4. The clock signal CLK1 is a signal obtained by delaying the reference clock signal CLK0 by the delay circuit 7 used in the semiconductor memory 200. When setting the latency 3, the CPU 100 sets “
When the latency 4 is set, an "H" LATENCY signal is output. When the latency 3 is set, the "L" clock signal is input to the clock signal input terminal of the register 4 from the AND gate 86. In this case, the register 4 outputs the input data as it is to the next-stage register 5. When the latency 4 is set, the clock signal input terminal of the register 4 receives the clock from the AND gate 86. The signal CLK1 is directly input as the clock signal CLK1 '.
The control contents of the signal after the ENCY signal is switched are the same as those of the semiconductor memory 200 described above.
The duplicate description here is omitted.

[0018]

According to the first clock synchronous type semiconductor memory of the present invention, two registers are connected in series at the next stage of the sense amplifier, and the number of registers for passing data output from the sense amplifier by the switching mechanism is provided. Is adopted. This makes it possible to switch the latencies 3 and 4 according to the operating frequency of the CPU using the semiconductor memory.

In the second clock-synchronous semiconductor memory of the present invention, the latency value can be changed by switching the control signal input to the input terminal by the CPU using the semiconductor memory.

In the third clock-synchronized semiconductor memory of the present invention, the control terminal of the transfer gate is connected to the power supply terminal or the ground terminal of the semiconductor memory, so that the latency value can be set alternatively. it can.

According to the fourth clock synchronous semiconductor memory of the present invention, the value of the latency can be set alternatively by a switching signal input from the outside.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an arithmetic processing device and a clock synchronous semiconductor memory used by the arithmetic processing device.

FIG. 2 is a block diagram showing a configuration of a semiconductor memory 200 which is an embodiment of a clock synchronous semiconductor memory.

FIG. 3 is a time chart showing states of each signal and a data signal when a latency 3 is set.

FIG. 4 is a time chart illustrating states of signals and data when a latency of 4 is set.

FIG. 5 is a diagram showing a configuration of a semiconductor memory of a comparative example.

FIG. 6 is a time chart illustrating states of signals and data when a latency of 4 is set in the semiconductor memory of the comparative example.

FIG. 7 is a block diagram illustrating a configuration of a semiconductor memory according to a second embodiment of the clock synchronization type semiconductor memory;

FIG. 8 is a block diagram showing a configuration of a semiconductor memory according to a third embodiment of the clock synchronous semiconductor memory;

FIG. 9 is a block diagram showing a configuration of a semiconductor memory according to a fourth embodiment of the clock synchronization type semiconductor memory;

[Explanation of symbols]

1,301 address decoder, 2,302 memory cell, 3,303 sense amplifier, 4, 5, 302, 30
5 registers, 6,306 output buffers, 7 delay circuits, 43, 44, 63, 64 transfer gates,
48, 68 inverters, 70, 71, 72 pads,
86 AND gate, 100 CPU, 200, 30
0,400,500,600 Semiconductor memory

Claims (4)

[Claims] 1. A semiconductor for reading data at a designated address from a memory cell in synchronization with a clock signal input from the outside, amplifying the data by a sense amplifier, and then reading the data via a register and an output buffer. In the memory, data output from a sense amplifier is input as the register, and the data is output in response to an input of a first clock signal obtained by delaying a clock signal input from the outside by a predetermined time by a delay circuit. And a second register connected to the first register and outputting data to an output buffer in response to the input of the clock signal naturally delayed by an internal circuit, and output from a sense amplifier. A switch for switching between inputting the data to the first register or the second register. Clock synchronous type semiconductor memories, characterized in that it comprises a latch circuit. 2. The clock synchronous semiconductor memory according to claim 1, wherein said switch circuit is constituted by a transfer gate, and has an input terminal for a control signal of said transfer gate. Type semiconductor memory. 3. The semiconductor memory according to claim 1, wherein said switch circuit comprises a transfer gate, and a control terminal of said transfer gate is connected to a power terminal or a ground terminal of said semiconductor memory. A clock-synchronous semiconductor memory characterized in that: 4. A semiconductor for reading data at a designated address from a memory cell in synchronization with a clock signal inputted from the outside, amplifying the data by a sense amplifier, and then reading the data via a register and an output buffer. In the memory, as the register, a mode in which data output from the sense amplifier is passed as it is by a switching signal input from the outside, and a first clock obtained by delaying the clock signal input from the outside by a predetermined time by a delay circuit A first register having a mode switching mechanism for outputting the data in response to a signal input; and an output buffer connected to the first register and outputting data in response to the input of the clock signal naturally delayed by an internal circuit. And a second register for outputting the clock to the clock synchronous type. Semiconductor memory.