KR20090005954A - Semiconductor integrated circuit, and nonvolatile memory device and system including the same - Google Patents

Abstract

A semiconductor integrated circuit, and nonvolatile memory device and system including the same is provided to suppress power consumption increase by holding the increment of the chip size accompanied by the enlargement of the memory size. In a semiconductor integrated circuit, a semiconductor IC comprises a clock delay control part(10) and a clock input buffer(40). The clock delay control part comprises the clock delay control circuit(15) and a mode register(20). The external clock signal(CLK') outputted from the clock input buffer is inputted to the clock delay control circuit of the clock delay control part. The clock delay control part controls the delay of the external clock signal the delay-time information signal(Latency Info.) corresponding to the frequency stored in the mode register to the basis. The delay clock signal(Delay CLK) is inputted to the burst counter(30-1) and data output driver(30-2) of data output stage(30).

Description

A semiconductor integrated circuit, and a nonvolatile memory device and system including the same {SEMICONDUCTOR INTEGRATED CIRCUIT, AND NONVOLATILE MEMORY DEVICE AND SYSTEM INCLUDING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for controlling synchronous burst read data of a nonvolatile memory, and more particularly, to a semiconductor integrated circuit for controlling data output timing of a data output unit, and a non-volatile circuit including the same. A volatile memory device and system are described.

In the synchronous burst read operation of the nonvolatile memory, a constant time relationship is defined between the clock signal and the output data.

3 is a pulse train showing a time relationship between a clock signal and output data. In FIG. 3, in the case of output data, data must be confirmed after the burst access time tBA has elapsed since the first external clock signal CLK has risen. In addition, the data must be held for the data holding time tBDH after the data is confirmed and after the next external clock signal CLK is raised.

4 is a standard table showing the relationship between the frequency of the external clock signal CLK, the burst access time tBA, and the data holding time tBDH. Referring to FIG. 4, for example, when the clock frequency is 54 MHz, the maximum burst access time tBA is 14.5 ns, and the minimum data retention time tBDH is 4 ns. When the clock frequency is 108 MHz, the maximum value of the burst access time tBA is 7 ns and the minimum value of the data retention time tBDH is 2 ns. The specification table also shows the recommended latency of the delay for each clock frequency.

5 is a block diagram illustrating a relationship between a data output unit and a clock signal in a conventional synchronous burst read operation. Referring to FIG. 5, the external clock signal CLK is input to the clock input buffer 40 through the clock pad 50 of the memory chip. The external clock signal CLK output from the clock input buffer 40 is input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30. The pipeline data read from the memory array 70 by the burst read operation is transferred to the external clock signal CLK input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30. Controlled by the data output pad 60 to the outside. The mode register 20 is on the same memory chip but is not related to the data output unit 30.

6 is a timing diagram showing an output timing of output data. In Fig. 6, " ○ " represents a burst access time tBA and a data holding time tBDH of output data output from the data output pad 60 of Fig. 5 for each clock frequency. Typically, it is designed to obtain the maximum timing margin for the maximum clock frequency. Therefore, for a clock frequency of 108 MHz, the data retention time (tBDH) and burst access time (tNH) is 4.5 ns, which is intermediate between a minimum of 2 ns of data retention time (tBDH) and 7 ns of a maximum of burst access time (tBA). tBA) is designed to obtain the maximum timing margin.

For this reason, when the clock frequency is lowered, for example, at 54 MHz, only a timing margin of 0.5 ns is left for the minimum value 4 ns of the data retention time tBDH, which makes the system design of the memory difficult. Japanese Patent Laid-Open No. 2005-228427 discloses a DLL having a phase comparison circuit for comparing a phase between an internal clock and a delay clock during a synchronous burst read operation, and a variable delay addition circuit for adjusting a delay amount by a signal from a phase comparison circuit. There is a description to optimize the timing of output data by using a circuit. However, since the DLL circuit has a large circuit size, it is difficult to reduce the chip size, and power consumption is also a problem.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, a semiconductor integrated circuit having a small circuit size and low power consumption, which improves the timing margin of output data when a synchronous burst read of a nonvolatile memory is performed, and To provide a nonvolatile memory device and system comprising the.

In accordance with one aspect of the present invention, a semiconductor integrated circuit includes: a mode register in which a plurality of delay time information corresponding to a plurality of frequencies is stored; And a clock delay controller for generating a delay clock signal in response to an external clock signal and the delay time information, wherein the delay clock signal is used to adjust a timing margin of output data read during a synchronous burst read operation of a nonvolatile memory. It is characterized by.

In an exemplary embodiment, the apparatus may further include a clock input buffer configured to provide the external clock signal to the clock delay controller.

In this embodiment, the clock delay control unit includes a plurality of delay circuits for delaying the external clock signal by different delay amounts; A selector configured to select one of the plurality of delay circuits, an input terminal of which is connected to connection nodes of the delay circuits and a control terminal of which is connected to an output terminal of the mode register; And a buffer for outputting the output of the selected delay circuit as the delay clock signal.

In this embodiment, the delay circuits are cascaded from each other.

In this embodiment, the delay time information is applied to the control stage, characterized in that for controlling the selection of the selector.

According to the semiconductor integrated circuit of the present invention as described above, it is possible to provide a semiconductor integrated circuit having a small circuit size and low power consumption while improving the timing margin of output data during a synchronous burst read operation of a nonvolatile memory. Therefore, it is possible to suppress an increase in chip size and an increase in power consumption accompanying an increase in memory capacity.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The semiconductor integrated circuit of the present invention receives the external clock signal CLK 'from the clock input buffer and controls the delay of the external clock signal CLK' based on the delay time information signal for each frequency stored in the mode register. The delay clock signal Delay CLK generated by the clock delay control circuit is input to the burst counter of the data output section and the data output driver to improve the timing margin of the synchronous burst read data of the nonvolatile memory. The clock delay control circuit according to the present invention has a smaller circuit scale and smaller power consumption than the conventional DLL circuit. Therefore, the circuit scale and power consumption of such a semiconductor integrated circuit, and a nonvolatile memory device and a system including the same become smaller. Looking at the configuration of the present invention as described above in detail as follows.

1 is a diagram illustrating a relationship between a clock delay control unit 10 and a data output unit 30 according to the present invention. As will be described in detail below, the semiconductor integrated circuit according to the present invention includes a clock delay controller 10 and a clock input buffer 40, and the clock delay controller 10 includes a clock delay control circuit CLK Delay Control 15. And a mode register 20. In the present invention, a case where the semiconductor integrated circuit of the present invention is provided in the nonvolatile memory 100 performing a synchronous burst read operation will be described.

Referring to FIG. 1, an external clock signal CLK ′ output from a clock input buffer 40 is input to the clock delay control circuit 15 of the clock delay controller 10. The clock delay control unit 10 uses an external clock signal based on a delay time information signal (Latency Info.) That is additional information (for example, information on output strength, etc.) corresponding to a frequency stored in the mode register 20. Control the delay of (CLK '). The delay clock signal Delay CLK is input to the burst counter 30-1 of the data output unit 30 and the data output driver 30-2. Such a path for providing a clock signal in the present invention is different from the conventional configuration (for example, the configuration in FIG. 5).

The clock delay control circuit 15 receives four cycles of the delay time information signal of FIG. 4 from the mode register 20 when the clock frequency is 54 MHz, and outputs an external clock signal (outputted from the clock input buffer 40). CLK ') to control the delay. The delayed clock signal Delay CLK generated by the control of the clock delay control circuit 15 is input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30. As a result, the pipeline data PipeLineData read by the burst read operation from the memory array 70 is output from the data output pads 60 as output data.

As indicated by " " in FIG. 6, in the present invention, the data holding time tBDH and burst access time tBA of the output data are at least 4 ns of the data holding time tBDH and the burst access time tBA. Is set to 6.5 ns, which is a value between 14.5 ns maximum. Therefore, according to the configuration of the present invention as described above, the timing margin on the data holding time tBDH side is improved.

The clock delay control circuit 15 obtains signals of 5, 6 and 8 cycles, which are the delay time information signals of FIG. 4, from the mode register 20 similarly even when the clock frequencies are 66 MHz, 83 MHz, and 108 MHz. The delay of the external clock signal CLK 'output from the clock input buffer 40 is controlled. The clock delay control circuit 15 then outputs the delayed clock signal Delay CLK generated by controlling the delay of the external clock signal CLK 'and the burst counter 30-1 of the data output unit 30 and the data output. Input by the driver 30-2. As a result, the data holding time tBDH and the burst access time tBA of the output data output from the data output pad 60 are the maximum values of the burst access time tBA as indicated by " " Is shifted to improve the timing margin on the data holding time tBDH side.

2 is a block diagram of the clock delay control circuit 15 included in the clock delay control unit 10 of the present invention.

Referring to FIG. 2, the clock delay control circuit 15 includes a plurality of delay circuits 15-1, 15-2, and 15-3, a selector 16, and a buffer 17. . Delay circuits 15-1, 15-2 and 15-3 are cascaded to each other. One end of the delay circuits 15-1, 15-2, and 15-3 is connected to the output terminal of the clock input buffer 40 and the other end is connected to one of the plurality of input terminals of the selector 16. To the other input of the selector 16, the output of the clock input buffer 40 and the connection nodes of the cascaded delay circuits 15-1, 15-2, and 15-3 are respectively connected. The control terminal of the selector 16 is connected to the output terminal of the mode register 20, and the output terminal of the selector 16 is connected to the input terminal of the buffer 17. The output terminal of the buffer 17 is connected to the burst counter 30-1 of the data output unit 30 and the input terminal of the data output driver 30-2.

The plurality of delay circuits 15-1, 15-2, and 15-3 respectively delay the external clock signal CLK ′ provided from the clock input buffer 40 with different delay amounts (eg, 0 ns, 1.0). ns, 2.0 ns, 3.0 ns). The selector 16 receives a delay time information signal corresponding to the frequency of the external clock signal CLK 'output from the clock input buffer 40 from the mode register 20 as a control signal. Based on the signal, one of delay clock signals having a delay amount of 0 ns, 1.0 ns, 2.0 ns, and 3.0 ns is selected. The buffer 17 supplies the result selected by the selector 16 to the burst counter 30-1 and the data output driver 30-2 as a delay clock signal Delay CLK.

According to such a configuration, the pipeline data read from the memory array 70 by the burst read operation is delayed input to the burst counter 30-1 and the data output driver 30-2 of the data output unit 30. It can be controlled by the clock signal Delay CLK. As a result, the data holding time tBDH and burst access time tBA of the output data output from the data output pad 60 are shifted toward the maximum value of the burst access time tBA as indicated by " " As a result, the timing margin on the data holding time tBDH side can be improved. The clock delay control circuit 15 has a smaller circuit scale and a smaller power consumption than the conventional DLL circuit.

According to the above-described configuration, the timing margin of the output data during the synchronous burst read operation of the nonvolatile memory can be improved, and thus a semiconductor integrated circuit having a small circuit size and low power consumption can be provided. Therefore, it is possible to suppress an increase in chip size and an increase in power consumption accompanying an increase in memory capacity.

FIG. 7 is a view illustrating a schematic configuration of a nonvolatile memory 100 having a semiconductor integrated circuit and a memory system 1000 including the semiconductor integrated circuit according to the present invention shown in FIG. 1.

Referring to FIG. 7, the memory system 1000 may include a nonvolatile memory 100, such as a flash memory device, and a memory controller 200. The configuration of the nonvolatile memory 100 is substantially the same as that shown in FIG. Therefore, duplicate description thereof is omitted below. The memory controller 200 is configured to control overall operations of the nonvolatile memory 100. As described above, the pipeline data read by the burst read operation of the nonvolatile memory 100 is controlled by the delay clock signal Delay CLK generated from the clock input buffer 40 and the clock delay control unit 10. do. The data holding time tBDH and burst access time tBA of the output data output from the data output pad 60 are shifted to the maximum value of the burst access time tBA as indicated by " " . As a result, the timing margin on the data holding time tBDH side is improved. In the present invention, the clock delay control circuit 15 included in the clock delay control unit 10 has a smaller circuit scale and lower power consumption than the conventional DLL circuit. Therefore, the circuit scale and power consumption of the semiconductor integrated circuit of the present invention and the nonvolatile memory 100 including the same become smaller.

Meanwhile, the nonvolatile memory 100 illustrated in FIG. 7 may constitute a memory card and / or a memory card system. In this case, the memory controller 200 may be one of various interface protocols such as USB, MMC, PCI-E, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, SCSI, ESDI, and Integrated Drive Electronics (IDE). It may be configured to communicate with an external (eg, host) via one. As described above, the memory having the semiconductor integrated circuit of the present invention is a nonvolatile memory capable of retaining stored data even when power is cut off. Due to such characteristics, the nonvolatile memory 100 may be used as a data storage as well as a code storage for storing contents to be preserved regardless of power supply. The nonvolatile memory 100 can be used in cellular devices, PDA digital cameras, portable game consoles, and mobile devices such as MP3P, and in home applications such as HDTV, DVD, routers, and GPS.

8 illustrates a schematic configuration of a computing system 2000 including a nonvolatile memory 100 having a semiconductor integrated circuit according to the present invention.

Referring to FIG. 8, a computing system 2000 according to the present invention includes a modem 300 such as a nonvolatile memory 100, a memory controller 200, and a baseband chipset electrically connected to a bus 400. , Microprocessor 500, and user interface 600. The nonvolatile memory 100 shown in FIG. 8 has a structure substantially the same as that shown in FIG. In the nonvolatile memory 100, N-bit data (N is an integer of 1 or larger) to be processed / processed by the microprocessor 500 is stored through the memory controller 200.

When the computing system according to the present invention is a mobile device, a battery 700 for supplying the operating voltage of the computing system is additionally provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-explanatory to those who have learned. The memory controller 200 and the nonvolatile memory 100 may configure, for example, an SSD (Solid State Drive / Disk) that uses a nonvolatile memory to store data.

The nonvolatile memory 100 and / or the memory controller 200 according to the present invention may be mounted using various types of packages. For example, the nonvolatile memory 100 and / or the memory controller 200 according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), a plastic leaded chip carrier (PLCC). ), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level It may be implemented using packages such as Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), or the like. In an exemplary embodiment of the present invention, the memory cells constituting the nonvolatile memory 100 may be implemented using one of various cell structures having a charge storage layer. The cell structure having the charge storage layer may be a charge trap flash structure using a charge trap layer, a stack flash structure in which arrays are stacked in multiple layers, a flash structure without source-drain, a pin-type flash structure, and the like. It is obvious to those with ordinary knowledge in the field.

As described above, the optimum embodiment has been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a diagram illustrating a relationship between a clock delay control unit and a data output unit according to the present invention.

2 is a block diagram of a clock delay control circuit included in the clock delay control unit of the present invention.

3 is a pulse train showing a time relationship between a clock signal and output data.

4 is a standard table showing the relationship between the frequency of the external clock signal CLK, the burst access time tBA, and the data holding time tBDH.

5 is a block diagram illustrating a relationship between a data output unit and a clock signal in a conventional synchronous burst read operation.

6 is a timing diagram showing an output timing of output data.

FIG. 7 is a diagram illustrating a schematic configuration of a nonvolatile memory having a semiconductor integrated circuit and a memory system including the same according to the present invention illustrated in FIG. 1.

8 illustrates a schematic configuration of a computing system including a nonvolatile memory having a semiconductor integrated circuit according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: clock delay control unit 15: clock delay control circuit

20: mode register 30: data output unit

40: clock input buffer 100: nonvolatile memory

Claims (8)

A mode register in which a plurality of delay time information corresponding to a plurality of frequencies is stored; And A clock delay controller configured to generate a delayed clock signal in response to an external clock signal and the delayed time information; And the delay clock signal is used to adjust a timing margin of output data read during a synchronous burst read operation of a nonvolatile memory. The method of claim 1, And a clock input buffer configured to provide the external clock signal to the clock delay controller. The method of claim 1, The clock delay control unit, A plurality of delay circuits for delaying the external clock signal with different delay amounts; A selector configured to select one of the plurality of delay circuits, an input terminal of which is connected to connection nodes of the delay circuits and a control terminal of which is connected to an output terminal of the mode register; And And a buffer for outputting the output of the selected delay circuit as the delay clock signal. The method of claim 3, wherein And the delay circuits are cascaded from each other. The method of claim 3, wherein The delay time information is applied to the control stage to control the selection of the selector. A data output section for adjusting a timing margin of output data read in a synchronous burst read operation in response to a delayed clock signal; And A semiconductor integrated circuit for generating the delayed clock signal from an external clock signal, The semiconductor integrated circuit includes a nonvolatile memory device according to claim 1. Nonvolatile memory devices; And A memory controller controlling the flash memory device; The nonvolatile memory device includes the memory device of claim 6. Host; Nonvolatile memory devices; And A memory controller controlling the nonvolatile memory device according to a request of the host; The nonvolatile memory device of claim 6 comprising the method of claim 6.

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