KR100949877B1 - Semiconductor package - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and discloses a technology for transmitting characteristic information of a DRAM in a multi-chip package to a flash chip to prevent deformation of characteristics in the flash due to temperature changes. . The present invention is a semiconductor package in which a plurality of chips are stacked, the first process to detect the temperature information for a specific temperature and output at a predetermined time interval, and the internal process corresponding to the temperature information applied from the first chip And a second chip to change.

Description

Semiconductor Package {Semiconductor package}

1 is a block diagram of a semiconductor package according to the present invention.

2 is an operation timing diagram of a semiconductor package according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor package, and is a technology for transmitting characteristic temperature of a DRAM in a flash chip in a multi-chip package to prevent deformation of characteristics in the flash due to temperature change.

Recently, as the performance of electric and electronic products is improved, various technologies for providing high capacity semiconductor modules have been researched and developed. Here, a method capable of implementing a high-capacity semiconductor module includes a method of achieving high integration of a device, a method of manufacturing a package in a stack structure, and reducing the size of a package, thereby increasing the number of packages in a limited size printed circuit board. There is a way to be mounted. In response to these various technologies, various types of packages such as thin small outline package (TSOP), fine pitch ball grid array (FBGA), and multi chip package (MCP) have been developed.

In addition, according to the trend of high speed and miniaturization of multimedia systems, components mounted therein are also miniaturized. For example, in the case of semiconductor ICs, miniaturization is achieved through reduction of memory chips, and board mounting efficiency is increased by mounting several chips in one package.

As described above, a package having several chips having different functions in one package is generally called a multi chip package (MCP). Each chip in the multi-chip package is attached to one substrate and electrically connected to each other to perform one function. Such a multi-chip packaged semiconductor device may include a plurality of semiconductor devices in one package, thereby greatly reducing the size of the applied system.

On the other hand, flash memory is a semiconductor memory device having a characteristic of low power consumption and stored information does not disappear even when the power is turned off. That is, as a non-volatile memory that is continuously supplied with power, the stored information may be preserved even when the power is cut, unlike a DRAM. In addition, information input and output is free, so it is widely used in digital televisions, digital camcorders, digital cameras, mobile phones, personal digital assistants (PDAs), game machines, and MP3 players.

The flash memory is classified into two types, a data storage type having a large storage capacity (NAND-Type) and a code storage type having a high processing speed (NOR-Type). NAND type flash memory (hereinafter referred to as " NAND flash memory ") is highly integrated and can replace a hand disk, and thus is widely used for storing highly integrated voices or images.

The NAND flash memory includes a bit line that functions as an input / output terminal, a string formed by connecting a plurality of memory cell transistors in series between the bit line and the ground line, and a memory including a predetermined set of the strings. It includes a cell array (memory cell array).

However, when the semiconductor memory device operates at a high speed, the amount of heat generated increases in proportion to this. When the amount of heat generated continues to increase, for example, to 85 ° C. or more, the semiconductor memory device stops operating and loses data being processed.

This problem is more serious in mobile devices because most of them do not have a separate cooling system because of the small size of the mobile device.

In addition, an operation speed of the semiconductor memory device may decrease due to an external temperature. In particular, when the external temperature is lower than the proper operating temperature, the operating speed is lowered. In this case, the data processing speed is not guaranteed at a reliable level.

In the existing multi-chip package, DRAM operates at a low speed of about 66MHz, so there is little effect on temperature. However, as more and more functions and high-speed operation are required in mobile products, the speed is more than doubled.

In particular, most DRAMs or flash chips applied to mobile phones are formed in one multi-chip package and electrically connected to each other. In addition, the DRAM chip is operated at a relatively high speed compared to the flash chip, thereby generating a lot of heat.

Accordingly, when the above-described problems occur in the DRAM, the problems are transmitted to the flash chip connected thereto. That is, when the temperature of the DRAM changes, the timing characteristics of the flash chip, the program / erase characteristics of the cell, the internal potential, and the period of the reference oscillator change.

The present invention was created in order to solve the above problems, and by transmitting the temperature information of the DRAM in the flash chip in a multi-chip package, it is possible to prevent the deformation of the characteristics inside the flash due to temperature changes. The purpose is to make it.

A semiconductor package of the present invention for achieving the above object, the semiconductor package comprising a plurality of chips stacked, the first chip for detecting a temperature information for a specific temperature and output at a predetermined time interval; And a second chip for changing an internal process in response to the temperature information applied from the first chip.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a configuration diagram of a semiconductor package according to the present invention.

The present invention has a multi-chip package structure in which a DRAM and a flash chip are stacked in two layers. The DRAM formed on the lower (or upper) layer and the flash chip formed on the upper (or lower) layer are electrically connected to each other through a bonding wire.

Here, the DRAM includes a temperature sensor 100, a driver 200, and input / output pads P1 and P2. The flash chip includes a controller 300, a driver 400, an internal control circuit 500, and input / output pads P3 and P4. The input / output pads P1 and P2 of the DRAM and the input / output pads P3 and P4 of the flash chip are connected in a one-to-one correspondence.

In addition, the driving unit 200 of the DRAM includes a D-flip flop 210, a buffer 220, and an inverter 230 as a driving element. Here, temperature information T_0, which is an output of the temperature sensor, is applied to the data input terminal of the D-flip flop 210. The output of the inverter 230 is applied to the clock terminal of the D-flip flop 210. In addition, the output terminal of the D-flip-flop 210 is connected to the buffer 220.

In addition, the buffer 220 buffers the output of the D-flip flop 210 and outputs the temperature signal T_1 to the input / output pad P1. The inverter 230 inverts the signal applied from the input / output pad P2 to output the clock terminal of the D-flip flop 210.

In addition, the driver 400 of the flash chip includes a D-flip flop 410 and a buffer 420. Here, the output of the input / output pad P3 is applied to the data input terminal of the D-flip flop 410. The output clock T_clk of the controller 300 is applied to the clock terminal of the D-flop flop 410. In addition, the temperature signal T_2 output through the output terminal of the D-flip flop 410 is output to the internal control circuit 500. The buffer 420 buffers the output of the controller 300 to output the input / output pad P4.

An operation process of the present invention having such a configuration will be described with reference to the timing diagram of FIG. 2 as follows.

In a multi-chip package in which DRAM and flash chips are stacked, DRAM operates as a main heating source. Accordingly, the temperature information of the DRAM is transferred to another flash chip provided in the same package, so that proper response to the temperature change can be performed.

First, the temperature sensor 100 of the DRAM detects a specific temperature inside the DRAM and outputs the detected temperature information T_0 at regular intervals. The D-flip flop 210 delays and outputs the temperature information T_0 applied from the temperature sensor 100 for a predetermined time. At this time, the D-flip-flop 210 samples the temperature information T_0 in synchronization with the output clock of the inverter 230 and outputs the temperature signal T_1.

Thereafter, the buffer 220 buffers the output of the D-flip flop 210 and outputs the temperature signal T_1 to the input / output pad P1. At this time, the temperature signal T_1 is output in synchronization with the falling edge of the clock T_clk. The signal output through the input / output pad P1 of the DRAM is transferred to the input / output pad P3 of the flash chip.

Subsequently, the D-flip-flop 410 delays the signal applied from the input / output pad P3 for a predetermined time and outputs the temperature signal T_2. At this time, the D-flip-flop 410 samples and outputs the temperature signal T_2 in synchronization with the rising edge of the output clock T_clk of the controller 300.

Here, the internal control circuit 500 receives the temperature signal T_2 to control the internal circuit in response to the temperature code. For example, when the temperature of the device is increased according to the temperature signal T_2, the characteristics of the device may be changed. In this case, the internal control circuit 500 changes the bias point and timing characteristics of the internal voltage in response to the temperature.

The internal control circuit 500 trims the program / erase characteristics of the cell and the period of the oscillator according to the change in temperature. In addition, the internal control circuit 500 controls to change the self refresh cycle according to the change in temperature. Therefore, the internal control circuit 500 allows the internal process to be appropriately changed in response to the temperature signal T_2.

Next, the buffer 420 buffers the output clock T_clk of the controller 300 and outputs it to the input / output pad P4. The signal output through the input / output pad P4 of the flash chip is transferred to the input / output pad P2 of the DRAM. The inverter 230 of the DRAM buffers the signal applied from the input / output pad P2 and outputs the buffered signal to the clock terminal of the D-flip flop 210. In this case, the output clock of the inverter 230 is controlled by the clock T_clk applied from the controller 300 through the pads P2 and P4 and the buffer 420.

For example, when the clock T_clk transitions from high to low, the output of the inverter 230 becomes high through the buffer 420 and the input / output pads P2 and P4. Accordingly, the D-flip flop 210 outputs the temperature signal T_1 in synchronization with the output clock of the inverter 230. At this time, the clock T_clk is turned low so that the D-flip-flop 410 does not perform a sampling operation.

On the other hand, when the clock T_clk transitions from low to high, the D-flip-flop 410 outputs the temperature signal T_2 in synchronization with the clock T_clk. In addition, the output of the inverter 230 is low in the D-flip flop 210 through the buffer 420 and the input / output pads P2 and P4. Accordingly, the clock T_clk goes low, and the D-flip flop 210 does not perform the sampling operation.

Here, the temperature change of the DRAM may occur for several seconds, but most of the time, it proceeds at a fairly slow speed. Accordingly, the controller 300 outputs an appropriately adjusted period of the clock T_clk within a range that does not affect the operation of the internal control circuit 500.

Although the present invention has been described as an embodiment of the present invention applied to a multi-chip package in which a DRAM and a flash chip are stacked, the present invention is not limited thereto, but a DRAM + DRAM structure and a DRAM + NAND Flash. It may also be applied to a structure or a system in package (SIP) structure that is a DRAM + controller.

As described above, the present invention provides the following effects.

First, in the multi-chip package, the temperature information of the DRAM may be transmitted to the inside of the flash chip to prevent deformation of the inside of the flash due to temperature change.

Second, the temperature information of the DRAM is transmitted to the flash chip to change the bias point and timing characteristics of the internal voltage corresponding to the temperature.

Third, the temperature information of the DRAM is transferred to the flash chip to trim the program / erase characteristics of the cell according to the temperature.

Fourth, the temperature information of the DRAM is transmitted to the flash chip to change the oscillator cycle and the self refresh cycle in response to the temperature.

Fifth, in the multi-chip package, the temperature information of the DRAM is transmitted to the inside of the flash chip, thereby preventing the deformation of the characteristics inside the flash due to the temperature change, thereby improving the reliability of the multi-chip package product. To provide.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (15)

In a semiconductor package in which a plurality of chips are stacked, A first chip detecting temperature information and outputting the same at a predetermined time interval; And A second chip configured to control an operating characteristic of an internal circuit in response to the temperature information output from the first chip, The first chip A temperature sensor which detects a temperature and outputs the temperature information; A first driver configured to sample the temperature information applied from the temperature sensor and output a first temperature signal; A first input / output pad configured to output the first temperature signal to the second chip; And And a second input / output pad to which a clock from the second chip is applied. The semiconductor package of claim 1, wherein the first chip is a DRAM chip. The semiconductor package of claim 1, wherein the second chip is a flash chip. delete The method of claim 1, wherein the first driving unit A first flip flop that flips the temperature information in synchronization with the clock; A first buffer buffering an output of the first flip-flop and outputting the first temperature signal to the first input / output pad; And And a first driving device for driving the clock and outputting the clock to the first flip-flop. The semiconductor package of claim 5, wherein the first driving device is an inverter. The semiconductor package of claim 1, wherein the first temperature signal is output in synchronization with a falling edge of the clock. The method of claim 1, wherein the second chip A third input / output pad to which the first temperature signal is applied; A second driver for sampling a signal applied from the third input / output pad to output a second temperature signal; An internal control circuit for changing the internal process in response to the second temperature signal; A controller supplying a clock to the second driver; And And a fourth input / output pad configured to output a signal applied from the second driver to the first chip. The method of claim 8, wherein the second driving unit A second flip-flop that flips the first temperature signal in synchronization with the clock; And And a second buffer for buffering the clock and outputting the clock to the fourth input / output pad. The semiconductor package of claim 8, wherein the second temperature signal is output in synchronization with a rising edge of the clock. The semiconductor package of claim 8, wherein the internal control circuit controls to change a bias point of an internal voltage in response to the second temperature signal. The semiconductor package of claim 8, wherein the internal control circuit controls to change a timing characteristic of an internal circuit in response to the second temperature signal. 9. The semiconductor package of claim 8, wherein the internal control circuit controls to change a program / erase characteristic of a cell in response to the second temperature signal. The semiconductor package of claim 8, wherein the internal control circuit controls to change an oscillator cycle and a self refresh cycle in response to the second temperature signal. The semiconductor package of claim 1, wherein the plurality of pads included in the first chip are connected in a one-to-one correspondence with the plurality of pads included in the second chip.

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