JP2009008895A - Substrate for display device and manufacturing method thereof, and liquid crystal display and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for display device for reducing the total manufacturing steps in a liquid crystal display by forming a channel without using a halftone exposure technique, protecting and insulating source wiring and drain wiring and forming a protective insulating layer functioning also as a black matrix and a photo spacer, and to provide a manufacturing method thereof, the liquid crystal display and a manufacturing method thereof. <P>SOLUTION: The manufacturing method of the substrate for display device has: a step for forming a scanning line and the like; a step for forming a semiconductor layer; a step for forming the source drain wiring and the like; and a step for forming an aperture part in the protective insulating layer. The manufacturing method achieves a four mask process since the halftone exposure technique is not used. A photosensitive black pigment dispersion resin is used for the protective insulating layer and a BM function and a PS function are given to the substrate for display device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device substrate and a manufacturing method thereof, and a liquid crystal display device and a manufacturing method thereof, and in particular, a liquid crystal display device having a color image display function, particularly an active liquid crystal display device having a switching element for each pixel. About.

  With recent advances in microfabrication technology, liquid crystal material technology, high-density packaging technology, etc., 5-100 cm diagonal liquid crystal display devices have already been provided in large quantities on a commercial basis as television images and various image display devices. . These liquid crystal display devices can easily realize color display by forming an RGB colored layer on one of two glass substrates constituting a liquid crystal panel. In addition, in a so-called active type liquid crystal panel in which a switching element is built in for each pixel, an image having a low crosstalk, a high response speed, and a high contrast ratio has been guaranteed from the beginning of commercialization.

  These liquid crystal display devices (liquid crystal panels) generally have a matrix organization of 200 to 1200 scanning lines and 300 to 1600 signal lines, but recently, to cope with an increase in display capacity, Large screen and high definition are progressing simultaneously.

FIG. 68 is a perspective view showing a mounted state of the liquid crystal panel.
In FIG. 68, a semiconductor integrated circuit chip 3 that supplies a drive signal to an electrode terminal 5 of a scanning line formed on one transparent insulating substrate, for example, a glass substrate 2, constituting the liquid crystal panel 1 is bonded electrically. For example, a COG (Chip-On-Glass) system that uses an agent or a TCP film 4 having a terminal of gold or solder-plated copper foil based on a polyimide-based resin thin film as an electrode terminal 6 of a signal line An electrical signal is supplied to the image display unit by a mounting means such as a TCP (Tape-Carrier-Package) system that is fixed by pressure contact with an appropriate adhesive containing a conductive medium. Here, for convenience, two mounting methods are shown at the same time, but in actuality, either method is appropriately selected.

  Wiring paths 7 and 8 connect the pixels in the image display unit located almost at the center of the liquid crystal panel 1 and the electrode terminals 5 and 6 of the scanning lines and signal lines. The wiring paths 7 and 8 are not necessarily made of the same conductive material as the electrode terminals 5 and 6. Reference numeral 9 denotes a counter glass substrate or a color filter, which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the counter surface.

FIG. 69 is an equivalent circuit diagram of an active liquid crystal display device in which an insulated gate transistor 10 is arranged for each pixel as a switching element.
11 (7 in FIG. 68) is a scanning line, 12 (8 in FIG. 68) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn with solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the counter electrode 14 common to all the liquid crystal cells 13 drawn with dotted lines is the same as that of the other counter glass substrate 9. It is formed on the opposing main surface. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is attached to the gradation of the display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Is added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a storage capacitor line or a common electrode line serving as a common bus for the storage capacitor 15.

FIG. 70 is a cross-sectional view of a main part of an image display unit of a conventional liquid crystal display device.
The two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of resin fibers, beads, or spacer materials such as columnar spacers formed on the color filter 9 (both not shown) and are about several μm. The gap (gap) is formed in a closed space sealed with a sealing material made of an organic resin and a sealing material (both not shown) at the peripheral edge of the counter glass substrate 9. The closed space is filled with the liquid crystal 17.

  In the case of realizing color display, an organic thin film having a thickness of about 1 to 2 μm including one or both of a dye and a pigment called a colored layer 18 is applied to the closed space side of the counter glass substrate 9. Thus, a color display function is provided. Such a glass substrate 9 is also called a color filter (color filter abbreviation is CF). Then, depending on the material properties of the liquid crystal 17, a polarizing plate 19 is attached on either one or both of the upper surface of the counter glass substrate 9 and the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element. Currently, most liquid crystal panels on the market use TN (twisted nematic) type liquid crystal material, and two polarizing plates 19 are usually required. Although not shown, the transmissive liquid crystal panel has a back light source disposed as a light source, and is irradiated with white light from below.

  The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed on the two glass substrates 2 and 9 in contact with the liquid crystal 17 is an alignment film for aligning liquid crystal molecules in a predetermined direction. . Reference numeral 21 denotes a drain electrode (wiring) that connects the drain of the insulated gate transistor 10 and the transparent conductive pixel electrode 22, and is often formed simultaneously with the signal line (source line) 12. The semiconductor layer 23 is located between the source electrode 12 and the drain electrode 21 and will be described in detail later. The Cr thin film layer 24 having a thickness of about 0.1 μm formed at the boundary between the adjacent colored layers 18 on the color filter 9 prevents external light from entering the semiconductor layer 23, the scanning line 11, and the signal line 12. This is a light-shielding member that is fixed as a so-called black matrix (Black Matrix abbreviation is BM).

  For manufacturing a display device substrate (active substrate) on which a scanning line, a signal line, an insulated gate transistor as a switching element, and a pixel electrode are formed on a glass substrate 2, a photomask is used like a semiconductor integrated circuit. Multiple photolithography (photographic etching) processes are essential. Although detailed details are omitted, as a result of rationalization of the island formation process of the semiconductor layer and reduction of the contact formation process to the scanning line, the photomask that was originally required about 7 to 8 sheets is introduced by the introduction of the dry etching technique. At present, the number is reduced to five, which greatly contributes to the reduction of process costs. In order to reduce the production cost of the liquid crystal display device, it is effective to reduce the process cost in the manufacturing process of the active substrate, and it is effective to reduce the material cost in the panel assembly process and the module mounting process. Is a well-known development goal. That is, it is self-evident that reducing the number of manufacturing processes including the photolithography process greatly contributes to improving the productivity and cost reduction of the liquid crystal display device.

As already described, in the production of an active substrate, a manufacturing method that requires five photolithography steps is common. Therefore, among the prior examples proposed for further reduction in manufacturing cost, for example, four masks which have already been mass-produced and disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2000-206571).・ The process is introduced as a conventional example.
As described below, this four-mask process uses a halftone exposure technique to form a semiconductor layer including a channel and a source / drain wiring process using a single photomask. Technology or rationalization technology.

71, 73, 75, 77, 79, 81 are schematic plan views of unit pixels of the active substrate corresponding to the respective manufacturing steps of the four-mask process.
72, 74, 76, 78, 80, and 82 are schematic cross-sectional views of unit pixels of the active substrate corresponding to the respective manufacturing steps of the four-mask process. (A) of these sectional views shows a sectional view on the AA ′ line (insulated gate type transistor region), and (b) shows a sectional view on the BB ′ line (electrode terminal region of the scanning line). (C) shows a cross-sectional view on the CC ′ line (electrode terminal region of the signal line) (see FIG. 81).
In the past, two types of insulating gate type transistors, an etch stop type and a channel etch type, have been widely used. Here, it is essential to use a channel etched type insulating gate type transistor.

  First, as shown in FIG. 71 and FIG. 72, as an insulating substrate excellent in heat resistance, chemical resistance and transparency, a glass substrate 2 having a thickness of about 0.5 to 1.1 mm, for example, a product manufactured by Corning. The name 1737 is used. Next, a first metal layer (scanning line metal layer, about 0.1 to 0.3 μm thick) is formed on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT (sputtering). Alternatively, a gate conductive layer) is deposited. Subsequently, the scanning line 11 that also serves as the gate electrode 11A and the storage capacitor line 16 are formed by a fine processing technique. The material of the scanning line is selected by comprehensively considering heat resistance, chemical resistance, hydrofluoric acid resistance, conductivity, and the like. Generally, a metal thin film layer such as Cr or Ta having high heat resistance or Mo An alloy thin film layer such as an alloy of W and W is used.

  In order to reduce the resistance value of the scanning line corresponding to the increase in the screen size and the definition of the liquid crystal panel, it is reasonable to use AL (aluminum) as the material of the scanning line. However, since AL alone has low heat resistance, a structure in which it is laminated with Cr, Ta, Mo, or their silicides, which are the above-mentioned heat-resistant metals, is generally used. That is, the scanning line 11 is usually composed of one or more metal layers.

  Next, as shown in FIG. 73 and FIG. 74, the first silicon nitride (SiNx) layer to be the gate insulating layer 30 and almost all impurities are contained on the entire surface of the glass substrate 2 using a PCVD (plasma sieve uid) apparatus. First, the first amorphous silicon (a-Si) layer 31 that becomes the channel of the insulated gate transistor, and the second amorphous silicon layer that contains phosphorus as an impurity and becomes the source / drain of the insulated gate transistor ( n + a-Si) 33 thin film layers are successively deposited with a film thickness of, for example, about 0.3-0.2-0.05 [mu] m. Subsequently, as a second metal layer (heat-resistant metal layer) 34 having a film thickness of about 0.1 μm, for example, a Ti thin film layer and a low-resistance metal layer 35 having a film thickness of about 0.3 μm using a vacuum film forming apparatus such as SPT. As an AL thin film layer and a buffer conductive layer 36 having a film thickness of about 0.1 μm, for example, a Ti thin film layer (that is, a source / drain wiring material consisting of three layers) is sequentially deposited.

  Next, as shown in FIGS. 75 and 76, an insulated gate type comprising three layers of a refractory metal layer 34, a low resistance metal layer 35, and a buffer conductive layer 36 so as to partially overlap the gate electrode 11A by microfabrication technology. The signal line 12 that also serves as the source electrode of the transistor and the drain electrode 21 of the insulated gate transistor, which is composed of three layers of the heat-resistant metal layer 34, the low-resistance metal layer 35, and the buffer conductive layer 36, are selectively formed. At the time of this selective pattern formation, the film thickness of the source / drain channel formation region 80B (region below the recess) is, for example, 1.5 μm by the halftone exposure technique, and the source / drain wiring formation region 80A (12 ), 80A (21) is formed with photosensitive resin patterns 80A and 80B having a thickness of 3 μm, which is a major feature of the streamlined four-mask process.

For production of the active substrate, a positive photosensitive resin is usually used. Therefore, in the photomask corresponding to such photosensitive resin patterns 80A and 80B, the Cr thin film is formed so that the source / drain wiring forming region 80A is black, and the channel forming region 80B is gray (halftone). In order to reduce the light passing through the photomask, for example, a line-and-space Cr pattern having a width of about 0.5 to 1.5 μm is formed, and other regions are white, that is, The Cr thin film has been removed. In the gray area, since the resolving power of the exposure device is insufficient, the line and space is not resolved, and it is possible to transmit about half of the photomask irradiation light from the lamp light source. Therefore, photosensitive resin patterns 80A and 80B having a concave cross-sectional shape shown in FIG. 76 can be obtained in accordance with the remaining film characteristics of the positive photosensitive resin. The gray region may be formed of a metal layer having a different thickness or transmittance, for example, a thin film of MoSi ₂ , instead of the line and space Cr pattern (slit).

Using the photosensitive resin patterns 80A and 80B as a mask, the buffer conductive layer 36, the low resistance metal layer 35, the refractory metal layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 are sequentially eaten. When engraved, the gate insulating layer 30 is exposed (see FIGS. 75 and 76).
Next, although not shown, when the photosensitive resin patterns 80A and 80B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 80B disappears and the buffer conductive layer in the channel formation region 36 is exposed, and the photosensitive resin patterns 80C (12) and 80C (21) whose thickness is reduced only in the source / drain wiring formation region can be left.

Next, as shown in FIGS. 77 and 78, the buffer conductive layers 36 between the source and drain wirings (channel formation region) are again formed using the reduced photosensitive resin patterns 80C (12) and 80C (21) as masks. The low resistance metal layer 35, the refractory metal layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 are sequentially etched. Etch leaving about 0.1 μm. At this point, the second amorphous silicon layer 33S on the source side and the second amorphous silicon layer 33D on the drain side are separated. The source / drain wirings 12 and 21 are formed by etching the metal layer and then leaving the first amorphous silicon layer 31A about 0.05 to 0.1 μm. An insulated gate transistor obtained by such a manufacturing method is called a channel etch type.
In the oxygen plasma treatment, the photosensitive resin pattern 80A is converted into the photosensitive resin pattern 80C with a reduced film thickness, so that it is desirable to increase the anisotropy in order to suppress a change in pattern dimension. As means for increasing the anisotropy, oxygen plasma treatments such as an RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) method having a high-density plasma source, and a TCP (Transfer Coupled Plasma) method can be exemplified.

Next, the photosensitive resin patterns 80C (12) and 80C (21) are removed.
Next, as shown in FIGS. 79 and 80, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer to form a passivation insulating layer 37. Subsequently, openings 62, 63, and 64 are formed in a region on the drain electrode 21 and a region where the electrode terminals of the scanning line 11 and the signal line 12 are formed in a region outside the image display unit, respectively. That is, in the opening 63, the passivation insulating layer 37 and the gate insulating layer 30 are removed, and a part 5 of the scanning line is exposed. In the openings 62 and 64, the passivation insulating layer 37 is removed, and a part of the drain electrode 21 and a part 6 of the signal line are exposed. Similarly, an opening 65 is formed on the storage capacitor line 16, and a part of the storage capacitor line 16 is exposed.

Next, as shown in FIGS. 81 and 82, using a vacuum film forming apparatus such as SPT, as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm, for example, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide) or a mixed crystal thereof is deposited. Subsequently, the transparent conductive pixel electrode 22 is selectively formed on the passivation insulating layer 37 in a range including the opening 62 by a microfabrication technique, and the display device substrate (active substrate) 2F is completed.
As for the configuration of the storage capacitor 15, as shown in FIGS. 79 and 80, the drain electrode 21 and the storage capacitor line 16 include the gate insulating layer 30, the first amorphous silicon layer 31 A, and the second non-storage layer. The storage capacitor formation region 50 is formed by overlapping in a planar manner through the crystalline silicon layer 33D (the storage capacitor forming region 50 is a hatched portion with a downward slope to the right).
As for the electrode terminals, transparent conductive electrode terminals 5A and 6A are selectively formed on the openings 63 and 64 and the passivation insulating layer 37 around them.
Further, as a countermeasure against static electricity, a thin transparent conductive layer pattern 40 is connected between the electrode terminal 5A of the scanning line and the electrode terminal 6A of the signal line.

As described above, when AL (aluminum) is used for the source / drain wirings 12 and 21, the refractory metal layer 34 is necessary to ensure electrical connection with the second amorphous silicon 33. Further, a buffer conductive layer 36 is necessary between the transparent conductive layer and the transparent conductive layer in order to avoid a battery effect in an alkaline solution, and as a result, the source / drain wiring has a three-layer structure. Although this three-layer configuration is disadvantageous from the viewpoint of production cost, it is not possible to avoid the use of a low-resistance metal layer in large screens and high-definition liquid crystal panels where restrictions on the resistance value of the source / drain wiring are severe. Have difficulty.
Conventionally, when Ti is used for the refractory metal layer 34 and the buffer conductive layer 36, a dry etching process using a chlorine-based gas is required for the etching, and a chlorine-based gas is automatically used for the AL etching. The dry etching process used was a heavy burden not only on the material side but also on the production equipment. Recently, new chemicals for etching Ti have been offered by Mitsubishi Chemical, and the possibility of reducing the investment burden of production facilities has increased. When Mo is used for the refractory metal layer 34 and the buffer conductive layer 36 instead of Ti, it is customary to perform a three-layer structure of Mo / AL / Mo with a single chemical treatment with a phosphoric acid solution to which an appropriate amount of nitric acid has been added. As a result, the investment of production facilities can be reduced. Further, it is not necessary to explain that efforts have been made to simplify the source / drain wiring as much as possible to reduce the production cost.
As a technique for improving productivity by reducing the number of masks, there are techniques described in Patent Documents 2 to 4, for example.
By the way, a decrease in the market price of TFT (thin film transistor) liquid crystal display devices due to a reduction in production cost can bring about a new stimulation of product demand. For this reason, manufacturers of TFT liquid crystal display devices are working to reduce the number of various processes.
JP 2000-206571 A JP 2005-215276 A JP-A-2005-122186 Japanese Patent Laid-Open No. 2005-181984 JP-A-2005-010806

However, the manufacturing method (four-mask process) requires strict manufacturing control, and there is a problem that it is practically difficult to improve yield and image quality.
That is, the channel forming step applied in the four-mask process is a step of selectively removing the source / drain wiring material between the source / drain wirings 12 and 21 and the semiconductor layer. In this step, the channel length (4 to 6 μm in the current mass-produced product) that greatly affects the ON characteristics of the insulated gate transistor is determined. When the channel length varies, the ON current value of the insulated gate transistor is greatly changed, and therefore, more stringent manufacturing management is required than conventional manufacturing management. This is because the channel length, that is, the pattern size of the halftone exposure area, the exposure amount (light source intensity and pattern accuracy of the mask, especially the line and space dimensions), the coating thickness of the photosensitive resin, the phenomenon processing of the photosensitive resin, and This is because it depends on many parameters such as the amount of film loss of the photosensitive resin in the etching process. Therefore, it is difficult to stabilize the above-mentioned various amounts, and furthermore, it is not realistic to stably produce with a high yield due to the in-plane uniformity of these amounts.

  In particular, when the channel length is 5 μm or less, the tendency becomes remarkable. This is because when the thickness of the photosensitive resin patterns 80A and 80B is reduced by 1.5 μm and the photosensitive resin patterns 80A and 80B are isotropically reduced, the dimension between the photosensitive resin patterns 80A and 80B is naturally This is because the channel length becomes 3 μm longer than the set value because it becomes 3 μm larger. Furthermore, fluctuations in channel length also cause parasitic capacitance values to fluctuate due to the gate electrode and drain electrode being formed through the gate insulating layer, so that luminance unevenness due to crosstalk in-plane non-uniformity is displayed. The uniformity of image quality was reduced.

  Further, since it is difficult to change the basic structure of the TFT, there is a problem that the four-mask process is further improved, for example, it is not easy to develop a three-mask process.

In addition, since the production of TFT liquid crystal display devices has started, CF (color filter) has long been a product purchased from a company specializing in CF production as a major member in the panel assembly process of liquid crystal panels.
However, dealing with mass production corresponding to the increasing amount of CF used by only a few CF manufacturing specialist companies has been a major issue in business investment risk and delivery time. For this reason, recently, an increasing number of panel manufacturers in-house produce CF.

Although detailed explanation is omitted, in order to manufacture CF, in addition to the formation process of BM and the formation of R, G, B colored layers, the gap formation accuracy of the liquid crystal cell has been increased in response to the latest large screen. A PS (Photo-Spacer) formation process is required to increase the thickness. In each of these forming processes, one photomask is required. Therefore, when four photomasks are used for manufacturing the TFT substrate, a total of six photomasks are required for the liquid crystal display device.
Further, when using vertically aligned liquid crystal for wide viewing angle, a resin protrusion is often used as an alignment regulating material on the CF counter electrode, and another photomask is also required here. In this case, if four photomasks are used for manufacturing the TFT substrate, a total of seven photomasks are required for the liquid crystal display device.

  If a part of the CF manufacturing process is performed on the active substrate and the total number of manufacturing steps in the TFT liquid crystal display device can be reduced, the manufacturing cost of the TFT liquid crystal display device can naturally be reduced. . In this way, there is a demand for the development of a comprehensive (total) technology that eliminates the boundaries between CF makers and panel makers.

  The present invention has been made in view of such a situation, and forms a channel without using a halftone exposure technique. Further, the present invention protects and insulates source wiring and drain wiring, and functions as a black matrix and a photo spacer. An object of the present invention is to provide a display device substrate and a method for manufacturing the same, and a liquid crystal display device and a method for manufacturing the same that can reduce the total number of manufacturing steps in the liquid crystal display by forming a protective insulating layer. To do.

The method for manufacturing a display device substrate (active substrate) according to the present invention includes a scanning line forming process, a semiconductor layer forming process, a source / drain wiring forming process, and an opening forming process in a protective insulating layer. A display device substrate can be manufactured using a total of four photomasks.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, the source / drain wiring is protected by using a photosensitive black pigment dispersed resin for the protective insulating layer of the active substrate. Since this protective insulating layer also functions as a black matrix and a photo spacer, the added value of the display device substrate can be improved. Further, when this display device substrate is used in a liquid crystal display device, it is not necessary to form a black matrix or a photo spacer in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

  Therefore, as disclosed in Patent Document 2 and Patent Document 3, a scanning line made of a laminate of a transparent conductive layer and a scanning line metal layer is employed, and as disclosed in Patent Document 4. In addition, a signal line made of a laminate of a transparent conductive layer and a metal layer for source / drain wiring is employed. If a pseudo pixel electrode composed of these layers is formed at the same time, an unnecessary thin film on the pseudo pixel electrode is removed to obtain a transparent conductive pixel electrode, as disclosed in Patent Document 5. A photosensitive black pigment-dispersed resin can be used, and the reduction of the manufacturing process is promoted.

  The display device substrate of the present invention includes a gate electrode, a scanning line and a scanning line electrode terminal formed from a gate conductive layer deposited on one main surface of the substrate, and the substrate, the gate electrode, the scanning line and the scanning. A gate insulating layer deposited on the line electrode terminal, and a first amorphous silicon layer not deposited on the gate electrode, which is deposited in succession following the gate insulating layer and does not contain impurities. A second amorphous silicon layer containing impurities and a conductive layer for source / drain electrodes, and a transparent conductive layer and a signal line conductive layer sequentially deposited on the source / drain electrode conductive layer and the gate insulating layer. A channel, a source electrode, a source wiring, a signal line, a pseudo electrode terminal for a signal line, a drain electrode, a drain wiring, and a pseudo pixel electrode formed from a multilayer body including a layer, the channel, the source electrode, the source wiring, the signal line, Signal line A pixel electrode opening on the pseudo pixel electrode and an electrode terminal opening on the scanning line electrode terminal are sequentially deposited on the substrate on which the pseudo electrode terminal, drain electrode, drain wiring, and pseudo pixel electrode are formed. The signal line conductive layer is removed from the passivation insulating layer and the protective insulating layer in which the electrode terminal openings are formed on the portions and the signal line pseudo electrode terminal, and the pseudo pixel electrode and the signal line pseudo electrode terminal. A pixel electrode and a signal line electrode terminal made of the transparent conductive layer, and an electrode terminal opening formed in the gate insulating layer to expose the scanning line electrode terminal. As a configuration.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
In general, the first metal layer is used as the gate conductive layer, the second metal layer (heat-resistant metal layer) is used as the source / drain electrode conductive layer, and the third metal layer is used as the signal line conductive layer. Is used.
Note that, with the above configuration, the pseudo pixel electrode and the signal line pseudo electrode terminal which are formed of a laminate including the transparent conductive layer and the signal line conductive layer and are formed together with the signal line have openings to the protective insulating layer and the passivation insulating layer. By removing the signal line conductive layer in the opening at the time of formation, a pixel electrode and a signal line electrode terminal made of a transparent conductive layer are obtained. The scanning line electrode terminal is made of a gate conductive layer which is the same member as the scanning line.

  The display device substrate of the present invention includes a gate electrode formed from a gate conductive layer deposited on one main surface of the substrate, a scanning line and a pseudo electrode terminal for scanning line, the substrate, the gate electrode, the scanning line, and A gate insulating layer formed on the gate electrode and the scanning line and formed on the gate electrode and the scanning line, the first amorphous silicon layer not containing the impurity, and the impurity. A multi-layer body including a second amorphous silicon layer and a conductive layer for source / drain electrodes, and a transparent conductive layer and a conductive layer for signal lines sequentially deposited on the source / drain electrode conductive layer and the substrate Channel, source electrode, source wiring, signal line, signal line pseudo electrode terminal, scanning line pseudo electrode terminal, drain electrode, drain wiring and pseudo pixel electrode, and the channel, source electrode, source Wiring, signal lines, pseudo electrode terminals for signal lines, pseudo electrode terminals for scanning lines, drain electrodes, drain wirings, and pixel electrodes on the pseudo pixel electrodes are sequentially deposited on the substrate on which the pseudo pixel electrodes are formed. A passivation insulating layer in which an opening, an opening for preventing a parasitic transistor on the scanning line, an electrode terminal opening on the scanning line pseudo electrode terminal, and an electrode terminal opening on the signal line pseudo electrode terminal are formed And a protective insulating layer, and a pixel electrode made of the transparent conductive layer exposed by removing the signal line conductive layer from the pseudo pixel electrode, the scanning line pseudo electrode terminal, and the signal line pseudo electrode terminal The gate insulation exposed in the opening for preventing the parasitic transistor by removing the scanning line electrode terminal and the signal line electrode terminal and the first amorphous silicon layer. A configuration equipped with door.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the first amorphous silicon layer on the scan line is partially removed, the adverse effect of the parasitic transistor can be avoided, and the performance as a display device substrate can be improved.
In general, the first metal layer is used as the gate conductive layer, the second metal layer (heat-resistant metal layer) is used as the source / drain electrode conductive layer, and the third metal layer is used as the signal line conductive layer. Is used.
With the above configuration, the pseudo pixel electrode, the scanning line pseudo electrode terminal, and the signal line pseudo electrode terminal, which are formed of a laminate including a transparent conductive layer and a signal line conductive layer and are formed with the signal line, are connected to the protective insulating layer. By removing the signal line conductive layer in the opening at the time of forming the opening in the passivation insulating layer, the pixel electrode, the scanning line electrode terminal, and the signal line electrode terminal formed of the transparent conductive layer are obtained.

  The display device substrate of the present invention includes a gate electrode, a scanning line, a scanning line pseudo-electrode terminal formed from a laminate including a transparent conductive layer and a gate conductive layer deposited on one main surface of the substrate, A signal line pseudo electrode terminal and a pseudo pixel electrode, and the substrate, gate electrode, scanning line, scanning line pseudo electrode terminal, signal line pseudo electrode terminal, and pseudo pixel electrode are sequentially deposited on the gate electrode and the scanning line. A gate insulating layer formed on the line wider than the gate electrode and the scan line, a first amorphous silicon layer not containing an impurity, a second amorphous silicon layer containing an impurity, and the pseudo electrode terminal for the scan line A pixel electrode made of the transparent conductive layer, a scanning line electrode terminal, and a signal line electrode terminal exposed by removing the gate conductive layer from the signal line pseudo electrode terminal and the pseudo pixel electrode; Second amorphous A silicon layer, a transparent conductive layer, a signal line conductive layer deposited on the substrate, a channel formed from a multilayer body including the first amorphous silicon layer and the second amorphous silicon layer, a source electrode A source line, a signal line connected to the signal line electrode terminal, a drain electrode, a drain line connected to the pixel electrode, and the channel, source electrode, source line, signal line, signal line electrode terminal, scanning A pixel electrode opening on the pixel electrode, a parasitic transistor preventing opening on the scanning line, and the scanning are sequentially deposited on the substrate on which the line electrode terminal, drain electrode, drain wiring, and pixel electrode are formed. Passivation insulating layer and protective insulating layer having electrode terminal opening on line electrode terminal and electrode terminal opening on signal line electrode terminal, and first amorphous silicon layer By being removed, a configuration equipped with said gate insulating layer exposed to said parasitic transistor preventing the opening.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the first amorphous silicon layer on the scan line is partially removed, the adverse effect of the parasitic transistor can be avoided, and the performance as a display device substrate can be improved.
In general, a first metal layer is used as the gate conductive layer, and one or more second metal layers including a heat-resistant metal layer are used as the signal line conductive layer.
With the above configuration, the pseudo pixel electrode, the pseudo electrode terminal for the scanning line, and the pseudo electrode terminal for the signal line which are formed of the laminate including the transparent conductive layer and the gate conductive layer together with the scanning line are gated when the semiconductor layer is formed. By removing the conductive layer, a pixel electrode, a scanning line electrode terminal, and a signal line electrode terminal made of a transparent conductive layer are obtained.

  The display device substrate of the present invention includes a gate electrode, a scanning line, a scanning line pseudo-electrode terminal formed from a laminate including a transparent conductive layer and a gate conductive layer deposited on one main surface of the substrate, A signal line pseudo electrode terminal and a pseudo pixel electrode, and the substrate, gate electrode, scanning line, scanning line pseudo electrode terminal, signal line pseudo electrode terminal, and pseudo pixel electrode are sequentially deposited on the gate electrode and the scanning line. A gate insulating layer formed on the line wider than the gate electrode and the scan line, a first amorphous silicon layer not containing impurities, a second amorphous silicon layer containing impurities, and the second amorphous A silicon layer, a gate conductive layer, a signal line conductive layer deposited on the substrate, a channel formed from a multilayer body including the first amorphous silicon layer and the second amorphous silicon layer, a source electrode , Source wiring, pseudo signal line The gate conductive layer is removed from the signal line connected to the electrode terminal, the drain electrode, the drain wiring connected to the pseudo pixel electrode, and the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, and the pseudo pixel electrode. The pixel electrode, the scanning line electrode terminal, and the signal line electrode terminal made of the transparent conductive layer, the channel, the source electrode, the source wiring, the signal line, the signal line electrode terminal, and the scanning line, A pixel electrode opening on the pixel electrode, a parasitic transistor preventing opening on the scanning line, and the scanning line, which are sequentially deposited on the substrate on which the electrode terminal, drain electrode, drain wiring and pixel electrode are formed. A passivation insulating layer and a protective insulating layer formed with an electrode terminal opening on the electrode terminal and an electrode terminal opening on the signal line electrode terminal, and the first amorphous By silicon layer is removed, a configuration equipped with said gate insulating layer exposed to said parasitic transistor preventing the opening.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the first amorphous silicon layer on the scan line is partially removed, the adverse effect of the parasitic transistor can be avoided, and the performance as a display device substrate can be improved.
In general, a first metal layer is used as the gate conductive layer, and one or more second metal layers including a heat-resistant metal layer are used as the signal line conductive layer.
With the above configuration, the pseudo pixel electrode, the pseudo electrode terminal for the scan line, and the pseudo electrode terminal for the signal line, which are formed of the laminated body including the transparent conductive layer and the gate conductive layer and are formed together with the scan line, By removing the gate conductive layer at the time of formation, a pixel electrode, a scanning line electrode terminal, and a signal line electrode terminal made of a transparent conductive layer are obtained.

  The display device substrate of the present invention includes a gate electrode, a scanning line, a scanning line pseudo-electrode terminal formed from a laminate including a transparent conductive layer and a gate conductive layer deposited on one main surface of the substrate, A signal line pseudo electrode terminal and a pseudo pixel electrode, and the substrate, gate electrode, scanning line, scanning line pseudo electrode terminal, signal line pseudo electrode terminal, and pseudo pixel electrode are sequentially deposited on the gate electrode and the scanning line. A gate insulating layer formed on the line wider than the gate electrode and the scan line, a first amorphous silicon layer not containing impurities, a second amorphous silicon layer containing impurities, and the second amorphous A silicon layer, a gate conductive layer, a signal line conductive layer deposited on the substrate, a channel formed from a multilayer body including the first amorphous silicon layer and the second amorphous silicon layer, a source electrode , Source wiring, pseudo signal line A signal line connected to the electrode terminal, a drain electrode, a drain wiring connected to the pseudo pixel electrode, and the channel, source electrode, source wiring, signal line, pseudo electrode terminal for signal line, pseudo electrode terminal for scanning line, A pixel electrode opening on the pseudo pixel electrode, a parasitic transistor preventing opening on the scanning line, and a scanning line pseudo are sequentially deposited on the substrate on which the drain electrode, drain wiring, and pseudo pixel electrode are formed. A passivation insulating layer and a protective insulating layer in which an electrode terminal opening on the electrode terminal and an electrode terminal opening on the signal line pseudo electrode terminal are formed, the scanning line pseudo electrode terminal, and the signal line pseudo electrode A pixel electrode made of the transparent conductive layer, a scanning line electrode terminal, and a signal line electrode exposed by removing the gate conductive layer from the terminal and the pseudo pixel electrode And child, by the first amorphous silicon layer is removed, a configuration equipped with said gate insulating layer exposed to said parasitic transistor preventing the opening.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the first amorphous silicon layer on the scan line is partially removed, the adverse effect of the parasitic transistor can be avoided, and the performance as a display device substrate can be improved.
In general, a first metal layer is used as the gate conductive layer, and one or more second metal layers including a heat-resistant metal layer are used as the signal line conductive layer.
With the above configuration, the pseudo pixel electrode, the pseudo electrode terminal for the scanning line, and the pseudo electrode terminal for the signal line, which are formed of the laminate including the transparent conductive layer and the gate conductive layer and formed with the scanning line, are protected from the protective insulating layer and the passivation insulation. By removing the gate conductive layer in the opening when forming the opening in the layer, a pixel electrode, a scanning line electrode terminal, and a signal line electrode terminal made of a transparent conductive layer are obtained.

Preferably, the protective insulating layer has a light shielding property.
In this case, the protective insulating layer protects and insulates the source wiring and the drain wiring and also functions as a black matrix, so that the added value of the display device substrate can be improved. Further, when this display device substrate is used in a liquid crystal display device, it is not necessary to form a black matrix in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.
Furthermore, it is possible to provide an alignment regulating means by leaving the protective insulating layer and the passivation insulating layer in a protruding shape on the pixel electrode, so that the vertical alignment type liquid crystal mode can be supported. That is, the viewing angle can be improved along with the process reduction.
In addition, photosensitive black pigment dispersion resin etc. are mentioned as a material which has light-shielding property.

Preferably, the protective insulating layer in the spacer region is thicker than other regions.
In this case, the protective insulating layer protects and insulates the source wiring and the drain wiring, and also functions as a photo spacer, so that the added value of the display device substrate can be improved. In addition, when this display device substrate is used in a liquid crystal display device, the spacer dispersion step is not required, or it is not necessary to form a photo spacer in the color filter, so the total number of masks in the liquid crystal display device Can be reduced. Accordingly, the manufacturing cost can be reduced.
A halftone exposure technique is used for producing protective insulating layers (photosensitive black pigment dispersed resin patterns) having different thicknesses.

Preferably, a storage capacitor to which the pixel electrode and one electrode are connected, a storage capacitor line connected to the other electrode of the storage capacitor, and a storage capacitor line electrode terminal are formed.
Thus, the gradation of the display image can be improved, and the added value as a display device substrate can be improved.

Preferably, the substrate is transparent and has an insulating property, and the passivation insulating layer is transparent.
In this way, the translucency can be improved, and when used in a liquid crystal display device, the image quality can be improved.

  The method for manufacturing a substrate for a display device according to the present invention includes a step of forming a gate electrode, a scanning line, and a scanning line electrode terminal made of a first metal layer on one main surface of the substrate, a gate insulating layer, A step of sequentially depositing a first amorphous silicon layer that does not contain, a second amorphous silicon layer that contains impurities, and a second metal layer; and the first amorphous silicon layer on the gate electrode Forming a laminate including a layer, a second amorphous silicon layer, and a second metal layer in an island shape, exposing the gate insulating layer, and depositing a transparent conductive layer and a third metal layer , Removing a part of the third metal layer, the transparent conductive layer, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer, a channel, a source electrode and a drain electrode, And a source wiring and a drain wiring comprising a laminate including the transparent conductive layer and the third metal layer. Forming a signal line, a pseudo pixel electrode, and a signal line pseudo electrode terminal; depositing a passivation insulating layer; an electrode terminal opening on the scan line electrode terminal; and the signal line pseudo electrode terminal. Forming a protective insulating layer having an opening for the electrode terminal on the upper side and an opening for the pixel electrode on the pseudo pixel electrode on the passivation insulating layer; and selectively removing the passivation insulating layer; Exposing the signal line pseudo electrode terminal and the pseudo pixel electrode; selectively removing the third metal layer; exposing the signal line electrode terminal and the pixel electrode made of the transparent conductive layer; A step of selectively removing the gate insulating layer and exposing the scanning line electrode terminal made of the first metal layer.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Also, a gate conductive layer is usually used as the first metal layer, a source / drain electrode conductive layer is used as the second metal layer (heat-resistant metal layer), and a signal line conductive layer is used as the third metal layer. Is used.
In addition, the pseudo pixel electrode and the pseudo electrode terminal for the signal line, which are formed of the laminate including the transparent conductive layer and the conductive layer for the signal line and formed with the signal line by the above method, are the openings to the protective insulating layer and the passivation insulating layer. By removing the signal line conductive layer in the opening at the time of formation, a pixel electrode and a signal line electrode terminal made of a transparent conductive layer are obtained. For this reason, an independent photolithography process for forming the pixel electrode is unnecessary. The scanning line electrode terminal is made of a gate conductive layer which is the same member as the scanning line.

  The method for manufacturing a substrate for a display device according to the present invention includes a step of forming a gate electrode, a scanning line, and a pseudo electrode terminal for a scanning line made of a first metal layer on one main surface of the substrate, and a gate insulating layer. Sequentially depositing a first amorphous silicon layer not containing an impurity, a second amorphous silicon layer containing an impurity, and a second metal layer, and the gate insulation on the gate electrode and the scan line A stacked body including a layer, a first amorphous silicon layer, a second amorphous silicon layer, and a second metal layer is formed wider than the gate electrode and the scanning line, and the scanning line pseudo electrode terminal and Exposing the substrate; depositing a transparent conductive layer and a third metal layer; and the third metal layer, the transparent conductive layer, the second metal layer, the second amorphous silicon layer, and the first metal layer Removing a part of the amorphous silicon layer, a channel, a source electrode and a drain electrode, And forming a source wiring, a drain wiring, a signal line, a pseudo pixel electrode, a scanning line pseudo electrode terminal, and a signal line pseudo electrode terminal made of a laminate including the transparent conductive layer and the third metal layer; A step of depositing a passivation insulating layer; an electrode terminal opening on the scanning line pseudo electrode terminal; an electrode terminal opening on the signal line pseudo electrode terminal; and a pixel electrode opening on the pseudo pixel electrode. And a step of forming a protective insulating layer having an opening for preventing parasitic transistors on the scanning line on the passivation insulating layer, and selectively removing the passivation insulating layer, and the scanning line pseudo electrode terminal A step of exposing the pseudo electrode terminal for signal lines, the pseudo pixel electrode and the first amorphous silicon layer in each of the openings, and selectively removing the third metal layer from the transparent conductive layer. Exposing the scanning line electrode terminal, the signal line electrode terminal, and the pixel electrode, and selectively removing the first amorphous silicon layer in the parasitic transistor prevention opening to prevent the parasitic transistor And exposing the gate insulating layer in the opening.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the first amorphous silicon layer on the scan line is partially removed, the adverse effect of the parasitic transistor can be avoided, and the performance as a display device substrate can be improved.
Also, a gate conductive layer is usually used as the first metal layer, a source / drain electrode conductive layer is used as the second metal layer (heat-resistant metal layer), and a signal line conductive layer is used as the third metal layer. Is used.
In addition, the pseudo pixel electrode, the pseudo electrode terminal for scanning line, and the pseudo electrode terminal for signal line, which are formed of a laminate including the transparent conductive layer and the signal line conductive layer by the above method and formed with the signal line, By removing the signal line conductive layer in the opening when forming the opening in the passivation insulating layer, a pixel electrode, a scanning line electrode terminal, and a signal line electrode terminal made of a transparent conductive layer are obtained. For this reason, an independent photolithography process for forming the pixel electrode is unnecessary.

  In addition, the method for manufacturing a substrate for a display device according to the present invention includes a gate electrode, a scanning line, a scanning line pseudo-electrode terminal formed of a laminate including a transparent conductive layer and a first metal layer on one main surface of the substrate, Forming a pseudo pixel electrode and a signal line pseudo electrode terminal; and sequentially depositing a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities. A stacked body including the gate insulating layer, the first amorphous silicon layer, and the second amorphous silicon layer is formed on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. A scanning line pseudo electrode terminal, a pseudo pixel electrode, a signal line pseudo electrode terminal, and a substrate; and a step of removing the first metal layer and forming the scanning line electrode terminal, the pixel electrode, and the transparent conductive layer. Exposing the signal line electrode terminals; and Depositing one or more second metal layers including a refractory metal layer, removing a portion of the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer; Forming a channel, a source electrode and a drain electrode, and a source wiring, a drain wiring, and a signal line made of the second metal layer, a step of depositing a passivation insulating layer, and a scanning line electrode terminal A protective insulating layer having an electrode terminal opening, an electrode terminal opening on the signal line electrode terminal, a pixel electrode opening on the pixel electrode, and a parasitic transistor prevention opening on the scanning line; Forming the passivation insulating layer on the passivation insulating layer; and selectively removing the passivation insulating layer; and the scanning line electrode terminal, the signal line electrode terminal, the pixel electrode, and the first amorphous silicon layer, Exposed in the opening And a step of selectively removing the first amorphous silicon layer in the opening for preventing parasitic transistors and exposing the gate insulating layer in the opening for preventing parasitic transistors. .

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the first amorphous silicon layer on the scan line is partially removed, the adverse effect of the parasitic transistor can be avoided, and the performance as a display device substrate can be improved.
Further, a gate conductive layer is usually used as the first metal layer, and a signal line conductive layer is used as one or more second metal layers including the refractory metal layer.
Note that the pseudo pixel electrode, the pseudo electrode terminal for the scanning line, and the pseudo electrode terminal for the signal line which are formed of the laminate including the transparent conductive layer and the gate conductive layer by the above method and are formed together with the scanning line are gated at the time of forming the semiconductor layer. By removing the conductive layer, a pixel electrode, a scanning line electrode terminal, and a signal line electrode terminal made of a transparent conductive layer are obtained. For this reason, an independent photolithography process for forming the pixel electrode is unnecessary.

  In addition, the method for manufacturing a substrate for a display device according to the present invention includes a gate electrode, a scanning line, a scanning line pseudo-electrode terminal formed of a laminate including a transparent conductive layer and a first metal layer on one main surface of the substrate, Forming a pseudo pixel electrode and a signal line pseudo electrode terminal; and sequentially depositing a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities. A stacked body including the gate insulating layer, the first amorphous silicon layer, and the second amorphous silicon layer is formed on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. A step of exposing a scanning line pseudo electrode terminal, a pseudo pixel electrode, a signal line pseudo electrode terminal, and a substrate; and depositing one or more second metal layers including a heat-resistant metal layer; and , The first metal layer, the second amorphous silicon layer, and the first A part of the crystalline silicon layer is removed to form a channel, a source electrode and a drain electrode, and a source wiring, a drain wiring and a signal line made of the second metal layer, and for a scanning line made of the transparent conductive layer Exposing the electrode terminal, the pixel electrode and the signal line electrode terminal; depositing a passivation insulating layer; an electrode terminal opening on the scan line electrode terminal; and an electrode on the signal line electrode terminal. Forming a protective insulating layer having a terminal opening, a pixel electrode opening on the pixel electrode, and a parasitic transistor preventing opening on the scanning line on the passivation insulating layer; and the passivation insulating layer Selectively exposing the scanning line electrode terminal, the signal line electrode terminal, the pixel electrode, and the first amorphous silicon layer in each of the openings, and the parasitic Selectively removing the first amorphous silicon layer transistor in preventing opening is as a method and a step of exposing the gate insulating layer on the parasitic transistor preventing the opening.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the first amorphous silicon layer on the scan line is partially removed, the adverse effect of the parasitic transistor can be avoided, and the performance as a display device substrate can be improved.
Further, a gate conductive layer is usually used as the first metal layer, and a signal line conductive layer is used as one or more second metal layers including the refractory metal layer.
By the above method, the pseudo pixel electrode, the pseudo electrode terminal for scanning line, and the pseudo electrode terminal for signal line which are formed of a laminated body including a transparent conductive layer and a gate conductive layer and are formed together with the scanning line are source / drain wirings, etc. By removing the gate conductive layer at the time of formation, a pixel electrode, a scanning line electrode terminal, and a signal line electrode terminal made of a transparent conductive layer are obtained. For this reason, an independent photolithography process for forming the pixel electrode is unnecessary.

  In addition, the method for manufacturing a substrate for a display device according to the present invention includes a gate electrode, a scanning line, a scanning line pseudo-electrode terminal formed of a laminate including a transparent conductive layer and a first metal layer on one main surface of the substrate, Forming a pseudo pixel electrode and a signal line pseudo electrode terminal; and sequentially depositing a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities. A stacked body including the gate insulating layer, the first amorphous silicon layer, and the second amorphous silicon layer is formed on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. A step of exposing a scanning line pseudo electrode terminal, a pseudo pixel electrode, a signal line pseudo electrode terminal, and a substrate; and depositing one or more second metal layers including a heat-resistant metal layer; and , Second amorphous silicon layer and first amorphous silicon Forming a channel, a source electrode and a drain electrode, and a source wiring, a drain wiring, and a signal line made of the second metal layer, a step of depositing a passivation insulating layer, Electrode terminal opening on scanning line pseudo electrode terminal, electrode terminal opening on signal line pseudo electrode terminal, pixel electrode opening on pseudo pixel electrode, and parasitic transistor prevention on scanning line A step of forming a protective insulating layer having an opening for the electrode on the passivation insulating layer, and selectively removing the passivation insulating layer, the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, and the pseudo pixel electrode And a step of exposing the first amorphous silicon layer in each of the openings, the first metal layer is selectively removed, and a scanning line electrode terminal comprising the transparent conductive layer, a signal Exposing the electrode terminal and the pixel electrode in each of the openings, and selectively removing the first amorphous silicon layer in the opening for preventing the parasitic transistor, and in the opening for preventing the parasitic transistor Exposing the gate insulating layer.

By doing so, display is performed using a total of four photomasks in the formation process of the scanning line, the formation process of the semiconductor layer, the formation process of the source / drain wiring, and the opening formation process to the protective insulating layer. A device substrate can be manufactured.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the first amorphous silicon layer on the scan line is partially removed, the adverse effect of the parasitic transistor can be avoided, and the performance as a display device substrate can be improved.
Further, a gate conductive layer is usually used as the first metal layer, and a signal line conductive layer is used as one or more second metal layers including the refractory metal layer.
The pseudo pixel electrode, the pseudo electrode terminal for the scanning line, and the pseudo electrode terminal for the signal line which are formed of the laminate including the transparent conductive layer and the gate conductive layer by the above method and formed with the scanning line are protected from the protective insulating layer and the passivation insulation. By removing the gate conductive layer in the opening when forming the opening in the layer, the pixel electrode, the scanning line electrode terminal, and the signal line electrode terminal formed of the transparent conductive layer are obtained. For this reason, an independent photolithography process for forming the pixel electrode is unnecessary.

Preferably, the protective insulating layer has a light shielding property.
In this case, the protective insulating layer protects and insulates the source wiring and the drain wiring and also functions as a black matrix, so that the added value of the display device substrate can be improved. Further, when this display device substrate is used in a liquid crystal display device, it is not necessary to form a black matrix in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.
Furthermore, it is possible to provide an alignment regulating means by leaving the protective insulating layer and the passivation insulating layer in a protruding shape on the pixel electrode, so that the vertical alignment type liquid crystal mode can be supported. That is, the viewing angle can be improved along with the process reduction.
In addition, photosensitive black pigment dispersion resin etc. are mentioned as a material which has light-shielding property.

Preferably, the protective insulating layer in the spacer region is thicker than other regions.
In this case, the protective insulating layer protects and insulates the source wiring and the drain wiring, and also functions as a photo spacer, so that the added value of the display device substrate can be improved. In addition, when this display device substrate is used in a liquid crystal display device, the spacer dispersion step is not required, or it is not necessary to form a photo spacer in the color filter, so the total number of masks in the liquid crystal display device Can be reduced. Accordingly, the manufacturing cost can be reduced.
A halftone exposure technique is used for producing protective insulating layers (photosensitive black pigment dispersed resin patterns) having different thicknesses.

Preferably, a storage capacitor to which the pixel electrode and one electrode are connected, a storage capacitor line connected to the other electrode of the storage capacitor, and a storage capacitor line electrode terminal are formed.
Thus, the gradation of the display image can be improved, and the added value as a display device substrate can be improved.

Preferably, the substrate is transparent and has an insulating property, and the passivation insulating layer is transparent.
In this way, the translucency can be improved, and when used in a liquid crystal display device, the image quality can be improved.

The liquid crystal display device of the present invention includes a display device substrate on which a thin film transistor is formed, a counter substrate or a color filter, and a liquid crystal filled between the display device substrate and the counter substrate or the color filter. In the liquid crystal display device, the display device substrate is the display device substrate according to any one of claims 1 to 9.
As described above, the present invention is also effective as an invention of a liquid crystal display device, and the protective insulating layer protects and insulates the source wiring and drain wiring, and also functions as a black matrix and a photo spacer. It is not necessary to form a black matrix or photo spacer, and the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.
Further, since the halftone exposure technique is not used when forming the channel, it is possible to avoid the problem that the channel length varies as in the conventional example. That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.

In addition, the method for manufacturing a liquid crystal display device according to the present invention includes the step of filling a liquid crystal between a display device substrate on which a thin film transistor is formed and a counter substrate or a color filter. The device substrate is manufactured by using the display device substrate manufacturing method according to any one of claims 10 to 18.
As described above, the present invention is also effective as an invention of a manufacturing method of a liquid crystal display device, and the protective insulating layer protects and insulates the source wiring and the drain wiring, and also functions as a black matrix and a photo spacer. It is not necessary to form a black matrix or a photo spacer in the color filter, and the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.
Further, since the halftone exposure technique is not used when forming the channel, it is possible to avoid the problem that the channel length varies as in the conventional example. That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.

As described above, according to the present invention, a total of four sheets are formed in the forming process of the scanning line, the forming process of the semiconductor layer, the forming process of the source / drain wiring, and the opening forming process to the protective insulating layer. A display device substrate (active substrate) can be manufactured using the photomask.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, by forming a protective insulating layer that also functions as a black matrix or a photo spacer, the total number of manufacturing steps in the liquid crystal display device can be reduced.

[First Embodiment of Display Device Substrate and Manufacturing Method Thereof]
FIG. 1: has shown the schematic flowchart figure for demonstrating the manufacturing method of the board | substrate for display apparatuses which concerns on 1st embodiment of this invention.
2, 4, 6, 8, and 10 are schematic plan views of a unit pixel corresponding to each manufacturing process for explaining a method for manufacturing a display device substrate according to the first embodiment of the present invention. .
3, 5, 7, 9, and 11 are schematic cross-sectional views of a unit pixel corresponding to each manufacturing process for explaining a method for manufacturing a display device substrate according to the first embodiment of the present invention. . (A) of these schematic cross-sectional views shows a cross-sectional view on the AA ′ line (insulated gate type transistor (thin film transistor) region), and (b) shows a cross-sectional view on the BB ′ line (scanning line electrode terminal region). A cross-sectional view is shown, and FIG. 10C is a cross-sectional view on the CC ′ line (signal line electrode terminal region) (see FIG. 10).
The display device substrate of this embodiment includes channel-etched insulated gate transistors (thin film transistors).
In addition, about the site | part same as a prior art example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
In order to streamline the manufacturing process of the pixel electrode, the display device substrate of the present embodiment (first embodiment) and the second embodiment includes a transparent conductive layer and a third metal layer (signal line conductive layer ( It is also referred to as a conductive layer for source / drain wiring. Furthermore, display device substrates having scanning lines made of a laminate of a transparent conductive layer and a first metal layer (gate conductive layer) will be described as third to fifth embodiments.

First, as shown in FIGS. 1, 2, and 3, the gate electrode 11A, the scanning line 11, and the scanning line electrode terminal 5A made of the first metal layer 92 are formed on the glass substrate 2 (step S1).
In other words, a transparent film substrate 2 having a film thickness of about 0.1 to 0.3 μm is formed on one main surface of a transparent glass substrate 2, for example, Corning's product name 1737 using a vacuum film forming apparatus such as SPT. One metal layer (gate conductive layer) 92 is deposited.
The first metal layer 92 may be a single layer metal such as Ti, Ta, Cr, or Mo. In order to reduce resistance, AL (aluminum) or a heat-resistant AL alloy may be used. In order to avoid the battery effect in an alkaline liquid with a transparent conductive layer described later, Mo / AL / Mo or A laminated structure such as AL (Nd) / Mo may be employed. Here, AL (Nd) means a highly heat-resistant AL alloy containing several weight percent or less of Nd, and there is no problem even if an AL alloy containing Ni, Ta, Hf or the like is substituted for Nd. Note that Cu or Cu alloy can be used instead of AL for low resistance.
Subsequently, the scanning electrode 11 connected to the gate electrode 11A, the scanning line electrode terminal 5A, the storage capacitor line 16, and the storage capacitor line electrode terminal 7A are formed by a fine processing technique. The scanning line electrode terminal 5A connected to the scanning line 11 and the storage capacitor line electrode terminal 7A connected to the storage capacitor line 16 are formed in a region outside the image display section.

Next, as shown in FIGS. 1, 4, and 5, the gate insulating layer 30, the first amorphous silicon layer 31, the second amorphous silicon layer 33, and the second metal layer are formed on the glass substrate 2. 34 are sequentially deposited (step S2).
That is, by using a PCVD apparatus over the entire surface of the glass substrate 2, a first SiNx layer as the gate insulating layer 30, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and Then, three types of thin film layers of the second amorphous silicon layer 33 containing impurities and serving as the source and drain of the insulated gate transistor are sequentially covered with a film thickness of, for example, about 0.3-0.2-0.05 μm. To wear. Furthermore, a second metal layer (conductive layer for source / drain electrodes) 34 having a thickness of about 0.1 μm is deposited using a vacuum film forming apparatus such as SPT. Usually, as the second metal layer 34, a heat-resistant metal layer (for example, a thin film layer of Mo, Ti or the like) is used. Note that the second metal layer 34 becomes a source electrode 34S and a drain electrode 34D as described later.

Next, as shown in FIGS. 1, 4, and 5, a stacked body including the first amorphous silicon layer 31, the second amorphous silicon layer 33, and the second metal layer 34 is formed in an island shape. (Step S3).
That is, a stacked body including the second metal layer 34A, the second amorphous silicon layer 33A, and the first amorphous silicon layer 31A is formed above the gate electrode 11A, which is a transistor formation region, by a microfabrication technique. The gate insulating layer 30 is exposed by forming an island shape. The formed island serves as a semiconductor layer region of the insulated gate transistor.

Next, as shown in FIGS. 1, 6, and 7, a transparent conductive layer 91 and a third metal layer 35 are deposited, and a channel 31A, a source electrode 34S, a drain electrode 34D, a source wiring 12S, a signal line 12, a drain The wiring 21, the pseudo pixel electrode P22, and the signal line pseudo electrode terminal P6 are formed (step S4).
That is, in the step of forming source / drain wiring, a transparent film 91 such as SPT is formed on the entire surface of the glass substrate 2 and a transparent conductive layer 91 having a film thickness of about 0.1 μm and a signal line conductive layer (source / drain). A third metal layer 35 is sequentially deposited as a wiring metal layer. Subsequently, the third metal layer 35 and the transparent conductive layer 91 are etched by microfabrication technology, and the second metal layer 34A and the second amorphous silicon 33A are selectively formed with respect to the gate insulating layer 30. Etching is further performed while leaving about 0.05 to 0.1 μm of the first amorphous silicon 31A. Thereby, the channel 31A, the source electrode 34S, and the drain electrode 34D are formed above the gate electrode 11A. Further, by etching the third metal layer 35 and the transparent conductive layer 91 as described above, the source wiring 12S, the signal line 12, and the drain made of a laminate including the transparent conductive layer 91 and the third metal layer 35 are obtained. The wiring 21, the pseudo pixel electrode P22, and the signal line pseudo electrode terminal P6 are formed. The source line 12S is connected to the source electrode 34S and the signal line 12, and the signal line 12 is connected to the signal line pseudo electrode terminal P6. The drain wiring 21 is connected to the drain electrode 34D and the pseudo pixel electrode P22.

  Here, in order to reduce the resistance of the signal line 12, AL is generally used as the third metal layer 35, but the laminated structure of the AL and the transparent conductive layer 91 has an alkaline liquid developer or The transparent conductive layer 91 disappears due to the battery reaction in the resist stripping solution. For this reason, it is necessary to interpose Mo as the buffer metal layer 36 between the AL and the transparent conductive layer. When the restriction on the resistance value of the signal line 12 is not severe, the configuration of the signal line 12 may be simplified by using a heat-resistant metal such as Ti, Cr, or Mo as the third metal layer 35. In a large screen size or high definition liquid crystal display device, AL is usually used for the third metal layer 35 in order to prevent an increase in wiring resistance. Therefore, for example, the laminated structure of the Mo thin film layer as the buffer metal layer 36 having a thickness of about 0.1 μm and the AL thin film layer as the low resistance metal layer having a thickness of about 0.3 μm is selected as the third metal layer 35. Is done. In FIG. 7, the buffer conductive layer 36 included in the third metal layer 35 is illustrated.

  Further, from the viewpoint of reducing the etching cross-section taper and the number of manufacturing steps, as described above, the third metal layer 35 (Mo thin film layer and AL thin film is formed by using a mixed acid which is a phosphoric acid solution to which an appropriate amount of nitric acid is added. It is desirable that the transparent conductive layer 91 can be etched following the layer. However, the transparent conductive layer 91 needs to be resistant against being etched with respect to the mixed acid so that the transparent conductive layer 91 is not lost in the pixel electrode exposing step described later. In this case, it is preferable to use the transparent conductive layer 91 whose film quality is changed by a heat treatment at about 250 ° C. in the step of forming the protective insulating layer 90 to be described later. In this case, the above problem can be avoided.

As the transparent conductive layer 91 having such properties, ITZO (In ₂ O ₃ —SnO ₂ —ZnO) having a crystallization temperature as low as 200 ° C. can be given. For example, an ITZO film having an ITZO composition ratio (wt%) of a sputtering target of 85: 10: 5 is subjected to a heat treatment at 250 ° C., which is a post-baking temperature of a black pigment dispersion resin that is a protective insulating layer 90, and the film quality is improved. It changes from amorphous to microcrystalline. This ITZO film is a very unique material that is resistant to the mixed acid in the pixel electrode exposure step. Therefore, when an ITZO film having an ITZO composition ratio (wt%) of 85: 10: 5 is used for the sputter target, the transparent conductive layer 91 is etched when the third metal layer 35 is etched using a mixed acid in the source / drain wiring formation process. Can be simultaneously etched to reduce the number of manufacturing steps.

Next, as shown in FIGS. 1, 8, and 9, a transparent insulating passivation insulating layer 37 is deposited on the glass substrate 2 (step S5).
That is, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating passivation insulating layer 37 using a PCVD apparatus. As a result, the second SiNx layer functions as a passivation insulating layer 37 and protects the first amorphous silicon 31A, which is the channel of the insulated gate transistor, from the outside air.

Next, as shown in FIGS. 1, 8, and 9, a protective insulating layer 90 having an opening is formed (step S6).
That is, first, as shown in FIGS. 8 and 9, a photosensitive black pigment dispersion resin having a thickness of 1 μm or more is applied as a protective insulating layer 90 on the entire surface of the glass substrate 2, followed by exposure and development. Do. Thereby, the pixel electrode opening 38 and the electrode terminal opening of the scanning line 11 are respectively formed on the pseudo pixel electrode P22, the scanning line electrode terminal 5A, the signal line pseudo electrode terminal P6, and the storage capacitor line electrode terminal 7A. 63, a protective insulating layer 90 having an electrode terminal opening 64 of the signal line 12 and an electrode terminal opening 65 of the storage capacitor line 16 is formed.

Next, as shown in FIGS. 1, 8, and 9, the signal line pseudo electrode terminal P6 and the pseudo pixel electrode P22 are exposed (step S7).
That is, using the photosensitive black pigment dispersed resin as the protective insulating layer 90 as a mask, the passivation insulating layer 37 in each of the openings 38, 63, 64, 65 is selectively removed, and each of the pseudo pixel electrodes P22 is placed in each of the openings. The gate insulating layer 30, the signal line pseudo electrode terminal P6, and the gate insulating layer 30 are exposed.

Next, as shown in FIGS. 1, 8, and 9, the signal line electrode terminal 6A and the pixel electrode 22 made of the transparent conductive layer 91 are exposed (step S8).
That is, using the photosensitive black pigment dispersed resin as the protective insulating layer 90 as a mask, the opening 38 and the third metal layer 35 (and the buffer metal layer 36) in the opening 64 are selectively removed to form a transparent conductive layer. The pixel electrode 22 composed of 91 and the signal line electrode terminal 6A are exposed. Here, the ITZO film having the ITZO composition ratio (wt%) of 85: 10: 5, which is the transparent conductive layer 91, is given crystallinity by the heat treatment received during the formation of the passivation insulating layer 37. Even if the third metal layer 35 (Mo thin film layer and AL thin film layer) is removed, there is no fear that the pixel electrode 22 and the signal line electrode terminal 6A are reduced or disappear.

Next, as shown in FIGS. 1, 10, and 11, the scanning line electrode terminal 5A made of the first metal layer 92 is exposed (step S9).
That is, using the photosensitive black pigment dispersion resin 90 as a mask, the gate insulating layer 30 in the openings 63 and 65 is selectively removed, and the scanning lines for the scanning line made of the first metal layer 92 are formed in the openings 63 and 65, respectively. The electrode terminal 5A and the storage capacitor line electrode terminal 7A are exposed.
In step S8, when the third metal layer 35 is removed using the mixed acid, the scanning line electrode terminal 5A and the storage capacitor line electrode terminal 7A are covered with the gate insulating layer 30. It is not removed by the mixed acid. In step S9, when the gate insulating layer 30 is removed, the transparent conductive pixel electrode 22 and the transparent conductive signal line electrode terminal 6A are resistant to the etching gas of the gate insulating layer 30. Problems such as a decrease in film thickness are avoided. Further, when a metal thin film such as Ti or Cr that is resistant to mixed acid is selected as the first metal layer 92, the passivation insulating layer 37 and the gate insulating layer 30 in the opening 63 are penetrated and removed at a stroke. Thereafter, it is possible to selectively remove the opening 38 and the third metal layer 35 in the opening 64 to expose the transparent conductive pixel electrode 22 and the signal line electrode terminal 6A.
Note that the configuration of the storage capacitor 15 is configured such that the pixel electrode 22, the pseudo pixel electrode P22, and the storage capacitor line 16 overlap in plan via the gate insulating layer 30, as shown in FIGS. (The storage capacitor formation region 52 is a hatched portion with a downward-sloping line by a dotted line).

As described above, according to the method for manufacturing the display device substrate 2A of the present embodiment, the scanning line 11 and the like forming process, the semiconductor layer forming process, the source / drain wiring forming process, and the protective insulating layer In the opening forming step to 90, a display device substrate can be manufactured using a total of four photomasks.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2A is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.
In the present embodiment, the scanning line electrode terminal 5A and the signal line electrode terminal 6A are not connected by a conductive member. Therefore, for example, countermeasures against static electricity are required in processes after panel assembly and electrical inspection.

Moreover, this embodiment has various application examples.
Next, an application example of the first embodiment will be described with reference to the drawings.
For example, in the above embodiment, a negative photosensitive black pigment dispersion resin (this resin is usually used for BM of a CF substrate) is used as the protective insulating layer 90. Halftone exposure technology may be used in combination with the developed positive photosensitive black pigment dispersion resin. In this way, as shown in FIGS. 12 and 13, pixel electrode openings are respectively formed on the pixel electrode P22, the scanning line electrode terminal 5A, the signal line pseudo electrode terminal P6, and the storage capacitor line electrode terminal 7A. 38 and the electrode terminal openings 63, 64, 65, and the photosensitive black pigment dispersed resin pattern 85A such that the spacer arrangement region 85A has a thickness of 3 μm, for example, and the other region 85B has a thickness of 1 μm, for example. , 85B can be formed. Using the photosensitive black pigment dispersed resin patterns 85A and 85B as a mask, the passivation insulating layer 37, the third metal layer 35 (and the buffer conductive layer 36) and the gate insulating layer 30 in each opening are selectively selected as described above. The transparent conductive pixel electrode 22, the scanning line electrode terminal 5A and the storage capacitor line electrode terminal 7A, and the transparent conductive signal line electrode terminal 6A are exposed. In addition, the spacer arrangement area 85A is an area that does not hinder image display within the pixel. For example, the spacer arrangement area 85A is arranged on the signal line 12 as shown in FIG. Good.

When the display device substrate 2A ′ thus obtained and the color filter 9 not incorporating BM are bonded to form a liquid crystal panel, a photo spacer (dispersed photosensitive black pigment dispersion) is formed on the display device substrate 2A ′. Since the resin pattern 85A) is formed, there is no need for the spacer dispersion step in the panel assembling step, or there is no need to form the spacer on the CF substrate. Reduction is further promoted, and it becomes easier to lower the manufacturing cost of the liquid crystal display device.
In addition, since the BM is formed on the display device substrate 2A ′, the relative positional deviation in the pasting of the display device substrate and the CF substrate as in the past is automatically absorbed and the aperture ratio is also automatically adjusted. A secondary effect is also obtained.

The present invention is also effective as an invention of a display device substrate.
The display device substrate 2A of the first embodiment is a display device substrate manufactured by the first embodiment of the display device substrate manufacturing method described above (see FIGS. 10 and 11).
The display device substrate 2A is a display device substrate having a channel etch type insulated gate transistor, and includes a gate electrode 11A, a scanning line 11, a gate insulator 30, a channel 31A, a source electrode 34S, a source wiring 12S, a signal. A line 12, a drain electrode 34D, a drain wiring 21, a pixel electrode 22, a passivation insulating layer 37, a protective insulating layer 90, and the like are provided.

The gate electrode 11 </ b> A, the scanning line 11, and the scanning line electrode terminal 5 </ b> A are formed of a gate conductive layer (first metal layer 92) deposited on one main surface of the glass substrate 2.
The gate insulating layer 30 is deposited on the glass substrate 2, the gate electrode 11A, the scanning line 11, and the scanning line electrode terminal 5A.
Further, the channel 31A, the source electrode 34S, and the drain electrode 34D are sequentially deposited following the gate insulating layer 30, and are formed on the gate electrode 11A in an island shape so as not to contain impurities. , A multilayer body including a second amorphous silicon layer 33 containing impurities and a source / drain electrode conductive layer (second metal layer 34). That is, the channel 31A, the source electrode 34S, and the drain electrode 34D are formed from the multilayer body using the normal exposure technique (without using the halftone exposure technique), the second metal layer 34, and the second amorphous layer. The silicon layer 33 and the first amorphous silicon layer 31 are formed by removing a part thereof.

  The source line 12S, the signal line 12, the signal line pseudo electrode terminal P6, the drain line 21 and the pseudo pixel electrode P22 include the source / drain electrode conductive layer (second metal layer 34) and gate formed in the island shape. From a multilayer body including a transparent conductive layer 91 and a signal line conductive layer (third metal layer 35) sequentially deposited on the insulating layer 30, using a normal exposure technique (without using a halftone exposure technique) ), By removing the third metal layer 35 and the transparent conductive layer 91. Note that the resist used at this time is a resist used when forming the channel 31A, the source electrode 34S, and the drain electrode 34D.

The passivation insulating layer 37 and the protective insulating layer 90 are formed with a channel 31A, a source electrode 34S, a source wiring 12S, a signal line 12, a signal line electrode terminal P6, a drain electrode 34D, a drain wiring 21, a pseudo pixel electrode P22, and the like. The glass substrate 2 is sequentially deposited.
The passivation insulating layer 37 and the protective insulating layer 90 are formed on the pixel electrode opening 38 on the pseudo pixel electrode P22, the electrode terminal opening 63 on the scanning line electrode terminal 5A, and the signal line pseudo electrode terminal P6. An electrode terminal opening 64 is formed.
Further, the pixel electrode 22 and the signal line electrode terminal 6A are made of the transparent conductive layer 91, and are exposed by removing the third metal layer 35 from the pseudo pixel electrode P22 and the signal line pseudo electrode terminal P6. ing.
The scanning line electrode terminal 5 </ b> A is exposed when the electrode terminal opening 63 is formed in the gate insulating layer 30.

The protective insulating layer 90 is an insulating layer having a light shielding property (a layer made of a photosensitive black pigment dispersed resin).
In this manner, the protective insulating layer 90 protects and insulates the source wiring 12S and the drain wiring 21 and also functions as a black matrix, so that the added value of the display device substrate can be improved. Further, when this display device substrate 2A is used in a liquid crystal display device, it is not necessary to form a black matrix in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

Further, the pseudo pixel electrode P22 and the like are formed from a laminate of the transparent conductive layer 91 and the third metal layer 35, and further, after forming the protective insulating layer 90, the third metal layer 35 in the opening is selected. Thus, the signal line electrode terminal 6A and the pixel electrode 22 made of the transparent conductive layer 91 are exposed.
Thus, the conductivity and translucency can be improved, and the performance as a display device substrate can be improved.
Furthermore, since the glass substrate 2 is transparent and has an insulating property, and the passivation insulating layer 37 is transparent, the translucency can be improved, and when used in a liquid crystal display device, Image quality can be improved.

Preferably, the storage capacitor line 16 or the like may be formed and the storage capacitor forming region 52 may be provided. Thus, the gradation of the display image can be improved, and the added value as a display device substrate can be improved.
The storage capacitor formation region 52 of the present embodiment forms a storage capacitor by planarly overlapping the pixel electrode 22 and the storage capacitor line 16 via the gate insulating layer 30, but the storage capacitor forming region 52 is limited to this. It is not a thing. For example, the storage capacitor may be configured by overlapping the pixel electrode 22 (or the storage electrode connected to the pixel electrode 22) and the preceding scanning line 11 via the gate insulating layer 30.

As described above, the display device substrate 2A of the present embodiment can be manufactured by a four-mask process.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2A is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.

Moreover, this embodiment has various application examples.
The display device substrate 2A ′ according to the application example of the first embodiment is a display device substrate manufactured according to the application example of the first embodiment of the method for manufacturing a display device substrate described above (see FIGS. 12 and 13). ).
That is, the protective insulating layer 90 in the spacer region is preferably made thicker than other regions, and the photosensitive black pigment dispersed resin pattern 85A is used as a photo spacer.
In this way, the protective insulating layer 90 protects and insulates the source wiring 12S, the drain wiring 21 and the like, and also functions as a photo spacer, so that the added value of the display device substrate 2A ′ can be improved. Further, when the display device substrate 2A ′ is used in a liquid crystal display device, it is not necessary to form a photo spacer on the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

[Second Embodiment of Display Device Substrate and Manufacturing Method Thereof]
FIG. 14: has shown the schematic flowchart figure for demonstrating the manufacturing method of the board | substrate for display apparatuses which concerns on 2nd embodiment of this invention.
FIGS. 15, 17, 19, 21, and 23 are schematic plan views of unit pixels corresponding to each manufacturing process, for explaining a method for manufacturing a display device substrate according to the second embodiment of the present invention. .
Further, FIGS. 16, 18, 20, 22, and 24 are schematic cross-sectional views of unit pixels corresponding to respective manufacturing steps for explaining a method for manufacturing a display device substrate according to the second embodiment of the present invention. . In these schematic cross-sectional views, (a) shows a cross-sectional view on the AA ′ line (insulated gate transistor (thin film transistor) region), and (b) shows a cross-sectional view on the BB ′ line (scanning line electrode terminal region). A cross-sectional view is shown, and FIG. 23C is a cross-sectional view on the line CC ′ (signal line electrode terminal region) (see FIG. 23).
The display device substrate of this embodiment includes channel-etched insulated gate transistors (thin film transistors).
In addition, about the site | part same as the said embodiment and application example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

First, as shown in FIGS. 14, 15 and 16, the gate electrode 11A, the scanning line 11, and the scanning line pseudo electrode terminal P5 made of the first metal layer 92 are formed on the glass substrate 2 (step S11).
In other words, a transparent film substrate 2 having a film thickness of about 0.1 to 0.3 μm is formed on one main surface of a transparent glass substrate 2, for example, Corning's product name 1737 using a vacuum film forming apparatus such as SPT. One metal layer (gate conductive layer) 92 is deposited.
Subsequently, the scanning electrode 11 connected to the gate electrode 11A, the scanning line pseudo electrode terminal P5, the storage capacitor line 16 and the storage capacitor line pseudo electrode terminal P7 are formed by a fine processing technique. The scanning line pseudo electrode terminal P5 connected to the scanning line 11 and the storage capacitor line pseudo electrode terminal P7 connected to the storage capacitor line 16 are formed in a region outside the image display unit.

Next, as shown in FIGS. 14, 17, and 18, the gate insulating layer 30, the first amorphous silicon layer 31, the second amorphous silicon layer 33, and the second metal layer are formed on the glass substrate 2. 34 are sequentially deposited (step S12).
This step S12 is substantially the same as step S2 in the first embodiment.

Next, as shown in FIGS. 14, 17, and 18, a stacked body including the gate insulating layer 30, the first amorphous silicon layer 31, the second amorphous silicon layer 33, and the second metal layer 34 is formed. Then, it is formed widely on the gate electrode 11A and the scanning line 11 (step S13).
That is, the gate insulating layer 30, the first amorphous silicon layer 31, the second amorphous silicon layer 33, and the second metal layer 34 are included on the gate electrode 11A, the scanning line 11, and the storage capacitor line 16. The stacked body is formed wider than the gate electrode 11A, the scanning line 11, and the storage capacitor line 16, and the scanning line pseudo electrode terminal P5, the storage capacitor line pseudo electrode terminal P7, and the glass substrate 2 are exposed.
Thereby, the gate electrode 11 </ b> A, the scanning line 11, and the storage capacitor line 16 are covered with the gate insulating layer 30 on the top and side surfaces. Further, a semiconductor layer made of a stacked body including a gate insulating layer 30A, a first amorphous silicon layer 31A, and a second amorphous silicon layer 33A on the gate electrode 11A, the scanning line 11, and the storage capacitor line 16. The region and the second metal layer 34A are formed.

When the second metal layer 34A, the semiconductor layer region, and the gate insulating layer 30A are formed, the second metal layer 34, the second amorphous silicon layer 33, and the second amorphous silicon layer 33 that are not covered with a resist (not shown) are formed. The one amorphous silicon layer 31 and the gate insulating layer 30 are removed by an etchant (etching solution or etching gas).
In this removal, when the second metal layer (heat-resistant metal layer) 34 is Mo (or Ti), the second metal layer 34 is dry-etched using a fluorine-based (chlorine-based in the case of Ti) gas. Then, the second amorphous silicon layer 33, the first amorphous silicon layer 31, and the gate insulating layer 30 are removed by dry etching using a fluorine-based gas. When the first metal layer 92 is Mo, Ti, Ta, the first metal layer 92 is subsequently removed by dry etching using a fluorine-based gas or a chlorine-based gas. When the first metal layer 92 is Cr, the first metal layer 92 is removed using a dedicated etching solution. Further, when the first metal layer 92 is a laminated body such as Mo / AL / Mo or AL (Nd) / Mo, the first metal layer 92 uses a mixed acid obtained by adding several percent by weight of nitric acid to phosphoric acid. , Removed by wet etching.

  At this time, the etching is for a multilayer film including the second metal layer 34, the second amorphous silicon layer 33, the first amorphous silicon layer 31, the gate insulating layer 30, and the first metal layer 92. In order to prevent an increase in the number of manufacturing steps, considerable consideration is required in selecting materials for the second metal layer 34 and the first metal layer 92 and employing an etching method. In addition, in order to avoid a short circuit of the multilayer wiring with the signal line through a transparent insulating layer described later, it is necessary to pay attention so that the cross-sectional shape of the multilayer film does not become a reverse taper (see FIG. 18).

Next, as shown in FIGS. 14, 19, and 20, the transparent conductive layer 91 and the third metal layer 35 are deposited, and the channel 31A, the source electrode 34S, the drain electrode 34D, the source wiring 12S, the signal line 12, the drain The wiring 21, the pseudo pixel electrode P22, the scanning line pseudo electrode terminal P5 ′, and the signal line pseudo electrode terminal P6 are formed (step S14).
That is, in the step of forming source / drain wiring, a transparent film 91 such as SPT is formed on the entire surface of the glass substrate 2 and a transparent conductive layer 91 having a film thickness of about 0.1 μm and a signal line conductive layer (source / drain). A third metal layer 35 is sequentially deposited as a wiring metal layer. Subsequently, the third metal layer 35 and the transparent conductive layer 91 are etched by the microfabrication technique, the second metal layer 34A and the second amorphous silicon 33A are etched, and the first amorphous layer is further etched. The quality silicon 31A is etched to leave about 0.05 to 0.1 μm. Thereby, the channel 31A, the source electrode 34S, and the drain electrode 34D are formed above the gate electrode 11A. Further, by etching the third metal layer 35 and the transparent conductive layer 91 as described above, the source wiring 12S, the signal line 12, and the drain made of a laminate including the transparent conductive layer 91 and the third metal layer 35 are obtained. A wiring 21, a pseudo pixel electrode P22, a scanning line pseudo electrode terminal P5 ′, a signal line pseudo electrode terminal P6, and a storage capacitor line pseudo electrode terminal P7 ′ are formed.
The scanning line pseudo electrode terminal P5 ′ and the storage capacitor line pseudo electrode terminal P7 ′ are formed on the scanning line pseudo electrode terminal P5 and the storage capacitor line pseudo electrode terminal P7, respectively. The detailed contents of the transparent conductive layer 91 and the third metal layer 35 are as described in the first embodiment.

Next, as shown in FIGS. 14, 21, and 22, a transparent insulating passivation insulating layer 37 is deposited on the glass substrate 2 (step S15).
That is, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating passivation insulating layer 37 using a PCVD apparatus. As a result, the second SiNx layer functions as a passivation insulating layer 37 and protects the first amorphous silicon 31A, which is the channel of the insulated gate transistor, from the outside air.

Next, as shown in FIGS. 14, 21, and 22, a protective insulating layer 90 having an opening is formed (step S16).
That is, first, as shown in FIGS. 21 and 22, a photosensitive black pigment dispersion resin having a thickness of 1 μm or more is applied as a protective insulating layer 90 on the entire surface of the glass substrate 2, followed by exposure and development. Do. Thereby, the pixel electrode opening 38 and the scanning are respectively formed on the pseudo pixel electrode P22, the scanning line pseudo electrode terminal P5 ′, the signal line pseudo electrode terminal P6, the storage capacitor line pseudo electrode terminal P7 ′, and the scanning line 11. A protective insulating layer 90 having an electrode terminal opening 63 of the line 11, an electrode terminal opening 64 of the signal line 12, an electrode terminal opening 65 of the storage capacitor line 16 and a parasitic transistor prevention opening 67 is formed.
The protective insulating layer 90 also has an opening for exposing the transparent conductive layer pattern 40.

Next, as shown in FIGS. 14, 21, and 22, the scanning line pseudo-electrode terminal P5 ′, the signal line pseudo-electrode terminal P6, the pseudo pixel electrode P22, and the first amorphous silicon layer 31A are exposed (steps). S17).
That is, the passivation insulating layer 37 in each of the openings 38, 63, 64, 65, and 67 is selectively removed using the photosensitive black pigment dispersed resin as the protective insulating layer 90 as a mask, and a pseudo pixel is formed in each of the openings. The electrode P22, the scanning line pseudo electrode terminal P5 ′, the signal line pseudo electrode terminal P6, the storage capacitor line pseudo electrode terminal P7 ′, and the first amorphous silicon layer 31A are exposed.

Next, as shown in FIGS. 14, 21, and 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the pixel electrode 22 made of the transparent conductive layer 91 are exposed (step S18).
That is, the third metal layer 35 (Mo thin film layer and AL thin film layer) in the openings 38, 63, 64, 65 is selectively removed using the photosensitive black pigment dispersed resin as the protective insulating layer 90 as a mask. The pixel electrode 22 made of the transparent conductive layer 91, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the storage capacitor line electrode terminal 7A are exposed. Here, the ITZO film having the ITZO composition ratio (wt%) of 85: 10: 5, which is the transparent conductive layer 91, is given crystallinity by the heat treatment received during the formation of the passivation insulating layer 37. Even if the third metal layer 35 (Mo thin film layer and AL thin film layer) is removed, the pixel electrode 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the storage capacitor line electrode terminal 7A are reduced in film thickness. There is no fear of disappearing.

Next, as shown in FIGS. 14, 23, and 24, the first amorphous silicon layer 31A in the parasitic transistor preventing opening 67 is selectively removed to expose the gate insulating layer 30 (step S19). .
That is, using the photosensitive black pigment dispersion resin 90 as a mask, the first amorphous silicon layer 31A in the parasitic transistor preventing opening 67 is selectively removed, and the gate insulating layer 30A is exposed in the opening 67. . In this way, unnecessary first amorphous silicon 31A in the opening 67 is removed, and generation of a parasitic transistor can be prevented.
As shown in FIG. 23, the configuration of the storage capacitor 15 is configured such that the pixel electrode 22, the pseudo pixel electrode P22, and the storage capacitor line 16 overlap in a plan view with the gate insulating layer 30 interposed therebetween. (The storage capacitor formation region 52 is a hatched portion with a downward-sloping line by a dotted line).
As a countermeasure against static electricity, the scanning line pseudo electrode terminal P5 ′, the signal line pseudo electrode terminal P6, and the storage capacitor line electrode terminal P7 ′ are connected to each other, and include a third metal layer 35 and a transparent conductive layer 91. An antistatic pattern is formed, and then a transparent conductive layer pattern 40 obtained by removing the third metal layer 35 is formed. As a result, it is possible to take a countermeasure against static electricity that is almost equivalent to that of the conventional example.

As described above, according to the method for manufacturing the display device substrate 2B of the present embodiment, the scanning line 11 and the like forming process, the semiconductor layer forming process, the source / drain wiring forming process, and the protective insulating layer In the opening forming step to 90, a display device substrate can be manufactured using a total of four photomasks.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2B is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.

Moreover, this embodiment has various application examples.
Next, an application example of the second embodiment will be described with reference to the drawings.
For example, in the above embodiment, a negative photosensitive black pigment dispersion resin (this resin is usually used for BM of a CF substrate) is used as the protective insulating layer 90. Halftone exposure technology may be used in combination with the developed positive photosensitive black pigment dispersion resin. In this way, as shown in FIGS. 25 and 26, the pixel electrode 22, the scanning line electrode terminal 5 </ b> A, the signal line electrode terminal 6 </ b> A, the storage capacitor line electrode terminal 7 </ b> A, and the scanning line 11, respectively. For example, the spacer arrangement region 85A has a thickness of 3 μm and the other region 85B has a thickness of 1 μm, for example. Such photosensitive black pigment dispersed resin patterns 85A and 85B can be formed. Using the photosensitive black pigment dispersed resin patterns 85A and 85B as a mask, the passivation insulating layer 37, the third metal layer 35 and the first amorphous silicon layer 31 in each opening are selectively removed as described above. Thus, the transparent conductive pixel electrode 22, the transparent conductive scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the storage capacitor line electrode terminal 7A are exposed. The spacer arrangement region 85A is formed in a region (region other than the pixel electrode) that does not hinder image display in the pixel.

When the display device substrate 2B ′ thus obtained and the color filter 9 not incorporating BM are bonded to form a liquid crystal panel, a photo spacer (dispersed photosensitive black pigment dispersion) is formed on the display device substrate 2B ′. Since the resin pattern 85A) is formed, there is no need for the spacer dispersion step in the panel assembling step, or it is not necessary to form the spacer on the CF substrate. Therefore, the number of manufacturing steps is smaller than that of the conventional liquid crystal display device. Reduction is further promoted, and it becomes easier to lower the manufacturing cost of the liquid crystal display device.
Further, since the BM is formed on the display device substrate 2B ′, the relative positional shift in the pasting of the display device substrate and the CF substrate as in the past is automatically absorbed and the aperture ratio is also automatically adjusted. A secondary effect is also obtained.

The present invention is also effective as an invention of a display device substrate.
The display device substrate 2B of the second embodiment is a display device substrate manufactured by the second embodiment of the display device substrate manufacturing method described above (see FIGS. 23 and 24).
The display device substrate 2B is a display device substrate having a channel etch type insulated gate transistor, and includes a gate electrode 11A, a scanning line 11, a gate insulator 30A, a channel 31A, a source electrode 34S, a source wiring 12S, a signal. A line 12, a drain electrode 34D, a drain wiring 21, a pixel electrode 22, a passivation insulating layer 37, a protective insulating layer 90, and the like are provided.

The gate electrode 11 </ b> A, the scanning line 11, and the scanning line electrode terminal 5 </ b> A are formed of a gate conductive layer (first metal layer 92) deposited on one main surface of the glass substrate 2.
The gate insulating layer 30 </ b> A is formed on the gate electrode 11 </ b> A and the scanning line 11 so as to be wider than the gate electrode 11 </ b> A and the scanning line 11. Thereby, the upper surfaces and side surfaces of the gate electrode 11A and the scanning line 11 are covered with the gate insulating layer 30A.
Furthermore, the channel 31A, the source electrode 34S, and the drain electrode 34D are sequentially deposited following the gate insulating layer 30, and are formed on the gate electrode 11A so as to be wider than the gate electrode 11A and do not contain impurities. It is formed from a multilayer body including a layer 31, a second amorphous silicon layer 33 containing impurities, and a source / drain electrode conductive layer (second metal layer 34). That is, the channel 31A, the source electrode 34S, and the drain electrode 34D are formed from the multilayer body using the normal exposure technique (without using the halftone exposure technique), the second metal layer 34, and the second amorphous layer. The silicon layer 33 and the first amorphous silicon layer 31 are formed by removing a part thereof.

  The source wiring 12S, the signal line 12, the signal line pseudo electrode terminal P6, the scanning line pseudo electrode terminal P5 ', the drain wiring 21 and the pseudo pixel electrode P22 are a source / drain electrode conductive layer (second metal layer 34). And a multilayer body including a transparent conductive layer 91 and a signal line conductive layer (third metal layer 35) sequentially deposited on the glass substrate 2, using a normal exposure technique (using a halftone exposure technique) Not), and is formed by removing the third metal layer 35 and the transparent conductive layer 91. Note that the resist used at this time is a resist used when forming the channel 31A, the source electrode 34S, and the drain electrode 34D.

The passivation insulating layer 37 and the protective insulating layer 90 include the channel 31A, the source electrode 34S, the source wiring 12S, the signal line 12, the signal line pseudo electrode terminal P6, the scanning line pseudo electrode terminal P5 ', the drain electrode 34D, and the drain wiring 21. And it is sequentially deposited on the glass substrate 2 on which the pseudo pixel electrode P22 and the like are formed.
In addition, the passivation insulating layer 37 and the protective insulating layer 90 are formed of the pixel electrode opening 38 on the pseudo pixel electrode P22, the parasitic transistor preventing opening 67 on the scanning line 11, and the electrode on the scanning line pseudo electrode terminal P5 ′. An electrode terminal opening 64 on the terminal opening 63 and the signal line pseudo electrode terminal P6 is formed.
Further, the pixel electrode 22, the scanning line electrode terminal 5 </ b> A, and the signal line electrode terminal 6 </ b> A are made of a transparent conductive layer 91, and the pseudo pixel electrode P <b> 22, the scanning line pseudo electrode terminal P <b> 5 ′, and the signal line pseudo electrode terminal P <b> 6. The third metal layer 35 is removed and exposed.

The protective insulating layer 90 is an insulating layer having a light shielding property (a layer made of a photosensitive black pigment dispersed resin).
In this manner, the protective insulating layer 90 protects and insulates the source wiring 12S and the drain wiring 21 and also functions as a black matrix, so that the added value of the display device substrate can be improved. Further, when this display device substrate 2B is used in a liquid crystal display device, it is not necessary to form a black matrix in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

Further, the pseudo pixel electrode P22 and the like are formed from a laminate of the transparent conductive layer 91 and the third metal layer 35, and further, after forming the protective insulating layer 90, the third metal layer 35 in the opening is selected. The pixel electrode 22 made of the transparent conductive layer 91 and the like are exposed.
Thus, the conductivity and translucency can be improved, and the performance as a display device substrate can be improved.
Further, the first amorphous silicon layer 31 </ b> A in the parasitic transistor preventing opening 67 is selectively removed, and the gate insulating layer 30 </ b> A is exposed in the opening 67. In this way, unnecessary first amorphous silicon 31A in the opening 67 is removed, and generation of a parasitic transistor can be prevented.
Further, since the glass substrate 2 is transparent and has an insulating property, and the passivation insulating layer 37 is transparent, the translucency can be improved, and when used in a liquid crystal display device, Image quality can be improved.

Preferably, the storage capacitor line 16 or the like may be formed and the storage capacitor forming region 52 may be provided. Thus, the gradation of the display image can be improved, and the added value as a display device substrate can be improved.
The storage capacitor formation region 52 of the present embodiment forms a storage capacitor by planarly overlapping the pixel electrode 22 and the storage capacitor line 16 via the gate insulating layer 30, but the storage capacitor forming region 52 is limited to this. It is not a thing. For example, the storage capacitor may be configured by overlapping the pixel electrode 22 (or the storage electrode connected to the pixel electrode 22) and the preceding scanning line 11 via the gate insulating layer 30.

As described above, the display device substrate 2B of this embodiment can be manufactured by a four-mask process.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2B is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.

Moreover, this embodiment has various application examples.
The display device substrate 2B ′ according to the application example of the second embodiment is a display device substrate manufactured by the application example of the second embodiment of the method for manufacturing the display device substrate described above (see FIGS. 25 and 26). ).
That is, the protective insulating layer 90 in the spacer region is preferably made thicker than other regions, and the photosensitive black pigment dispersed resin pattern 85A is used as a photo spacer.
In this case, the protective insulating layer 90 protects and insulates the source wiring 12S, the drain wiring 21, and the like, and also functions as a photo spacer, so that the added value of the display device substrate 2B ′ can be improved. Further, when this display device substrate 2B ′ is used in a liquid crystal display device, it is not necessary to form a photo spacer in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

[Third embodiment of display device substrate and manufacturing method thereof]
FIG. 27 is a schematic flowchart for explaining a method for manufacturing a display device substrate according to the third embodiment of the present invention.
FIGS. 28, 30, 32, 34, 36, and 38 are schematic plan views of unit pixels corresponding to respective manufacturing steps for explaining a method for manufacturing a display device substrate according to the third embodiment of the present invention. It is.
Furthermore, FIGS. 29, 31, 33, 35, 37, and 39 are schematic cross-sectional views of unit pixels corresponding to respective manufacturing steps for explaining a method for manufacturing a display device substrate according to the third embodiment of the present invention. It is. In these schematic cross-sectional views, (a) shows a cross-sectional view on the AA ′ line (insulated gate transistor (thin film transistor) region), and (b) shows a cross-sectional view on the BB ′ line (scanning line electrode terminal region). A sectional view is shown, and (c) shows a sectional view on the line CC ′ (signal line electrode terminal region) (see FIG. 38).
The display device substrate of this embodiment includes channel-etched insulated gate transistors (thin film transistors).
In addition, about the site | part same as the said embodiment and application example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

First, as shown in FIGS. 27, 28, and 29, on a glass substrate 2, a gate electrode 11A made of a laminate including a transparent conductive layer 91 and a first metal layer 92, a scanning line 11, and a scanning line pseudo-electrode terminal. 94, the pseudo pixel electrode 93 and the signal line pseudo electrode terminal 95 are formed (step S21).
That is, a transparent conductive layer 91 having a film thickness of about 0.1 μm is formed on a transparent and insulating glass substrate 2, for example, on one main surface of a product name 1737 manufactured by Corning using a vacuum film forming apparatus such as SPT. A first metal layer 92 is deposited as a gate conductive layer having a thickness of about 0.1 to 0.3 μm.
The first metal layer 92 is as described in the first embodiment. However, in order to reduce the resistance of the scanning line 11 and prevent the battery reaction with the transparent conductive layer 91, Mo / AL / Mo or A laminated structure such as Mo / AL (Nd) is optimal.
As for the transparent conductive layer 91, as described above, an ITZO film having an ITZO composition ratio (wt%) of a sputtering target of 85: 10: 5 may be used. In this case, when the first metal layer 92 is etched using the mixed acid, the transparent conductive layer 91 is also etched at the same time, so that the number of manufacturing steps can be reduced. In addition, the shape control of the laminated cross section becomes easy.

Subsequently, the gate electrode 11A, the scanning line 11 connected to the gate electrode 11A, the pseudo electrode terminal for scanning line 94, the pseudo pixel electrode 93, the pseudo electrode terminal for signal line 95, the storage capacitor line 16 and the storage by the fine processing technique. A capacitance line pseudo electrode terminal 96 is formed.
Note that the scanning line pseudo electrode terminal 94 connected to the scanning line 11, the storage capacitor line pseudo electrode terminal 96 and the signal line pseudo electrode terminal 95 connected to the storage capacitor line 16 are located outside the image display area. It is formed.
In addition, the pseudo pixel electrode 93 of the present embodiment is formed to face two locations on both sides of the storage capacitor line 16.

Next, as shown in FIGS. 27, 30, and 31, a gate insulating layer 30A, a first amorphous silicon layer 31A, and a second amorphous silicon layer 33A are sequentially deposited on the glass substrate 2 (see FIG. Step S22).
That is, by using a PCVD apparatus over the entire surface of the glass substrate 2, a first SiNx layer as the gate insulating layer 30, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and Then, three types of thin film layers of the second amorphous silicon layer 33 containing impurities and serving as the source and drain of the insulated gate transistor are sequentially covered with a film thickness of, for example, about 0.3-0.2-0.05 μm. To wear.

Next, as shown in FIGS. 27, 30, and 31, the stacked body including the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A is converted into the gate electrode 11A and the scanning line. 11 is formed widely on step 11 (step S23).
That is, a stacked body including the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A on the gate electrode 11A and the scanning line 11 is formed into the gate electrode 11A and the scanning line 11. Form wider. Further, a stacked body including the gate insulating layer 30 </ b> B, the first amorphous silicon layer 31 </ b> B, and the second amorphous silicon layer 33 </ b> B is formed on the storage capacitor line 16 wider than the storage capacitor line 16. Thus, the scanning line pseudo electrode terminal 94, the pseudo pixel electrode 93, the signal line pseudo electrode terminal 95, the storage capacitor line pseudo electrode terminal 96, and the glass substrate 2 are exposed. Further, the gate electrode 11 </ b> A, the scanning line 11, and the storage capacitor line 16 are covered with the gate insulating layer 30 on the upper surface and side surfaces.

Next, as shown in FIGS. 27, 32, and 33, the scanning line electrode terminal 5A, the pixel electrode 22, and the signal line electrode terminal 6A made of the transparent conductive layer 91 are exposed (step S24).
That is, the first metal layers 92A to 92C exposed on the glass substrate 2 are selectively removed to expose the scanning line electrode terminals 5A, the pixel electrodes 22, and the signal line electrode terminals 6A. At this time, the storage capacitor line electrode terminal 7A is also exposed.
Here, since the ITZO film having an ITZO composition ratio (wt%) of 85: 10: 5, which is the transparent conductive layer 91, is given crystallinity by the heat treatment received during the formation of the gate insulating layer 30, a mixed acid is used. Even if the first metal layers 92A to 92C are removed, there is no fear that the scanning line electrode terminal 5A, the pixel electrode 22, and the signal line electrode terminal 6A are reduced or disappear.

Next, as shown in FIGS. 27, 34 and 35, one or more second metal layers 35 'including a refractory metal layer 34' are deposited, and a channel 31A, a source electrode 33S, a drain electrode 33D, and a source wiring are deposited. 12S, the signal line 12 and the drain wiring 21 are formed (step S25).
Here, when the second metal layer 35 ′ is a single layer, a refractory metal such as Ti, Cr, or Mo is used as the second metal layer 35 ′ similarly to the first metal layer 92. Further, when the second metal layer 35 ′ is used in combination with the AL thin film layer for reducing the resistance of the signal line 12, the second metal layer 35 ′ is used in order to avoid an alkaline reaction with the transparent conductive layer. As described above, it is necessary to interpose a Mo thin film layer as the refractory metal layer 34. Note that the second metal layer 35 ′ of this embodiment is composed of a Mo thin film layer and an AL thin film layer as the refractory metal layer 34 ′. Further, in FIG. 35, the heat-resistant metal layer 34 'included in the metal layer 35' is shown for easy understanding.
That is, in the source / drain wiring formation process, the second metal layer (metal layer for source / drain wiring) 35 ′ (AL thin film layer and film) is formed on the entire surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT. A heat-resistant metal layer (buffer metal layer) 34 ′) having a thickness of about 0.1 μm is sequentially deposited. Subsequently, the second metal layer 35 ′ is etched by a microfabrication technique, and the second amorphous silicon 33 A is selectively etched, so that the first amorphous silicon 31 A has a thickness of 0.05. Etch leaving about 0.1 μm. Thereby, the channel 31A, the source electrode 33S, and the drain electrode 33D are formed above the gate electrode 11A. Further, by etching the second metal layer 35 ′ as described above, the source made of the second metal layer 35 ′ (laminated body including the AL thin film layer and the refractory metal layer (buffer metal layer) 34 ′). A wiring 12S, a signal line 12, and a drain wiring 21 are formed. At this time, a storage electrode 72 that connects the opposing pixel electrodes 22 is also formed on the storage capacitor line 16 in the pixel.

Next, as shown in FIGS. 27, 36, and 37, a transparent insulating passivation insulating layer 37 is deposited on the glass substrate 2 (step S26).
That is, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating passivation insulating layer 37 using a PCVD apparatus. As a result, the second SiNx layer functions as a passivation insulating layer 37 and protects the first amorphous silicon 31A, which is the channel of the insulated gate transistor, from the outside air.

Next, as shown in FIGS. 27, 36, and 37, a protective insulating layer 90 having an opening is formed (step S27).
That is, first, as shown in FIGS. 36 and 37, a photosensitive black pigment dispersion resin having a film thickness of 1 μm or more is applied as a protective insulating layer 90 on the entire surface of the glass substrate 2, and then exposure and development are performed. Do. Thus, the pixel electrode openings 38 and the scanning line 11 electrode terminals are provided on the pixel electrode 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, the storage capacitor line electrode terminal 7A and the scanning line 11, respectively. A protective insulating layer 90 having an opening 63, an electrode terminal opening 64 of the signal line 12, an electrode terminal opening 65 of the storage capacitor line 16 and a parasitic transistor prevention opening 67 is formed.

Next, as shown in FIGS. 27, 36, and 37, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, the pixel electrode 22, and the first amorphous silicon layer 31A are exposed (step S28).
That is, the passivation insulating layer 37 in each of the openings 38, 63, 64, 65, and 67 is selectively removed using the photosensitive black pigment dispersed resin that is the protective insulating layer 90 as a mask, and the pixel electrode is disposed in each of the openings. 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, the storage capacitor line electrode terminal 7A, and the first amorphous silicon layer 31A are exposed.

Next, as shown in FIGS. 27, 38, and 39, the first amorphous silicon layer 31A in the parasitic transistor preventing opening 67 is selectively removed to expose the gate insulating layer 30A (step S29). .
That is, using the photosensitive black pigment dispersion resin 90 as a mask, the first amorphous silicon layer 31A in the parasitic transistor preventing opening 67 is selectively removed, and the gate insulating layer 30A is exposed in the opening 67. . In this way, unnecessary first amorphous silicon 31A in the opening 67 is removed, and generation of a parasitic transistor can be prevented.
As for the configuration of the storage capacitor 15, as shown in FIG. 34, the storage electrode 72 and the storage capacitor line 16 are composed of the second amorphous silicon layer 33B, the first amorphous silicon layer 31B, and the gate insulation. The storage capacitor formation region 52 is formed by overlapping in a plane via the layer 30 </ b> B (the storage capacitor forming region 52 is a downward slanting line portion by a dotted line).
As countermeasures against static electricity, the static electricity composed of the first metal layer 92 and the transparent conductive layer 91 is connected to the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the storage capacitor line pseudo electrode terminal 96. A countermeasure pattern is formed, and then a transparent conductive layer pattern 40 obtained by removing the first metal layer 92 is formed. As a result, it is possible to take a countermeasure against static electricity that is almost equivalent to that of the conventional example.

As described above, according to the method for manufacturing the display device substrate 2C of the present embodiment, the scanning line 11 and the like forming process, the semiconductor layer forming process, the source and drain wiring forming process, and the protective insulating layer In the opening forming step to 90, a display device substrate can be manufactured using a total of four photomasks.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2C is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.

Moreover, this embodiment has various application examples.
Next, an application example of the third embodiment will be described with reference to the drawings.
For example, in the above embodiment, a negative photosensitive black pigment dispersion resin (this resin is usually used for BM of a CF substrate) is used as the protective insulating layer 90. Halftone exposure technology may be used in combination with the developed positive photosensitive black pigment dispersion resin. In this way, as shown in FIGS. 40 and 41, the pixel electrodes are respectively formed on the pixel electrode 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, the storage capacitor line electrode terminal 7A, and the scanning line 11. For example, the spacer opening region 85A has a film thickness of 3 μm and the other region 85B has a film thickness of 1 μm, for example. Such photosensitive black pigment dispersed resin patterns 85A and 85B can be formed. By using the photosensitive black pigment dispersed resin patterns 85A and 85B as a mask, the passivation insulating layer 37 and the first amorphous silicon layer 31 in each opening are selectively removed as described above, so that transparent conductive pixels are formed. The electrode 22, the transparent conductive scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the storage capacitor line electrode terminal 7A are exposed. The spacer arrangement region 85A is formed in a region (region other than the pixel electrode) that does not hinder image display in the pixel.

When the display device substrate 2C ′ thus obtained and the color filter 9 not incorporating BM are bonded to form a liquid crystal panel, a photo spacer (dispersed photosensitive black pigment dispersion) is formed on the display device substrate 2C ′. Since the resin pattern 85A) is formed, there is no need for the spacer dispersion step in the panel assembling step, or it is not necessary to form the spacer on the CF substrate. Therefore, the number of manufacturing steps is smaller than that of the conventional liquid crystal display device. Reduction is further promoted, and it becomes easier to lower the manufacturing cost of the liquid crystal display device.
In addition, since the BM is formed on the display device substrate 2C ′, the relative positional deviation in the pasting of the display device substrate and the CF substrate as in the past is automatically absorbed and the aperture ratio is also automatically adjusted. A secondary effect is also obtained.

The present invention is also effective as an invention of a display device substrate.
The display device substrate 2C of the third embodiment is a display device substrate manufactured by the third embodiment of the display device substrate manufacturing method described above (see FIGS. 38 and 39).
The display device substrate 2C is a display device substrate having a channel etch type insulated gate transistor, and includes a gate electrode 11A, a scanning line 11, a gate insulator 30A, a channel 31A, a source electrode 33S, a source wiring 12S, a signal. A line 12, a drain electrode 33D, a drain wiring 21, a pixel electrode 22, a passivation insulating layer 37, a protective insulating layer 90, and the like are provided.

The gate electrode 11A, the scanning line 11, the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the pseudo pixel electrode 93 are connected to the transparent conductive layer 91 deposited on one main surface of the glass substrate 2 and the gate conduction. It is formed from a laminate including a layer (first metal layer 92).
Further, the gate insulating layer 30A, the first amorphous silicon layer 31A containing no impurities, and the second amorphous silicon layer 33A containing impurities contain the glass substrate 2, the gate electrode 11A, the scanning line 11, and the scanning line. The pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the pseudo pixel electrode 93 are sequentially deposited on the gate electrode 11A and the scanning line 11 so as to be wider than the gate electrode 11A and the scanning line 11. Thereby, the upper surfaces and side surfaces of the gate electrode 11A and the scanning line 11 are covered with the gate insulating layer 30A.
Further, the pixel electrode 22 made of the transparent conductive layer 91, the scanning line electrode terminal 5A, and the signal line electrode terminal 6A are connected to the pseudo pixel electrode 93, the scanning line pseudo electrode terminal 94, and the signal line pseudo electrode terminal 95, respectively. One metal layer (gate conductive layer) 92 is exposed by being removed.

  The source line 12S, the signal line 12 connected to the signal line electrode terminal 6A, and the drain line 21 connected to the pixel electrode 22 are formed on the second amorphous silicon layer 33, the transparent conductive layer 91, and the glass substrate 2. The deposited conductive layer for signal lines (second metal layer 35 ') is formed using a normal exposure technique (without using a halftone exposure technique). Note that the resist used at this time is a resist used when forming the channel 31A, the source electrode 33S, and the drain electrode 33D. In this embodiment, the source electrode and the drain electrode are the source electrode 33S and the drain electrode 33D made of the second amorphous silicon layer 33. However, the signal line conduction above the source electrode 33S and the drain electrode 33D is used. The layer (second metal layer 35 ') may be a source electrode and a drain electrode.

  Further, the channel 31A, the source electrode 33S, and the drain electrode 33D are sequentially deposited following the gate insulating layer 30, and are formed on the gate electrode 11A so as to be wider than the gate electrode 11A and do not contain impurities. It is formed from a multilayer body including the layer 31 and the second amorphous silicon layer 33 containing impurities. That is, the channel 31A, the source electrode 33S, and the drain electrode 33D are formed from the multilayer body using the normal exposure technique (without using the halftone exposure technique), and the second amorphous silicon layer 33 and the first electrode 33D. It is formed by removing a part of the amorphous silicon layer 31.

The passivation insulating layer 37 and the protective insulating layer 90 include a channel 31A, a source electrode 33S, a source wiring 12S, a signal line 12, a signal line electrode terminal 6A, a scanning line electrode terminal 5A, a drain electrode 33D, a drain wiring 21, and a pixel electrode. The glass substrate 2 is sequentially deposited on the formed glass substrate 2.
In addition, the passivation insulating layer 37 and the protective insulating layer 90 include a pixel electrode opening 38 on the pixel electrode 22, a parasitic transistor preventing opening 67 on the scanning line 11, and an electrode terminal opening on the scanning line electrode terminal 5A. The electrode terminal opening 64 on the part 63 and the signal line electrode terminal 6A is formed.
Further, the gate insulating layer 30 in the opening for preventing parasitic transistors 67 is exposed in the opening for preventing parasitic transistors 67 by removing the first amorphous silicon layer 31.

The protective insulating layer 90 is an insulating layer having a light shielding property (a layer made of a photosensitive black pigment dispersed resin).
In this manner, the protective insulating layer 90 protects and insulates the source wiring 12S and the drain wiring 21 and also functions as a black matrix, so that the added value of the display device substrate can be improved. Further, when this display device substrate 2C is used in a liquid crystal display device, it is not necessary to form a black matrix in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

Further, the pseudo pixel electrode P22 and the like are formed from a laminated body of the transparent conductive layer 91 and the first metal layer 92, and further, after the semiconductor layers (31A and 33A) are formed, the exposed first metal layer 92 is formed. Are selectively removed to expose the pixel electrode 22 made of the transparent conductive layer 91 and the like.
Thus, the conductivity and translucency can be improved, and the performance as a display device substrate can be improved.
Further, the first amorphous silicon layer 31 </ b> A in the parasitic transistor preventing opening 67 is selectively removed, and the gate insulating layer 30 </ b> A is exposed in the opening 67. In this way, unnecessary first amorphous silicon 31A in the opening 67 is removed, and generation of a parasitic transistor can be prevented.
Further, since the glass substrate 2 is transparent and has an insulating property, and the passivation insulating layer 37 is transparent, the translucency can be improved, and when used in a liquid crystal display device, Image quality can be improved.

Preferably, the storage capacitor line 16 or the like may be formed and the storage capacitor forming region 52 may be provided. Thus, the gradation of the display image can be improved, and the added value as a display device substrate can be improved.
The storage capacitor formation region 52 of the present embodiment forms a storage capacitor by planarly overlapping the storage electrode 72 and the storage capacitor line 16 that connect the pair of pixel electrodes 22 with the gate insulating layer 30 interposed therebetween. Yes.

As described above, the display device substrate 2C of this embodiment can be manufactured by a four-mask process.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2C is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.

Moreover, this embodiment has various application examples.
The display device substrate 2C ′ according to the application example of the third embodiment is a display device substrate manufactured by the application example of the third embodiment of the method for manufacturing a display device substrate described above (see FIGS. 40 and 41). ).
That is, the protective insulating layer 90 in the spacer region is preferably made thicker than other regions, and the photosensitive black pigment dispersed resin pattern 85A is used as a photo spacer.
In this way, the protective insulating layer 90 protects and insulates the source wiring 12S, the drain wiring 21 and the like, and also functions as a photo spacer, so that the added value of the display device substrate 2C ′ can be improved. Further, when this display device substrate 2C ′ is used in a liquid crystal display device, it is not necessary to form a photo spacer on the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

[Fourth Embodiment of Display Device Substrate and Method of Manufacturing the Same]
FIG. 42 is a schematic flowchart for explaining a method for manufacturing a display device substrate according to the fourth embodiment of the present invention.
43, 45, 47, 49, and 51 are schematic plan views of unit pixels corresponding to respective manufacturing steps for explaining a method for manufacturing a display device substrate according to the fourth embodiment of the present invention. .
Furthermore, FIGS. 44, 46, 48, 50, and 52 are schematic cross-sectional views of unit pixels corresponding to respective manufacturing steps for explaining a method for manufacturing a display device substrate according to the fourth embodiment of the present invention. . In these schematic cross-sectional views, (a) shows a cross-sectional view on the AA ′ line (insulated gate transistor (thin film transistor) region), and (b) shows a cross-sectional view on the BB ′ line (scanning line electrode terminal region). A cross-sectional view is shown, and FIG. 5C is a cross-sectional view on the line CC ′ (signal line electrode terminal region) (see FIG. 51).
The display device substrate of this embodiment includes channel-etched insulated gate transistors (thin film transistors).
In addition, about the site | part same as the said embodiment and application example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

First, as shown in FIGS. 42, 43, and 44, on a glass substrate 2, a gate electrode 11A made of a laminate including a transparent conductive layer 91 and a first metal layer 92, a scanning line 11, and a scanning line pseudo-electrode terminal. 94, the pseudo pixel electrode 93 and the signal line pseudo electrode terminal 95 are formed (step S31).
That is, a transparent conductive layer 91 having a film thickness of about 0.1 μm is formed on a transparent and insulating glass substrate 2, for example, on one main surface of a product name 1737 manufactured by Corning using a vacuum film forming apparatus such as SPT. A first metal layer 92 is deposited as a gate conductive layer having a thickness of about 0.1 to 0.3 μm.
The first metal layer 92 is as described in the first embodiment. However, in order to reduce the resistance of the scanning line 11 and prevent the battery reaction with the transparent conductive layer 91, Mo / AL / Mo or A laminated structure such as Mo / AL (Nd) is optimal.
For the transparent conductive layer 91, an ITZO film having a sputter target ITZO composition ratio (wt%) of 70:15:15 may be used. An ITZO film having an ITZO composition ratio (wt%) of 70:15:15 has resistance to an acidic solution regardless of heating. That is, even if the first metal layer 92 is removed using a mixed acid obtained by adding several percent nitric acid to phosphoric acid, the pixel electrode 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the like are reduced in film thickness. There is no problem of disappearing.

Subsequently, the gate electrode 11A, the scanning line 11 connected to the gate electrode 11A, the pseudo electrode terminal for scanning line 94, the pseudo pixel electrode 93, the pseudo electrode terminal for signal line 95, the storage capacitor line 16 and the storage by the fine processing technique. A capacitance line pseudo electrode terminal 96 is formed.
Note that the scanning line pseudo electrode terminal 94 connected to the scanning line 11, the storage capacitor line pseudo electrode terminal 96 and the signal line pseudo electrode terminal 95 connected to the storage capacitor line 16 are located outside the image display area. It is formed.
In addition, the pseudo pixel electrode 93 of the present embodiment is formed to face two locations on both sides of the storage capacitor line 16.

Next, as shown in FIGS. 42, 45, and 46, the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A are sequentially deposited on the glass substrate 2 (see FIG. Step S32).
That is, by using a PCVD apparatus over the entire surface of the glass substrate 2, a first SiNx layer as the gate insulating layer 30, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and Then, three types of thin film layers of the second amorphous silicon layer 33 containing impurities and serving as the source and drain of the insulated gate transistor are sequentially covered with a film thickness of, for example, about 0.3-0.2-0.05 μm. To wear.

Next, as shown in FIGS. 42, 45, and 46, the stacked body including the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A is formed into the gate electrode 11A and the scanning line. 11 is formed widely (step S33).
That is, a stacked body including the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A on the gate electrode 11A and the scanning line 11 is formed into the gate electrode 11A and the scanning line 11. Form wider. Further, a stacked body including the gate insulating layer 30 </ b> B, the first amorphous silicon layer 31 </ b> B, and the second amorphous silicon layer 33 </ b> B is formed on the storage capacitor line 16 wider than the storage capacitor line 16. Thus, the scanning line pseudo electrode terminal 94, the pseudo pixel electrode 93, the signal line pseudo electrode terminal 95, the storage capacitor line pseudo electrode terminal 96, and the glass substrate 2 are exposed. Further, the gate electrode 11 </ b> A, the scanning line 11, and the storage capacitor line 16 are covered with the gate insulating layer 30 on the upper surface and side surfaces.

Next, as shown in FIGS. 42, 47, and 48, one or more second metal layers 35 'including a refractory metal layer 34' are deposited, and a channel 31A, a source electrode 33S, a drain electrode 33D, and a source wiring are formed. 12S, the signal line 12 and the drain wiring 21 are formed, and the scanning line electrode terminal 5A, the pixel electrode 22 and the signal line electrode terminal 6A made of the transparent conductive layer 91 are exposed (step S34).
Here, the detailed contents of one or more second metal layers 35 ′ including the refractory metal layer 34 ′ of the present embodiment are as described in the third embodiment.

  That is, in the source / drain wiring formation process, the second metal layer (metal layer for source / drain wiring) 35 ′ (AL thin film layer and film) is formed on the entire surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT. A heat-resistant metal layer (buffer metal layer) 34 ′) having a thickness of about 0.1 μm is sequentially deposited. Subsequently, the second metal layer 35 ′ and the first metal layers 92 </ b> A to 92 </ b> C are etched by a microfabrication technique, and the second amorphous silicon 33 </ b> A is selectively etched, so that the first The amorphous silicon 31A is etched while leaving about 0.05 to 0.1 μm. Thereby, the channel 31A, the source electrode 33S, and the drain electrode 33D are formed above the gate electrode 11A. Further, by etching the second metal layer 35 ′ and the first metal layers 92 </ b> A to 92 </ b> C as described above, the second metal layer 35 ′ (AL thin film layer and refractory metal layer (buffer metal layer) 34 is formed. A source wiring 12S, a signal line 12 and a drain wiring 21 are formed. At this time, a storage electrode 72 that connects the opposing pixel electrodes 22 is also formed on the storage capacitor line 16 in the pixel. Further, the first metal layers 92A to 92C exposed on the glass substrate 2 are selectively removed to expose the scanning line electrode terminal 5A, the pixel electrode 22, and the signal line electrode terminal 6A. At this time, the storage capacitor line electrode terminal 7A is also exposed. If it does in this way, compared with 3rd embodiment, when removing 2nd metal layer 35 ', since 1st metal layer 92A-92C can also be selectively removed, reduction of the number of manufacturing processes Is possible.

  As described above, the second metal layer 35 ′ is preferably an AL thin film layer for reducing the resistance of the signal line 12, and a Mo thin film layer is selected as the refractory metal layer 34 ′. In the present embodiment, the first metal layer 92 is, for example, Mo / AL / Mo or Mo / AL (Nd) so that the first metal layer 92 is also etched when the second metal layer 35 ′ is etched. It is preferable to adopt a laminated structure such as As a result, when the source wiring 12S and the drain wiring 21 are formed as described above, the pixel electrode 22 made of the transparent conductive layer 91 and the scanning line electrode are formed on the glass substrate 2 by overetching the second metal layer 35 '. The terminal 5A, the signal line electrode terminal 6A, and the storage capacitor line electrode terminal 7A are exposed. In addition, the ITZO film (transparent conductive layer 91) having an ITZO composition ratio (wt%) of 70:15:15 has resistance to an acidic solution regardless of heating. That is, even if the first metal layer 92 is removed using a mixed acid obtained by adding several percent nitric acid to phosphoric acid, the pixel electrode 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the like are reduced in film thickness. There is no problem of disappearing.

Next, as shown in FIGS. 42, 49 and 50, a transparent insulating passivation insulating layer 37 is deposited on the glass substrate 2 (step S35).
That is, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating passivation insulating layer 37 using a PCVD apparatus. As a result, the second SiNx layer functions as a passivation insulating layer 37 and protects the first amorphous silicon 31A, which is the channel of the insulated gate transistor, from the outside air.

Next, as shown in FIGS. 42, 49, and 50, a protective insulating layer 90 having an opening is formed (step S36).
That is, first, as shown in FIGS. 49 and 50, a photosensitive black pigment dispersion resin having a thickness of 1 μm or more is applied as a protective insulating layer 90 on the entire surface of the glass substrate 2, followed by exposure and development. Do. Thus, the pixel electrode openings 38 and the scanning line 11 electrode terminals are provided on the pixel electrode 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, the storage capacitor line electrode terminal 7A and the scanning line 11, respectively. A protective insulating layer 90 having an opening 63, an electrode terminal opening 64 of the signal line 12, an electrode terminal opening 65 of the storage capacitor line 16 and a parasitic transistor prevention opening 67 is formed.

Next, as shown in FIGS. 42, 49, and 50, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, the pixel electrode 22, and the first amorphous silicon layer 31A are exposed (step S37).
That is, the passivation insulating layer 37 in each of the openings 38, 63, 64, 65, and 67 is selectively removed using the photosensitive black pigment dispersed resin that is the protective insulating layer 90 as a mask, and the pixel electrode is disposed in each of the openings. 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, the storage capacitor line electrode terminal 7A, and the first amorphous silicon layer 31A are exposed.

Next, as shown in FIGS. 42, 51, and 52, the first amorphous silicon layer 31A in the parasitic transistor preventing opening 67 is selectively removed to expose the gate insulating layer 30A (step S38). .
That is, using the photosensitive black pigment dispersion resin 90 as a mask, the first amorphous silicon layer 31A in the parasitic transistor preventing opening 67 is selectively removed, and the gate insulating layer 30A is exposed in the opening 67. . In this way, unnecessary first amorphous silicon 31A in the opening 67 is removed, and generation of a parasitic transistor can be prevented.
As to the configuration of the storage capacitor 15, as shown in FIG. 47, the storage electrode 72 and the storage capacitor line 16 are formed by the second amorphous silicon layer 33B, the first amorphous silicon layer 31B, and the gate insulation. The storage capacitor forming region 52 is formed by overlapping with the layer 30B in a plan view (the storage capacitor forming region 52 is a hatched portion with a lower right side by a dotted line).
As countermeasures against static electricity, the static electricity composed of the first metal layer 92 and the transparent conductive layer 91 is connected to the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the storage capacitor line pseudo electrode terminal 96. A countermeasure pattern is formed, and then a transparent conductive layer pattern 40 obtained by removing the first metal layer 92 is formed. As a result, it is possible to take a countermeasure against static electricity that is almost equivalent to that of the conventional example.

As described above, according to the method for manufacturing the display device substrate 2D of the present embodiment, the scanning line 11 and the like forming process, the semiconductor layer forming process, the source and drain wiring forming process, and the protective insulating layer In the opening forming step to 90, a display device substrate can be manufactured using a total of four photomasks.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2D is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.
Further, compared to the third embodiment, when removing the second metal layer 35 ′, the first metal layers 92 </ b> A to 92 </ b> C can also be selectively removed, so that the number of manufacturing steps can be reduced. Become.

Moreover, this embodiment has various application examples.
Next, an application example of the fourth embodiment will be described with reference to the drawings.
For example, in the above embodiment, a negative photosensitive black pigment dispersion resin (this resin is usually used for BM of a CF substrate) is used as the protective insulating layer 90. Halftone exposure technology may be used in combination with the developed positive photosensitive black pigment dispersion resin. Thus, as shown in FIGS. 53 and 54, the pixel electrode 22, the scanning line electrode terminal 5 </ b> A, the signal line electrode terminal 6 </ b> A, the storage capacitor line electrode terminal 7 </ b> A, and the scanning line 11, respectively. For example, the spacer arrangement region 85A has a thickness of 3 μm and the other region 85B has a thickness of 1 μm, for example. Such photosensitive black pigment dispersed resin patterns 85A and 85B can be formed. By using the photosensitive black pigment dispersed resin patterns 85A and 85B as a mask, the passivation insulating layer 37 and the first amorphous silicon layer 31 in each opening are selectively removed as described above, so that transparent conductive pixels are formed. The electrode 22, the transparent conductive scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the storage capacitor line electrode terminal 7A are exposed. The spacer arrangement region 85A is formed in a region (region other than the pixel electrode) that does not hinder image display in the pixel.

When the display device substrate 2D ′ thus obtained and the color filter 9 not incorporating BM are bonded to form a liquid crystal panel, a photo spacer (dispersed photosensitive black pigment dispersion) is formed on the display device substrate 2D ′. Since the resin pattern 85A) is formed, there is no need for the spacer dispersion step in the panel assembling step, or there is no need to form the spacer on the CF substrate. Reduction is further promoted, and it becomes easier to lower the manufacturing cost of the liquid crystal display device.
Further, since the BM is formed on the display device substrate 2D ′, the relative positional shift in the pasting of the display device substrate and the CF substrate as in the conventional case is automatically absorbed and the aperture ratio is automatically adjusted. A secondary effect is also obtained.

The present invention is also effective as an invention of a display device substrate.
The display device substrate 2D of the fourth embodiment is a display device substrate manufactured according to the fourth embodiment of the display device substrate manufacturing method described above (see FIGS. 51 and 52).
The display device substrate 2D is a display device substrate having channel-etched insulated gate transistors, and includes a gate electrode 11A, a scanning line 11, a gate insulator 30A, a channel 31A, a source electrode 33S, a source wiring 12S, a signal. A line 12, a drain electrode 33D, a drain wiring 21, a pixel electrode 22, a passivation insulating layer 37, a protective insulating layer 90, and the like are provided.

The gate electrode 11A, the scanning line 11, the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the pseudo pixel electrode 93 are connected to the transparent conductive layer 91 deposited on one main surface of the glass substrate 2 and the gate conduction. It is formed from a laminate including a layer (first metal layer 92).
Further, the gate insulating layer 30A, the first amorphous silicon layer 31A containing no impurities, and the second amorphous silicon layer 33A containing impurities contain the glass substrate 2, the gate electrode 11A, the scanning line 11, and the scanning line. The pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the pseudo pixel electrode 93 are sequentially deposited on the gate electrode 11A and the scanning line 11 so as to be wider than the gate electrode 11A and the scanning line 11. Thereby, the upper surfaces and side surfaces of the gate electrode 11A and the scanning line 11 are covered with the gate insulating layer 30A.

The source line 12S, the signal line 12 connected to the signal line electrode terminal 6A, and the drain line 21 connected to the pixel electrode 22 are a second amorphous silicon layer 33, a first metal layer (gate conductive layer). 92 and the signal line conductive layer (second metal layer 35 ′) deposited on the glass substrate 2, using a normal exposure technique (without using a halftone exposure technique). At this time, the pixel electrode 22, the scanning line electrode terminal 5A, and the signal line electrode terminal 6A made of the transparent conductive layer 91 are the pseudo pixel electrode 93, the scanning line pseudo electrode terminal 94, and the signal line pseudo electrode terminal 95. Then, the first metal layer 92 is exposed by being removed.
The resist used at this time is a resist used when forming the channel 31A, the source electrode 33S, and the drain electrode 33D. In this embodiment, the source electrode and the drain electrode are the source electrode 33S and the drain electrode 33D made of the second amorphous silicon layer 33. However, the signal line conduction above the source electrode 33S and the drain electrode 33D is used. The layer (second metal layer 35 ') may be a source electrode and a drain electrode.

  Further, the channel 31A, the source electrode 33S, and the drain electrode 33D are sequentially deposited following the gate insulating layer 30, and are formed on the gate electrode 11A so as to be wider than the gate electrode 11A and do not contain impurities. It is formed from a multilayer body including the layer 31 and the second amorphous silicon layer 33 containing impurities. That is, the channel 31A, the source electrode 33S, and the drain electrode 33D are formed from the multilayer body using the normal exposure technique (without using the halftone exposure technique), and the second amorphous silicon layer 33 and the first electrode 33D. It is formed by removing a part of the amorphous silicon layer 31.

The passivation insulating layer 37 and the protective insulating layer 90 include a channel 31A, a source electrode 33S, a source wiring 12S, a signal line 12, a signal line electrode terminal 6A, a scanning line electrode terminal 5A, a drain electrode 33D, a drain wiring 21, and a pixel electrode. The glass substrate 2 is sequentially deposited on the formed glass substrate 2.
In addition, the passivation insulating layer 37 and the protective insulating layer 90 include a pixel electrode opening 38 on the pixel electrode 22, a parasitic transistor preventing opening 67 on the scanning line 11, and an electrode terminal opening on the scanning line electrode terminal 5A. The electrode terminal opening 64 on the part 63 and the signal line electrode terminal 6A is formed.
Further, the gate insulating layer 30 in the opening for preventing parasitic transistors 67 is exposed in the opening for preventing parasitic transistors 67 by removing the first amorphous silicon layer 31.

The protective insulating layer 90 is an insulating layer having a light shielding property (a layer made of a photosensitive black pigment dispersed resin).
In this manner, the protective insulating layer 90 protects and insulates the source wiring 12S and the drain wiring 21 and also functions as a black matrix, so that the added value of the display device substrate can be improved. Further, when this display device substrate 2D is used in a liquid crystal display device, it is not necessary to form a black matrix in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

Further, the pseudo pixel electrode P22 and the like are formed from a laminate of the transparent conductive layer 91 and the first metal layer 92, and the first metal exposed when the source wiring 12 and the drain wiring 21 are formed. The layer 92 is selectively removed to expose the pixel electrode 22 made of the transparent conductive layer 91 and the like.
Thus, the conductivity and translucency can be improved, and the performance as a display device substrate can be improved. Further, compared to the third embodiment, when removing the second metal layer 35 ′, the first metal layers 92 </ b> A to 92 </ b> C can also be selectively removed, so that the number of manufacturing steps can be reduced. Become.
Further, the first amorphous silicon layer 31 </ b> A in the parasitic transistor preventing opening 67 is selectively removed, and the gate insulating layer 30 </ b> A is exposed in the opening 67. In this way, unnecessary first amorphous silicon 31A in the opening 67 is removed, and generation of a parasitic transistor can be prevented.
Further, since the glass substrate 2 is transparent and has an insulating property, and the passivation insulating layer 37 is transparent, the translucency can be improved, and when used in a liquid crystal display device, Image quality can be improved.

Preferably, the storage capacitor line 16 or the like may be formed and the storage capacitor forming region 52 may be provided. Thus, the gradation of the display image can be improved, and the added value as a display device substrate can be improved.
The storage capacitor formation region 52 of the present embodiment forms a storage capacitor by planarly overlapping the storage electrode 72 and the storage capacitor line 16 that connect the pair of pixel electrodes 22 with the gate insulating layer 30 interposed therebetween. Yes.

As described above, the display device substrate 2D of this embodiment can be manufactured by a four-mask process.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2D is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.
Further, compared to the third embodiment, when removing the second metal layer 35 ′, the first metal layers 92 </ b> A to 92 </ b> C can also be selectively removed, so that the number of manufacturing steps can be reduced. Become.

Moreover, this embodiment has various application examples.
The display device substrate 2D ′ according to the application example of the fourth embodiment is a display device substrate manufactured by the application example of the fourth embodiment of the method for manufacturing the display device substrate described above (see FIGS. 53 and 54). ).
That is, the protective insulating layer 90 in the spacer region is preferably made thicker than other regions, and the photosensitive black pigment dispersed resin pattern 85A is used as a photo spacer.
In this case, the protective insulating layer 90 protects and insulates the source wiring 12S, the drain wiring 21 and the like, and also functions as a photo spacer, so that the added value of the display device substrate 2D ′ can be improved. Further, when this display device substrate 2D ′ is used in a liquid crystal display device, it is not necessary to form a photo spacer on the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

[Fifth Embodiment of Display Device Substrate and Method of Manufacturing the Same]
FIG. 55 is a schematic flowchart for explaining a method for manufacturing a display device substrate according to the fifth embodiment of the present invention.
56, 58, 60, 62, and 64 are schematic plan views of unit pixels corresponding to the respective manufacturing steps for explaining a method for manufacturing a display device substrate according to the fifth embodiment of the present invention. .
Further, FIGS. 57, 59, 61, 63, and 65 are schematic cross-sectional views of unit pixels corresponding to respective manufacturing steps for explaining a method for manufacturing a display device substrate according to the fifth embodiment of the present invention. . In these schematic cross-sectional views, (a) shows a cross-sectional view on the AA ′ line (insulated gate transistor (thin film transistor) region), and (b) shows a cross-sectional view on the BB ′ line (scanning line electrode terminal region). A cross-sectional view is shown, and (c) shows a cross-sectional view on the line CC ′ (signal line electrode terminal region) (see FIG. 64).
The display device substrate of this embodiment includes channel-etched insulated gate transistors (thin film transistors).
In addition, about the site | part same as the said embodiment and application example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

First, as shown in FIGS. 55, 56, and 57, on a glass substrate 2, a gate electrode 11A made of a laminate including a transparent conductive layer 91 and a first metal layer 92, a scanning line 11, and a scanning line pseudo-electrode terminal. 94, the pseudo pixel electrode 93 and the signal line pseudo electrode terminal 95 are formed (step S41).
That is, a transparent conductive layer 91 having a film thickness of about 0.1 μm is formed on a transparent and insulating glass substrate 2, for example, on one main surface of a product name 1737 manufactured by Corning using a vacuum film forming apparatus such as SPT. A first metal layer 92 is deposited as a gate conductive layer having a thickness of about 0.1 to 0.3 μm.
As for the first metal layer 92, a heat resistant material such as Ti or Cr is used as the first metal layer 92 so that the first metal layer 92 is not etched when a second metal layer 35 'described later is etched. Metal is selected.
For the transparent conductive layer 91, an ITZO film having an ITZO composition ratio (wt%) of a sputtering target of 85: 10: 5 may be used. In this case, when the first metal layer 92 is etched using the mixed acid, the transparent conductive layer 91 is also etched at the same time, so that the number of manufacturing steps can be reduced. In addition, the shape control of the laminated cross section becomes easy.

Subsequently, the gate electrode 11A, the scanning line 11 connected to the gate electrode 11A, the pseudo electrode terminal for scanning line 94, the pseudo pixel electrode 93, the pseudo electrode terminal for signal line 95, the storage capacitor line 16 and the storage by the fine processing technique. A capacitance line pseudo electrode terminal 96 is formed.
Note that the scanning line pseudo electrode terminal 94 connected to the scanning line 11, the storage capacitor line pseudo electrode terminal 96 and the signal line pseudo electrode terminal 95 connected to the storage capacitor line 16 are located outside the image display area. It is formed.
In addition, the pseudo pixel electrode 93 of the present embodiment is formed to face two locations on both sides of the storage capacitor line 16.

Next, as shown in FIGS. 55, 58, and 59, the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A are sequentially deposited on the glass substrate 2 (see FIG. Step S42).
That is, by using a PCVD apparatus over the entire surface of the glass substrate 2, a first SiNx layer as the gate insulating layer 30, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and Then, three types of thin film layers of the second amorphous silicon layer 33 containing impurities and serving as the source and drain of the insulated gate transistor are sequentially covered with a film thickness of, for example, about 0.3-0.2-0.05 μm. To wear.

Next, as shown in FIGS. 55, 58, and 59, the stacked body including the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A is formed into the gate electrode 11A and the scanning line. 11 is widely formed (step S43).
That is, a stacked body including the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A on the gate electrode 11A and the scanning line 11 is formed into the gate electrode 11A and the scanning line 11. Form wider. Further, a stacked body including the gate insulating layer 30 </ b> B, the first amorphous silicon layer 31 </ b> B, and the second amorphous silicon layer 33 </ b> B is formed on the storage capacitor line 16 wider than the storage capacitor line 16. Thus, the scanning line pseudo electrode terminal 94, the pseudo pixel electrode 93, the signal line pseudo electrode terminal 95, the storage capacitor line pseudo electrode terminal 96, and the glass substrate 2 are exposed. Further, the gate electrode 11 </ b> A, the scanning line 11, and the storage capacitor line 16 are covered with the gate insulating layer 30 on the upper surface and side surfaces.

Next, as shown in FIGS. 55, 60, and 61, one or more second metal layers 35 'including the refractory metal layer 34' are deposited, and the channel 31A, the source electrode 33S, the drain electrode 33D, and the source wiring are formed. 12S, the signal line 12 and the drain wiring 21 are formed, and the scanning line pseudo electrode terminal 94, the pseudo pixel electrode 93, and the signal line pseudo electrode terminal 95 are exposed (step S44).
Here, the detailed contents of one or more second metal layers 35 ′ including the refractory metal layer 34 ′ of the present embodiment are as described in the third embodiment.

  That is, in the source / drain wiring formation process, the second metal layer (metal layer for source / drain wiring) 35 ′ (AL thin film layer and film) is formed on the entire surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT. A heat-resistant metal layer (buffer metal layer) 34 ′) having a thickness of about 0.1 μm is sequentially deposited. Subsequently, the second metal layer 35 ′ (the AL thin film layer and the heat-resistant metal layer (buffer metal layer) 34 ′) is etched by the fine processing technique, and the second amorphous silicon 33A is selectively etched. The first amorphous silicon 31A is etched to leave about 0.05 to 0.1 μm. Thereby, the channel 31A, the source electrode 33S, and the drain electrode 33D are formed above the gate electrode 11A. Further, as described above, the second metal layer 35 '(AL thin film layer and refractory metal) is etched by etching the second metal layer 35' (AL thin film layer and refractory metal layer (buffer metal layer) 34 '). A source wiring 12S, a signal line 12, and a drain wiring 21 made of a layer (a laminated body including a layer (buffer metal layer) 34 ') are formed. At this time, a storage electrode 72 that connects the opposing pixel electrodes 22 is also formed on the storage capacitor line 16 in the pixel. At this time, the storage capacitor line electrode terminal 7A is also exposed.

  As described above, the second metal layer 35 ′ is preferably an AL thin film layer for reducing the resistance of the signal line 12, and a Mo thin film layer is selected as the refractory metal layer 34 ′. In the present embodiment, a refractory metal such as Ti or Cr is selected as the first metal layer 92 so that the first metal layer 92 is not etched when the second metal layer 35 ′ is etched. .

Next, as shown in FIGS. 55, 62, and 63, a transparent insulating passivation insulating layer 37 is deposited on the glass substrate 2 (step S45).
That is, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating passivation insulating layer 37 using a PCVD apparatus. As a result, the second SiNx layer functions as a passivation insulating layer 37 and protects the first amorphous silicon 31A, which is the channel of the insulated gate transistor, from the outside air.

Next, as shown in FIGS. 55, 62, and 63, a protective insulating layer 90 having an opening is formed (step S46).
That is, first, as shown in FIGS. 62 and 63, a photosensitive black pigment dispersion resin having a thickness of 1 μm or more is applied as a protective insulating layer 90 on the entire surface of the glass substrate 2, and then exposure and development are performed. Do. As a result, the pixel electrode openings 38 and the scanning lines 11 are placed on the pseudo pixel electrode 93, the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, the storage capacitor line pseudo electrode terminal 96, and the scanning line 11, respectively. The protective insulating layer 90 having the electrode terminal opening 63, the electrode terminal opening 64 of the signal line 12, the electrode terminal opening 65 of the storage capacitor line 16 and the parasitic transistor prevention opening 67 is formed.

Next, as shown in FIGS. 55, 62, and 63, the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, the pseudo pixel electrode 93, and the first amorphous silicon layer 31A are exposed (step S47). ).
That is, the passivation insulating layer 37 in each of the openings 38, 63, 64, 65, and 67 is selectively removed using the photosensitive black pigment dispersed resin as the protective insulating layer 90 as a mask, and a pseudo pixel is formed in each of the openings. The electrode 93, the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, the storage capacitor line pseudo electrode terminal 96, and the first amorphous silicon layer 31A are exposed.

Next, as shown in FIGS. 55, 62, and 63, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the pixel electrode 22 made of the transparent conductive layer 91 are exposed (step S48).
That is, the first metal layer 92 in each of the openings 38, 63, 64, 65 is selectively removed using the photosensitive black pigment dispersion resin that is the protective insulating layer 90 as a mask, and the pixel electrode is disposed in each of the openings. 22, the scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the storage capacitor line electrode terminal 7A are exposed.

Next, as shown in FIGS. 55, 64, and 65, the first amorphous silicon layer 31A in the parasitic transistor preventing opening 67 is selectively removed to expose the gate insulating layer 30A (step S49). .
That is, using the photosensitive black pigment dispersion resin 90 as a mask, the first amorphous silicon layer 31A in the parasitic transistor preventing opening 67 is selectively removed, and the gate insulating layer 30A is exposed in the opening 67. . In this way, unnecessary first amorphous silicon 31A in the opening 67 is removed, and generation of a parasitic transistor can be prevented.
Regarding the configuration of the storage capacitor 15, as shown in FIG. 60, the storage electrode 72 and the storage capacitor line 16 are composed of the second amorphous silicon layer 33B, the first amorphous silicon layer 31B, and the gate insulation. The storage capacitor forming region 52 is formed by overlapping with the layer 30B in a plan view (the storage capacitor forming region 52 is a hatched portion with a lower right side by a dotted line).
As countermeasures against static electricity, the static electricity composed of the first metal layer 92 and the transparent conductive layer 91 is connected to the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the storage capacitor line pseudo electrode terminal 96. A countermeasure pattern is formed, and then a transparent conductive layer pattern 40 obtained by removing the first metal layer 92 is formed. As a result, it is possible to take a countermeasure against static electricity that is almost equivalent to that of the conventional example.

As described above, according to the method for manufacturing the display device substrate 2E of the present embodiment, the scanning line 11 and the like forming process, the semiconductor layer forming process, the source / drain wiring forming process, and the protective insulating layer In the opening forming step to 90, a display device substrate can be manufactured using a total of four photomasks.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2D is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.
Further, after the formation of the protective insulating layer 90, the first metal layers 92A to 92C are selectively removed, so that the degree of freedom in process design can be expanded.

Moreover, this embodiment has various application examples.
Next, an application example of the fifth embodiment will be described with reference to the drawings.
For example, in the above embodiment, a negative photosensitive black pigment dispersion resin (this resin is usually used for BM of a CF substrate) is used as the protective insulating layer 90. Halftone exposure technology may be used in combination with the developed positive photosensitive black pigment dispersion resin. 66 and 67, the pseudo pixel electrode 93, the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, the storage capacitor line pseudo electrode terminal 96, and the scanning line 11 are formed. The pixel electrode openings 38, the electrode terminal openings 63, 64, 65, and the parasitic transistor prevention openings 67 are provided, and the spacer arrangement region 85A has a thickness of 3 μm, for example, and the other regions 85B have a thickness. For example, photosensitive black pigment dispersed resin patterns 85A and 85B can be formed so as to be 1 μm. Using the photosensitive black pigment dispersed resin patterns 85A and 85B as a mask, the passivation insulating layer 37, the first metal layer 92, and the first amorphous silicon layer 31 in each opening are selectively removed as described above. Thus, the transparent conductive pixel electrode 22, the transparent conductive scanning line electrode terminal 5A, the signal line electrode terminal 6A, and the storage capacitor line electrode terminal 7A are exposed. The spacer arrangement region 85A is formed in a region (region other than the pixel electrode) that does not hinder image display in the pixel.

When the display device substrate 2E ′ thus obtained and the color filter 9 not incorporating BM are bonded to form a liquid crystal panel, a photo spacer (dispersed photosensitive black pigment dispersion) is formed on the display device substrate 2E ′. Since the resin pattern 85A) is formed, there is no need for the spacer dispersion step in the panel assembling step, or there is no need to form the spacer on the CF substrate. Reduction is further promoted, and it becomes easier to lower the manufacturing cost of the liquid crystal display device.
Further, since the BM is formed on the display device substrate 2E ′, the relative positional shift in the pasting of the display device substrate and the CF substrate as in the conventional case is automatically absorbed and the aperture ratio is automatically adjusted. A secondary effect is also obtained.

The present invention is also effective as an invention of a display device substrate.
The display device substrate 2E according to the fifth embodiment is a display device substrate manufactured according to the fifth embodiment of the display device substrate manufacturing method described above (see FIGS. 64 and 65).
The display device substrate 2E is a display device substrate having a channel etch type insulated gate transistor, and includes a gate electrode 11A, a scanning line 11, a gate insulator 30A, a channel 31A, a source electrode 33S, a source wiring 12S, a signal. A line 12, a drain electrode 33D, a drain wiring 21, a pixel electrode 22, a passivation insulating layer 37, a protective insulating layer 90, and the like are provided.

The gate electrode 11A, the scanning line 11, the scanning line pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the pseudo pixel electrode 93 are connected to the transparent conductive layer 91 deposited on one main surface of the glass substrate 2 and the gate conduction. It is formed from a laminate including a layer (first metal layer 92).
Further, the gate insulating layer 30A, the first amorphous silicon layer 31A containing no impurities, and the second amorphous silicon layer 33A containing impurities contain the glass substrate 2, the gate electrode 11A, the scanning line 11, and the scanning line. The pseudo electrode terminal 94, the signal line pseudo electrode terminal 95, and the pseudo pixel electrode 93 are sequentially deposited on the gate electrode 11A and the scanning line 11 so as to be wider than the gate electrode 11A and the scanning line 11. Thereby, the upper surfaces and side surfaces of the gate electrode 11A and the scanning line 11 are covered with the gate insulating layer 30A.

The source wiring 12S, the signal line 12 connected to the pseudo electrode terminal 95 for signal lines, and the drain wiring 21 connected to the pseudo pixel electrode 93 are composed of a second amorphous silicon layer 33, a first metal layer (gate conductive Layer) 92 and the signal line conductive layer (second metal layer 35 ') deposited on the glass substrate 2, using a normal exposure technique (without using a halftone exposure technique). Yes.
The resist used at this time is a resist used when forming the channel 31A, the source electrode 33S, and the drain electrode 33D. In this embodiment, the source electrode and the drain electrode are the source electrode 33S and the drain electrode 33D made of the second amorphous silicon layer 33. However, the signal line conduction above the source electrode 33S and the drain electrode 33D is used. The layer (second metal layer 35 ') may be a source electrode and a drain electrode.

  Further, the channel 31A, the source electrode 33S, and the drain electrode 33D are sequentially deposited following the gate insulating layer 30, and are formed on the gate electrode 11A so as to be wider than the gate electrode 11A and do not contain impurities. It is formed from a multilayer body including the layer 31 and the second amorphous silicon layer 33 containing impurities. That is, the channel 31A, the source electrode 33S, and the drain electrode 33D are formed from the multilayer body using the normal exposure technique (without using the halftone exposure technique), and the second amorphous silicon layer 33 and the first electrode 33D. It is formed by removing a part of the amorphous silicon layer 31.

The passivation insulating layer 37 and the protective insulating layer 90 include the channel 31A, the source electrode 33S, the source wiring 12S, the signal line 12, the signal line pseudo electrode terminal 95, the scanning line pseudo electrode terminal 94, the drain electrode 33D, the drain wiring 21 and They are sequentially deposited on the glass substrate 2 on which the pseudo pixel electrodes 93 and the like are formed.
In addition, the passivation insulating layer 37 and the protective insulating layer 90 include a pixel electrode opening 38 on the pseudo pixel electrode 93, a parasitic transistor preventing opening 67 on the scanning line 11, and an electrode terminal on the scanning line pseudo electrode terminal 94. An electrode terminal opening 64 on the signal opening 63 and the signal line pseudo electrode terminal 95 is formed.
Further, the pixel electrode 22, the scanning line electrode terminal 5 A, and the signal line electrode terminal 6 A made of the transparent conductive layer 91 are connected to the pseudo pixel electrode 93, the scanning line pseudo electrode terminal 94, and the signal line pseudo electrode terminal 95, respectively. The one metal layer 92 is exposed by being removed.
Further, the gate insulating layer 30 in the opening for preventing parasitic transistors 67 is exposed in the opening for preventing parasitic transistors 67 by removing the first amorphous silicon layer 31.

The protective insulating layer 90 is an insulating layer having a light shielding property (a layer made of a photosensitive black pigment dispersed resin).
In this manner, the protective insulating layer 90 protects and insulates the source wiring 12S and the drain wiring 21 and also functions as a black matrix, so that the added value of the display device substrate can be improved. Further, when this display device substrate 2E is used in a liquid crystal display device, it is not necessary to form a black matrix in the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

Further, the pseudo pixel electrode P22 and the like are formed from a laminated body of the transparent conductive layer 91 and the first metal layer 92, and further, the exposed first metal layer is formed after the passivation insulating layer 37 and the protective insulating layer 90 are formed. 92 is selectively removed to expose the pixel electrode 22 made of the transparent conductive layer 91 and the like.
Thus, the conductivity and translucency can be improved, and the performance as a display device substrate can be improved. Further, as compared with the third embodiment and the fourth embodiment, the process of selectively removing the first metal layers 92A to 92C can be changed, and the degree of freedom in process design can be expanded.
Further, the first amorphous silicon layer 31 </ b> A in the parasitic transistor preventing opening 67 is selectively removed, and the gate insulating layer 30 </ b> A is exposed in the opening 67. In this way, unnecessary first amorphous silicon 31A in the opening 67 is removed, and generation of a parasitic transistor can be prevented.
Further, since the glass substrate 2 is transparent and has an insulating property, and the passivation insulating layer 37 is transparent, the translucency can be improved, and when used in a liquid crystal display device, Image quality can be improved.

Preferably, the storage capacitor line 16 or the like may be formed and the storage capacitor forming region 52 may be provided. Thus, the gradation of the display image can be improved, and the added value as a display device substrate can be improved.
The storage capacitor formation region 52 of the present embodiment forms a storage capacitor by planarly overlapping the storage electrode 72 and the storage capacitor line 16 that connect the pair of pixel electrodes 22 with the gate insulating layer 30 interposed therebetween. Yes.

As described above, the display device substrate 2E of this embodiment can be manufactured by a four-mask process.
Further, although the channel is formed in the formation process of the source / drain wiring, etc., since the halftone exposure technique is not used in the present invention, it is possible to avoid the problem that the channel length varies as in the conventional example. . That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Furthermore, since the opening forming process (final photolithography process) in the protective insulating layer 90 also serves as the BM forming process, the display device substrate 2D is substantially manufactured using three photomasks. It has been done. Therefore, the reduction in the number of manufacturing steps is obvious as compared with the conventional liquid crystal display device.

Moreover, this embodiment has various application examples.
The display device substrate 2E ′ according to the application example of the fifth embodiment is a display device substrate manufactured according to the application example of the fifth embodiment of the method for manufacturing a display device substrate described above (see FIGS. 66 and 67). ).
That is, the protective insulating layer 90 in the spacer region is preferably made thicker than other regions, and the photosensitive black pigment dispersed resin pattern 85A is used as a photo spacer.
In this way, the protective insulating layer 90 protects and insulates the source wiring 12S, the drain wiring 21 and the like, and also functions as a photo spacer, so that the added value of the display device substrate 2E ′ can be improved. Further, when this display device substrate 2E ′ is used in a liquid crystal display device, it is not necessary to form a photo spacer on the color filter, so that the total number of masks in the liquid crystal display device can be reduced. Accordingly, the manufacturing cost can be reduced.

[One Embodiment of Liquid Crystal Display Device and Manufacturing Method Thereof]
The present invention is also effective as an invention of a liquid crystal display device and a manufacturing method thereof.
The liquid crystal display device according to this embodiment includes a display device substrate 2A ′ on which channel-etched insulated gate transistors are formed, a color filter, and a liquid crystal filled between the display device substrate 2A ′ and the color filter. A liquid crystal display device having The display device substrate 2A ′ is a display device substrate according to an application example of the first embodiment of the display device substrate. That is, this liquid crystal display device is formed into a liquid crystal panel by bonding the display device substrate 2A ′ and the color filter 9 on which the BM and the photo spacer are not formed.

As described above, the present invention is also effective as an invention of a liquid crystal display device, and the protective insulating layer 90 protects and insulates the source wiring and drain wiring, and also functions as a black matrix and a photo spacer. Further, it is not necessary to form a black matrix or photo spacer, and the total number of masks in the liquid crystal display device can be reduced. Therefore, the reduction in the number of manufacturing processes, especially the photolithography process, is clear. As a result, the manufacturing cost of the liquid crystal display device can be significantly reduced.
In addition, a channel is formed in the process of forming the source / drain wiring of the display device substrate 2A ′. However, since the halftone exposure technique is not used in the present invention, the channel length varies as in the conventional example. The trouble can be avoided. That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, the present embodiment is configured to use the display device substrate 2A ′, but is not limited thereto. For example, the above-described display device substrates 2A, 2B, 2B ′, 2C, 2C ′, 2E, and 2E ′ may be used.

  In addition, the method for manufacturing a liquid crystal display device according to the present embodiment includes a step of filling a liquid crystal between a color filter and a display device substrate 2A ′ on which a channel-etched insulated gate transistor is formed. In this manufacturing method, the display device substrate is manufactured using the method for manufacturing the display device substrate 2A ′ according to the application example of the first embodiment. That is, in the method for manufacturing the liquid crystal display device, the display device substrate 2A ′ and the color filter 9 on which the BM and the photo spacer are not formed are bonded to form a liquid crystal panel.

As described above, the present invention is also effective as an invention of a manufacturing method of a liquid crystal display device, and the protective insulating layer protects and insulates the source wiring and the drain wiring, and also functions as a black matrix and a photo spacer. It is not necessary to form a black matrix or a photo spacer in the color filter, and the total number of masks in the liquid crystal display device can be reduced. Therefore, the manufacturing cost of the liquid crystal display device can be greatly reduced.
In addition, a channel is formed in the process of forming the source / drain wiring of the display device substrate 2A ′. However, since the halftone exposure technique is not used in the present invention, the channel length varies as in the conventional example. The trouble can be avoided. That is, it is not necessary to perform strict manufacturing management, and yield and image quality can be improved.
Further, the present embodiment is a method using the method for manufacturing the display device substrate 2A ′ described above, but is not limited thereto. For example, a method using the manufacturing method of the display device substrates 2A, 2B, 2B ′, 2C, 2C ′, 2E, and 2E ′ described above may be used.

The display device substrate and the manufacturing method thereof, and the liquid crystal display device and the manufacturing method thereof according to the present invention have been described with reference to the preferred embodiments. The liquid crystal display device and the manufacturing method thereof are not limited to the above-described embodiments, and it goes without saying that various modifications can be made within the scope of the present invention.
For example, the liquid crystal display device is not limited to a transmissive type, and can be applied to a reflective or transflective liquid crystal display device.
It is also clear that the semiconductor layer of the insulated gate transistor is not limited to an amorphous silicon layer.
Further, although not shown in the drawing, an alignment regulating means is provided by making a slit (cut) in the pixel electrode or by leaving a protective insulating layer and a passivation insulating layer in a protruding shape on the pixel electrode. It is also possible to correspond to the liquid crystal mode. Therefore, the viewing angle can be improved along with the process reduction.

  The display device substrate according to the present invention is not limited to the case of being provided in a liquid crystal display device, and can be applied to a display device such as an organic EL display.

FIG. 1: has shown the schematic flowchart figure for demonstrating the manufacturing method of the board | substrate for display apparatuses which concerns on 1st embodiment of this invention. FIG. 2 is a schematic plan view of the display device substrate of the first embodiment in which scanning lines and the like are formed. FIG. 3 is a schematic cross-sectional view of the display device substrate of the first embodiment in which scanning lines and the like are formed. FIG. 4 is a schematic plan view of the display device substrate of the first embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 5 is a schematic cross-sectional view of the display device substrate of the first embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 6 is a schematic plan view of the display device substrate of the first embodiment in which signal lines, pseudo pixel electrodes, channels, and the like are formed. FIG. 7 is a schematic cross-sectional view of the display device substrate of the first embodiment in which signal lines, pseudo pixel electrodes, channels, and the like are formed. FIG. 8 is a schematic plan view of the display device substrate of the first embodiment in which a passivation insulating layer and a protective insulating layer are formed and the pixel electrodes and signal line electrode terminals are exposed. FIG. 9 is a schematic cross-sectional view of the display device substrate according to the first embodiment in which a passivation insulating layer and a protective insulating layer are formed and the pixel electrodes and signal line electrode terminals are exposed. FIG. 10 is a schematic plan view of the display device substrate of the first embodiment in which the scanning line electrode terminals and the like are exposed. FIG. 11 is a schematic cross-sectional view of the display device substrate of the first embodiment in which the scanning line electrode terminals and the like are exposed. FIG. 12 is a schematic plan view of a display device substrate according to an application example of the first embodiment. FIG. 13 is a schematic cross-sectional view of a display device substrate according to an application example of the first embodiment. FIG. 14: has shown the schematic flowchart figure for demonstrating the manufacturing method of the board | substrate for display apparatuses which concerns on 2nd embodiment of this invention. FIG. 15 is a schematic plan view of a display device substrate according to the second embodiment in which scanning lines and the like are formed. FIG. 16 is a schematic cross-sectional view of the display device substrate of the second embodiment in which scanning lines and the like are formed. FIG. 17 is a schematic plan view of the display device substrate of the second embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 18 is a schematic cross-sectional view of a display device substrate according to the second embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 19 is a schematic plan view of a display device substrate of the second embodiment in which signal lines, pseudo pixel electrodes, channels, and the like are formed. FIG. 20 is a schematic cross-sectional view of the display device substrate of the second embodiment in which signal lines, pseudo pixel electrodes, channels, and the like are formed. FIG. 21 is a schematic plan view of a display device substrate according to the second embodiment in which a passivation insulating layer and a protective insulating layer are formed, and pixel electrodes, signal line electrode terminals, and the like are exposed. FIG. 22 is a schematic cross-sectional view of the display device substrate according to the second embodiment in which a passivation insulating layer and a protective insulating layer are formed, and pixel electrodes, signal line electrode terminals, and the like are exposed. FIG. 23 is a schematic plan view of the display device substrate of the second embodiment from which the first amorphous silicon layer in the opening for preventing parasitic transistors is removed. FIG. 24 is a schematic cross-sectional view of the display device substrate of the second embodiment from which the first amorphous silicon layer in the opening for preventing a parasitic transistor is removed. FIG. 25 is a schematic plan view of a display device substrate according to an application example of the second embodiment. FIG. 26 is a schematic cross-sectional view of a display device substrate according to an application example of the second embodiment. FIG. 27 is a schematic flowchart for explaining a method for manufacturing a display device substrate according to the third embodiment of the present invention. FIG. 28 is a schematic plan view of the display device substrate of the third embodiment in which scanning lines and the like are formed. FIG. 29 is a schematic cross-sectional view of the display device substrate of the third embodiment in which scanning lines and the like are formed. FIG. 30 is a schematic plan view of the display device substrate of the third embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 31 is a schematic cross-sectional view of the display device substrate of the third embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 32 is a schematic plan view of the display device substrate of the third embodiment in which the pixel electrodes and the like are exposed. FIG. 33 is a schematic cross-sectional view of the display device substrate of the third embodiment in which pixel electrodes and the like are exposed. FIG. 34 is a schematic plan view of a display device substrate according to the third embodiment in which signal lines, channels, and the like are formed. FIG. 35 is a schematic cross-sectional view of the display device substrate of the third embodiment in which signal lines, channels, and the like are formed. FIG. 36 is a schematic plan view of the display device substrate of the third embodiment in which a passivation insulating layer and a protective insulating layer are formed and the pixel electrodes and the like are exposed. FIG. 37 is a schematic cross-sectional view of the display device substrate of the third embodiment in which a passivation insulating layer and a protective insulating layer are formed and the pixel electrodes and the like are exposed. FIG. 38 is a schematic plan view of the display device substrate of the third embodiment from which the first amorphous silicon layer in the opening for preventing a parasitic transistor has been removed. FIG. 39 is a schematic cross-sectional view of the display device substrate of the third embodiment from which the first amorphous silicon layer in the opening for preventing a parasitic transistor has been removed. FIG. 40 is a schematic plan view of a display device substrate according to an application example of the third embodiment. FIG. 41 is a schematic cross-sectional view of a display device substrate according to an application example of the third embodiment. FIG. 42 is a schematic flowchart for explaining a method for manufacturing a display device substrate according to the fourth embodiment of the present invention. FIG. 43 is a schematic plan view of a display device substrate of the fourth embodiment in which scanning lines and the like are formed. FIG. 44 is a schematic cross-sectional view of the display device substrate of the fourth embodiment in which scanning lines and the like are formed. FIG. 45 is a schematic plan view of a display device substrate according to the fourth embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 46 is a schematic cross-sectional view of the display device substrate of the fourth embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 47 is a schematic plan view of the display device substrate of the fourth embodiment in which signal lines, channels, and the like are formed and pixel electrodes and the like are exposed. FIG. 48 is a schematic cross-sectional view of the display device substrate of the fourth embodiment in which signal lines, channels, and the like are formed and pixel electrodes and the like are exposed. FIG. 49 is a schematic plan view of the display device substrate of the fourth embodiment in which a passivation insulating layer and a protective insulating layer are formed and the pixel electrodes and the like are exposed. FIG. 50 is a schematic cross-sectional view of the display device substrate of the fourth embodiment in which a passivation insulating layer and a protective insulating layer are formed and the pixel electrodes and the like are exposed. FIG. 51 is a schematic plan view of the display device substrate of the fourth embodiment from which the first amorphous silicon layer in the opening for preventing a parasitic transistor has been removed. FIG. 52 is a schematic cross-sectional view of the display device substrate of the fourth embodiment from which the first amorphous silicon layer in the opening for preventing a parasitic transistor has been removed. FIG. 53 is a schematic plan view of a display device substrate according to an application example of the fourth embodiment. FIG. 54 is a schematic cross-sectional view of a display device substrate according to an application example of the fourth embodiment. FIG. 55 is a schematic flowchart for explaining a method for manufacturing a display device substrate according to the fifth embodiment of the present invention. FIG. 56 is a schematic plan view of a display device substrate of the fifth embodiment in which scanning lines and the like are formed. FIG. 57 is a schematic cross-sectional view of the display device substrate of the fifth embodiment in which scanning lines and the like are formed. FIG. 58 is a schematic plan view of a display device substrate of the fifth embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 59 is a schematic cross-sectional view of the display device substrate of the fifth embodiment in which a gate insulating layer, a semiconductor layer, and the like are formed. FIG. 60 is a schematic plan view of a display device substrate according to the fifth embodiment in which signal lines, channels, and the like are formed. FIG. 61 is a schematic cross-sectional view of the display device substrate of the fifth embodiment in which signal lines, channels, and the like are formed. FIG. 62 is a schematic plan view of the display device substrate of the fifth embodiment in which a passivation insulating layer and a protective insulating layer are formed and the pixel electrodes and the like are exposed. FIG. 63 is a schematic cross-sectional view of the display device substrate of the fifth embodiment, in which a passivation insulating layer and a protective insulating layer are formed, and pixel electrodes and the like are exposed. FIG. 64 is a schematic plan view of the display device substrate of the fifth embodiment from which the first amorphous silicon layer in the opening for preventing a parasitic transistor has been removed. FIG. 65 is a schematic cross-sectional view of the display device substrate of the fifth embodiment from which the first amorphous silicon layer in the opening for preventing parasitic transistors has been removed. FIG. 66 is a schematic plan view of a display device substrate according to an application example of the fifth embodiment. FIG. 67 is a schematic cross-sectional view of a display device substrate according to an application example of the fifth embodiment. FIG. 68 is a perspective view showing a mounted state of the liquid crystal panel. FIG. 69 is an equivalent circuit diagram of the liquid crystal display device. FIG. 70 is a cross-sectional view of a main part of an image display unit of a conventional liquid crystal display device. FIG. 71 is a schematic plan view of a conventional active substrate on which scanning lines and the like are formed. FIG. 72 is a schematic cross-sectional view of a conventional active substrate on which scanning lines and the like are formed. FIG. 73 is a schematic plan view of a conventional active substrate in which a gate insulating layer, a channel layer, and a metal layer are stacked. FIG. 74 is a schematic cross-sectional view of a conventional active substrate in which a gate insulating layer, a channel layer, and a metal layer are stacked. FIG. 75 is a schematic plan view of a conventional active substrate on which signal lines and the like are formed. FIG. 76 is a schematic cross-sectional view of a conventional active substrate in which signal lines and the like are formed. FIG. 77 is a schematic plan view of a conventional active substrate on which a source electrode and a drain electrode are formed. FIG. 78 is a schematic cross-sectional view of a conventional active substrate on which a source electrode and a drain electrode are formed. FIG. 79 is a schematic plan view of a conventional active substrate on which a passivation insulating layer is formed. FIG. 80 is a schematic cross-sectional view of a conventional active substrate on which a passivation insulating layer is formed. FIG. 81 is a schematic plan view of a conventional active substrate on which pixel electrodes and the like are formed. FIG. 82 is a schematic cross-sectional view of a conventional active substrate on which pixel electrodes and the like are formed.

Explanation of symbols

1: Liquid crystal panel 2: Glass substrates 2A, 2A ′, 2B, 2B ′, 2C, 2C ′: Display device substrates (active substrates)
2D, 2D ', 2E, 2E': Display device substrate (active substrate)
2F: Display device substrate (active substrate)
3: Semiconductor integrated circuit chip 4: TCP film 5: Part of scanning line or electrode terminal 5A: Scanning line electrode terminal (electrode terminal)
P5, P5 ': Scanning line pseudo electrode terminal 6: A part of signal line or electrode terminal 6A: Signal line electrode terminal (electrode terminal)
P6: Signal line pseudo electrode terminal 7: Wiring path 7A: Storage capacitor line electrode terminal (electrode terminal)
P7, P7 ′: Pseudo electrode terminal for storage capacitor line 8: Wiring path 9: Color filter (opposing glass substrate)
10: insulated gate transistor 11: scanning line 11A: gate wiring, gate electrode 11P: protective wiring 12: signal line (source wiring, source electrode)
12S: source wiring 13: liquid crystal cell 14: counter electrode 15: storage capacitor portion (storage capacitor)
16: Storage capacitor line 17: Liquid crystal 18: Colored layer 19: Polarizing plate 20: Polyimide resin thin film 21: Drain electrode (drain wiring)
21P: pixel connection electrode 22: pixel electrode P22: pseudo pixel electrode 23: semiconductor layer 24: Cr thin film layer 30: gate insulating layer 31: first amorphous silicon layer 33: second amorphous silicon layer 34: Second metal layer (heat-resistant metal layer)
34 ': heat-resistant metal layer (buffer metal layer)
34C2: Storage electrode 35: Third metal layer (low resistance metal layer)
35 ': second metal layer (metal layer for source / drain wiring)
36: buffer conductive layer 37: passivation insulating layer 38: pixel electrode opening 40: transparent conductive layer pattern 50, 52: storage capacitor forming region 61A: source electrode opening 62, 62A: drain electrode opening (opening) )
63, 63A: Openings for electrode terminals (openings)
64: Electrode terminal opening (opening)
65, 65A: electrode terminal opening (opening)
66, 66A: Storage electrode opening (opening)
67: Opening for preventing parasitic transistors 72: Storage electrodes 80A, 80B: Photosensitive resin patterns 84, 84A, 84B: Photosensitive resin patterns 85A, 85B: Photosensitive black pigment dispersed resin pattern 90: Protective insulating layer 91: Transparent conductive Layer 92: first metal layer (gate conductive layer)
93: Pseudo pixel electrode 94: Scanning line pseudo electrode terminal 95: Signal line pseudo electrode terminal 96: Storage capacitor line pseudo electrode terminal

Claims (20)

A gate electrode formed from a gate conductive layer deposited on one main surface of the substrate, a scanning line and a scanning line electrode terminal;
A gate insulating layer deposited on the substrate, gate electrode, scanning line and scanning line electrode terminal;
A first amorphous silicon layer containing no impurities, a second amorphous silicon layer containing impurities, and a source / layer formed on the gate electrode in succession after the gate insulating layer. A drain electrode conductive layer, and a channel, a source electrode, and a source formed from a multilayer body including a transparent conductive layer and a signal line conductive layer sequentially deposited on the source / drain electrode conductive layer and the gate insulating layer. Wiring, signal line, pseudo electrode terminal for signal line, drain electrode, drain wiring and pseudo pixel electrode;
The channel, the source electrode, the source wiring, the signal line, the pseudo electrode terminal for the signal line, the drain electrode, the drain wiring, and the pseudo pixel electrode are sequentially deposited on the substrate on which the pseudo pixel electrode is formed. A passivation insulating layer and a protective insulating layer formed with an opening, an electrode terminal opening on the scanning line electrode terminal, and an electrode terminal opening on the signal line pseudo electrode terminal;
A pixel electrode and a signal line electrode terminal made of the transparent conductive layer exposed by removing the signal line conductive layer from the pseudo pixel electrode and the signal line pseudo electrode terminal;
A display device substrate, comprising: an electrode terminal opening formed in the gate insulating layer exposing the scan line electrode terminal. A gate electrode formed from a gate conductive layer deposited on one main surface of the substrate, a scanning line and a pseudo electrode terminal for the scanning line;
A gate insulating layer formed on the substrate, the gate electrode, the scanning line, and the scanning line pseudo electrode terminal in sequence, and formed on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. An amorphous silicon layer, a second amorphous silicon layer containing impurities, a source / drain electrode conductive layer, a transparent conductive layer sequentially deposited on the source / drain electrode conductive layer and the substrate, and A channel, a source electrode, a source wiring, a signal line, a pseudo electrode terminal for a signal line, a pseudo electrode terminal for a scanning line, a drain electrode, a drain wiring, and a pseudo pixel electrode formed from a multilayer body including a signal line conductive layer;
The channel, source electrode, source wiring, signal line, signal line pseudo electrode terminal, scanning line pseudo electrode terminal, drain electrode, drain wiring, and pseudo pixel electrode are sequentially deposited on the substrate, and the pseudo Pixel electrode opening on the pixel electrode, parasitic transistor preventing opening on the scanning line, electrode terminal opening on the scanning line pseudo electrode terminal, and electrode terminal opening on the signal line pseudo electrode terminal A passivation insulating layer and a protective insulating layer formed of
The pixel electrode and the scanning line electrode terminal made of the transparent conductive layer exposed by removing the signal line conductive layer from the pseudo pixel electrode, the scanning line pseudo electrode terminal, and the signal line pseudo electrode terminal. And signal line electrode terminals;
A display device substrate comprising: the gate insulating layer exposed in the opening for preventing a parasitic transistor by removing the first amorphous silicon layer. A gate electrode, a scanning line, a pseudo electrode terminal for a scanning line, a pseudo electrode terminal for a signal line, and a pseudo pixel electrode formed from a laminate including a transparent conductive layer and a gate conductive layer deposited on one main surface of the substrate; ,
The substrate, the gate electrode, the scanning line, the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, and the pseudo pixel electrode are sequentially deposited on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. A gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities;
The pixel electrode composed of the transparent conductive layer, the scanning line electrode terminal, and the signal exposed by removing the gate conductive layer from the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, and the pseudo pixel electrode. Wire electrode terminals;
A multilayer body including the second amorphous silicon layer, the transparent conductive layer, the signal line conductive layer deposited on the substrate, the first amorphous silicon layer, and the second amorphous silicon layer; A formed channel, a source electrode, a source wiring, a signal line connected to the signal line electrode terminal, a drain electrode, and a drain wiring connected to the pixel electrode;
The channel, the source electrode, the source wiring, the signal line, the signal line electrode terminal, the scanning line electrode terminal, the drain electrode, the drain wiring, and the pixel electrode are sequentially deposited on the pixel electrode. Passivation insulation in which a pixel electrode opening, a parasitic transistor preventing opening on the scanning line, an electrode terminal opening on the scanning line electrode terminal, and an electrode terminal opening on the signal line electrode terminal are formed. Layers and protective insulating layers;
A display device substrate comprising: the gate insulating layer exposed in the opening for preventing a parasitic transistor by removing the first amorphous silicon layer. A gate electrode, a scanning line, a pseudo electrode terminal for a scanning line, a pseudo electrode terminal for a signal line, and a pseudo pixel electrode formed from a laminate including a transparent conductive layer and a gate conductive layer deposited on one main surface of the substrate; ,
The substrate, the gate electrode, the scanning line, the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, and the pseudo pixel electrode are sequentially deposited on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. A gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities;
A multi-layer body including the second amorphous silicon layer, the gate conductive layer and the signal line conductive layer deposited on the substrate, the first amorphous silicon layer and the second amorphous silicon layer; A channel formed, a source electrode, a source wiring, a signal line connected to the pseudo electrode terminal for signal lines, a drain electrode, and a drain wiring connected to the pseudo pixel electrode;
The pixel electrode composed of the transparent conductive layer, the scanning line electrode terminal, and the signal exposed by removing the gate conductive layer from the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, and the pseudo pixel electrode. Wire electrode terminals;
The channel, the source electrode, the source wiring, the signal line, the signal line electrode terminal, the scanning line electrode terminal, the drain electrode, the drain wiring, and the pixel electrode are sequentially deposited on the pixel electrode. Passivation insulation in which a pixel electrode opening, a parasitic transistor preventing opening on the scanning line, an electrode terminal opening on the scanning line electrode terminal, and an electrode terminal opening on the signal line electrode terminal are formed. Layers and protective insulating layers;
A display device substrate comprising: the gate insulating layer exposed in the opening for preventing a parasitic transistor by removing the first amorphous silicon layer. A gate electrode, a scanning line, a pseudo electrode terminal for a scanning line, a pseudo electrode terminal for a signal line, and a pseudo pixel electrode formed from a laminate including a transparent conductive layer and a gate conductive layer deposited on one main surface of the substrate; ,
The substrate, the gate electrode, the scanning line, the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, and the pseudo pixel electrode are sequentially deposited on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. A gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities;
A multi-layer body including the second amorphous silicon layer, the gate conductive layer and the signal line conductive layer deposited on the substrate, the first amorphous silicon layer and the second amorphous silicon layer; A channel formed, a source electrode, a source wiring, a signal line connected to the pseudo electrode terminal for signal lines, a drain electrode, and a drain wiring connected to the pseudo pixel electrode;
The channel, source electrode, source wiring, signal line, signal line pseudo electrode terminal, scanning line pseudo electrode terminal, drain electrode, drain wiring, and pseudo pixel electrode are sequentially deposited on the substrate, and the pseudo Pixel electrode opening on the pixel electrode, parasitic transistor preventing opening on the scanning line, electrode terminal opening on the scanning line pseudo electrode terminal, and electrode terminal opening on the signal line pseudo electrode terminal A passivation insulating layer and a protective insulating layer formed of
The pixel electrode composed of the transparent conductive layer, the scanning line electrode terminal, and the signal exposed by removing the gate conductive layer from the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, and the pseudo pixel electrode. Wire electrode terminals;
A display device substrate comprising: the gate insulating layer exposed in the opening for preventing a parasitic transistor by removing the first amorphous silicon layer.   The display device substrate according to claim 1, wherein the protective insulating layer has a light shielding property.   The display device substrate according to claim 1, wherein the protective insulating layer in the spacer region is thicker than other regions.   8. A storage capacitor to which the pixel electrode and one electrode are connected, a storage capacitor line connected to the other electrode of the storage capacitor, and an electrode terminal for the storage capacitor line are formed. The display device substrate according to any one of the above.   The display device substrate according to claim 1, wherein the substrate is transparent and has an insulating property, and the passivation insulating layer is transparent. Forming a gate electrode, a scanning line and a scanning line electrode terminal made of a first metal layer on one main surface of the substrate;
Sequentially depositing a gate insulating layer, a first amorphous silicon layer containing no impurities, a second amorphous silicon layer containing impurities, and a second metal layer;
Forming a stack including the first amorphous silicon layer, the second amorphous silicon layer, and the second metal layer in an island shape on the gate electrode, and exposing the gate insulating layer; ,
A transparent conductive layer and a third metal layer are deposited, one of the third metal layer, the transparent conductive layer, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer. A source line, a drain line, a signal line, a pseudo pixel electrode, and a pseudo electrode terminal for a signal line, each of which includes a channel, a source electrode, a drain electrode, and a laminate including the transparent conductive layer and the third metal layer. Forming a step;
Depositing a passivation insulating layer;
A protective insulating layer having an electrode terminal opening on the scanning line electrode terminal, an electrode terminal opening on the signal line pseudo-electrode terminal, and a pixel electrode opening on the pseudo-pixel electrode; Forming on the passivation insulating layer;
Selectively removing the passivation insulating layer and exposing the pseudo electrode terminal for signal lines and the pseudo pixel electrode;
Selectively removing the third metal layer and exposing a signal line electrode terminal and a pixel electrode made of the transparent conductive layer;
And a step of selectively removing the gate insulating layer and exposing the scanning line electrode terminal made of the first metal layer. Forming a gate electrode made of a first metal layer, a scanning line and a pseudo electrode terminal for scanning line on one main surface of the substrate;
Sequentially depositing a gate insulating layer, a first amorphous silicon layer containing no impurities, a second amorphous silicon layer containing impurities, and a second metal layer;
A stacked body including the gate insulating layer, the first amorphous silicon layer, the second amorphous silicon layer, and the second metal layer over the gate electrode and the scanning line is wider than the gate electrode and the scanning line. Forming and exposing the scanning line pseudo electrode terminal and the substrate;
A transparent conductive layer and a third metal layer are deposited, one of the third metal layer, the transparent conductive layer, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer. A source line, a drain line, a signal line, a pseudo pixel electrode, and a scanning line pseudo electrode terminal made of a laminate including the transparent conductive layer and the third metal layer. And forming a pseudo electrode terminal for a signal line;
Depositing a passivation insulating layer;
Electrode terminal opening on the scanning line pseudo electrode terminal, electrode terminal opening on the signal line pseudo electrode terminal, pixel electrode opening on the pseudo pixel electrode, and parasitic transistor on the scanning line Forming a protective insulating layer having an opening for prevention on the passivation insulating layer;
Selectively removing the passivation insulating layer, exposing the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, the pseudo pixel electrode, and the first amorphous silicon layer in each of the openings;
Selectively removing the third metal layer and exposing the scanning line electrode terminal, the signal line electrode terminal and the pixel electrode made of the transparent conductive layer;
Selectively removing the first amorphous silicon layer in the opening for preventing the parasitic transistor and exposing the gate insulating layer in the opening for preventing the parasitic transistor. . Forming a gate electrode, a scanning line, a scanning line pseudo electrode terminal, a pseudo pixel electrode, and a signal line pseudo electrode terminal made of a laminate including a transparent conductive layer and a first metal layer on one main surface of the substrate; When,
Sequentially depositing a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities;
A stack including the gate insulating layer, the first amorphous silicon layer, and the second amorphous silicon layer is formed on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. Exposing the pseudo electrode terminal, the pseudo pixel electrode, the signal line pseudo electrode terminal, and the substrate;
Removing the first metal layer and exposing a scanning line electrode terminal, a pixel electrode and a signal line electrode terminal made of the transparent conductive layer;
Depositing one or more second metal layers including a refractory metal layer, removing a portion of the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer; Forming a channel, a source electrode and a drain electrode, and a source wiring, a drain wiring, and a signal line made of the second metal layer;
Depositing a passivation insulating layer;
Electrode terminal opening on the scanning line electrode terminal, electrode terminal opening on the signal line electrode terminal, pixel electrode opening on the pixel electrode, and parasitic transistor prevention opening on the scanning line Forming a protective insulating layer having a portion on the passivation insulating layer;
Selectively removing the passivation insulating layer, exposing the scanning line electrode terminal, the signal line electrode terminal, the pixel electrode, and the first amorphous silicon layer in each of the openings;
Selectively removing the first amorphous silicon layer in the opening for preventing the parasitic transistor and exposing the gate insulating layer in the opening for preventing the parasitic transistor. . Forming a gate electrode, a scanning line, a scanning line pseudo electrode terminal, a pseudo pixel electrode, and a signal line pseudo electrode terminal made of a laminate including a transparent conductive layer and a first metal layer on one main surface of the substrate; When,
Sequentially depositing a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities;
A stack including the gate insulating layer, the first amorphous silicon layer, and the second amorphous silicon layer is formed on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. Exposing the pseudo electrode terminal, the pseudo pixel electrode, the signal line pseudo electrode terminal, and the substrate;
One or more second metal layers including a refractory metal layer are deposited, and the second metal layer, the first metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are formed. Part is removed to form a channel, a source electrode and a drain electrode, and a source wiring, a drain wiring and a signal line made of the second metal layer, and a scanning line electrode terminal and a pixel electrode made of the transparent conductive layer And exposing the signal line electrode terminals;
Depositing a passivation insulating layer;
Electrode terminal opening on the scanning line electrode terminal, electrode terminal opening on the signal line electrode terminal, pixel electrode opening on the pixel electrode, and parasitic transistor prevention opening on the scanning line Forming a protective insulating layer having a portion on the passivation insulating layer;
Selectively removing the passivation insulating layer, exposing the scanning line electrode terminal, the signal line electrode terminal, the pixel electrode, and the first amorphous silicon layer in each of the openings;
Selectively removing the first amorphous silicon layer in the opening for preventing the parasitic transistor and exposing the gate insulating layer in the opening for preventing the parasitic transistor. . Forming a gate electrode, a scanning line, a scanning line pseudo electrode terminal, a pseudo pixel electrode, and a signal line pseudo electrode terminal made of a laminate including a transparent conductive layer and a first metal layer on one main surface of the substrate; When,
Sequentially depositing a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities;
A stack including the gate insulating layer, the first amorphous silicon layer, and the second amorphous silicon layer is formed on the gate electrode and the scanning line so as to be wider than the gate electrode and the scanning line. Exposing the pseudo electrode terminal, the pseudo pixel electrode, the signal line pseudo electrode terminal, and the substrate;
Depositing one or more second metal layers including a refractory metal layer, removing a portion of the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer; Forming a channel, a source electrode and a drain electrode, and a source wiring, a drain wiring, and a signal line made of the second metal layer;
Depositing a passivation insulating layer;
Electrode terminal opening on the scanning line pseudo electrode terminal, electrode terminal opening on the signal line pseudo electrode terminal, pixel electrode opening on the pseudo pixel electrode, and parasitic transistor on the scanning line Forming a protective insulating layer having an opening for prevention on the passivation insulating layer;
Selectively removing the passivation insulating layer, exposing the scanning line pseudo electrode terminal, the signal line pseudo electrode terminal, the pseudo pixel electrode, and the first amorphous silicon layer in each of the openings;
Selectively removing the first metal layer and exposing a scanning line electrode terminal, a signal line electrode terminal and a pixel electrode made of the transparent conductive layer in each of the openings;
Selectively removing the first amorphous silicon layer in the opening for preventing the parasitic transistor and exposing the gate insulating layer in the opening for preventing the parasitic transistor. .   The method for manufacturing a substrate for a display device according to claim 10, wherein the protective insulating layer has a light shielding property.   The method for manufacturing a substrate for a display device according to any one of claims 10 to 15, wherein the protective insulating layer in the spacer region is thicker than other regions.   17. A storage capacitor to which the pixel electrode and one electrode are connected, a storage capacitor line connected to the other electrode of the storage capacitor, and an electrode terminal for the storage capacitor line are formed. The manufacturing method of the board | substrate for display apparatuses as described in any one of these.   18. The display device substrate according to claim 10, wherein the substrate is transparent and has an insulating property, and further, the passivation insulating layer is transparent. Method. In a liquid crystal display device having a display device substrate on which a thin film transistor is formed, a counter substrate or a color filter, and liquid crystal filled between the display device substrate and the counter substrate or the color filter.
The said display apparatus substrate is a display apparatus substrate as described in any one of the said Claims 1-9, The liquid crystal display device characterized by the above-mentioned. In a method for manufacturing a liquid crystal display device comprising a step of filling a liquid crystal between a display device substrate on which a thin film transistor is formed and a counter substrate or a color filter
A method for manufacturing a liquid crystal display device, wherein the display device substrate is manufactured using the method for manufacturing a display device substrate according to any one of claims 10 to 18.

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