JP2009004664A - Manufacturing method for board with built-in components - Google Patents

Manufacturing method for board with built-in components Download PDF

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JP2009004664A
JP2009004664A JP2007165725A JP2007165725A JP2009004664A JP 2009004664 A JP2009004664 A JP 2009004664A JP 2007165725 A JP2007165725 A JP 2007165725A JP 2007165725 A JP2007165725 A JP 2007165725A JP 2009004664 A JP2009004664 A JP 2009004664A
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component mounting
component
substrate
board
boards
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Yoji Ueda
洋二 上田
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Panasonic Corp
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Panasonic Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a board with built-in components that achieves the low profile size and improves the reliability. <P>SOLUTION: In a manufacturing method for a board with built-in components, step (d) places a component mounting board 1 with components mounted on its both sides at a center, and arranges to stack first and second support substrates 2a, 2b having the thermal expansion coefficient equal to or almost close to that of the component mounting board 1, while arranging insulating layers 3a, 3b in a pre-curing state between the component mounting board 1 and the first and second support substrates 2a, 2b, step (e) heats and presses the first and second support substrates 2a, 2b in a stack direction to cure the insulating layers 3a, 3b for integration, and step (f) leaves pattern electrodes 103c, 103d and removes the first and second support substrates 2a, 2b to expose the pattern electrodes 103c, 103d. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、部品内蔵基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a component-embedded substrate.

電子機器の小型化、高機能化、高密度化および低コスト化の要求に伴い、更なる実装密度の向上や基板の低背化が求められている。高密度実装の一例として、無機質フィラーと熱硬化性樹脂との混合物内に、既存部品である能動部品や受動部品を埋め込んだ部品内蔵基板が提案されている。   With the demand for downsizing, high functionality, high density, and low cost of electronic devices, further improvement in mounting density and reduction in the height of the substrate are required. As an example of high-density mounting, a component-embedded substrate in which active components and passive components that are existing components are embedded in a mixture of an inorganic filler and a thermosetting resin has been proposed.

特許文献1には、図17(a)(b)(c)に示すように多層回路基板に表面実装後無機質フィラーと熱硬化性樹脂との混合物を用いて部品内蔵基板を実現した高密度実装技術が記載されている。   In Patent Document 1, as shown in FIGS. 17 (a), (b), and (c), high-density mounting in which a component-embedded substrate is realized using a mixture of an inorganic filler and a thermosetting resin after surface mounting on a multilayer circuit board. The technology is described.

図17(a)(b)において、401a,401bは片側に半導体素子404aや電子部品406aを表面に実装した多層回路基板である。2つの多層回路基板401a,401bの間にコンポジットシート407を配置し、これを熱プレスにて加熱加圧することによって部品を内蔵した基板が作成されている。   17A and 17B, 401a and 401b are multilayer circuit boards having a semiconductor element 404a and an electronic component 406a mounted on the surface on one side. A composite sheet 407 is disposed between the two multilayer circuit boards 401a and 401b, and this is heated and pressed by a hot press to produce a board with built-in components.

コンポジットシート407はエポキシなどの樹脂にシリカなどのセラミック粉を配合した回路基板用絶縁部材で、多層回路基板401a,401bを接続するためパターン電極402の位置に導電性ペースト403が充填されていると共に、あらかじめ部品の入るスペース405が形成されている。   The composite sheet 407 is an insulating member for a circuit board in which ceramic powder such as silica is blended in a resin such as epoxy, and the conductive paste 403 is filled at the position of the pattern electrode 402 to connect the multilayer circuit boards 401a and 401b. A space 405 into which parts are placed is formed in advance.

熱プレス後、図17(c)に示すように半導体素子404bや電子部品406bを表面に実装することにより部品内蔵基板が完成する。
特許文献2には、図18(a)〜(i)に示す工程で作成して低背化を実現した部品内蔵基板が記載されている。
After hot pressing, the component-embedded substrate is completed by mounting the semiconductor element 404b and the electronic component 406b on the surface as shown in FIG.
Patent Document 2 describes a component-embedded substrate that has been made by the steps shown in FIGS.

図18(a)では、金属の支持層30のパターン電極31に電子部品32を導電性接合材33で実装して部品実装基板を作成する。
図18(b)では、図18(a)で作成した部品実装基板と、金属の支持層35にパターン電極36が形成されたものとの間に、プレプレグ34(上記コンポジットシートでも構わない)を配置し、これを熱プレスにて加熱加圧する。つぎに支持層30,35を剥離することによって図18(c)に示すように低背化された部品内蔵基板ができる。
In FIG. 18A, an electronic component 32 is mounted on a pattern electrode 31 of a metal support layer 30 with a conductive bonding material 33 to create a component mounting board.
18B, a prepreg 34 (which may be the composite sheet described above) is provided between the component mounting board created in FIG. 18A and the metal support layer 35 on which the pattern electrode 36 is formed. It arrange | positions and this is heat-pressed with a hot press. Next, by peeling off the support layers 30 and 35, a component-embedded substrate with a reduced height can be obtained as shown in FIG.

図18(d)では、上下のパターン電極31,36の接続用にビア37を形成する。
図18(e)では電子部品39をパターン電極31に導電性接合材40で実装する。
その後は、図18(f)〜(h)に示すように、金属の支持層42に形成されたパターン電極43およびプリプレグ41を用いて、以下同様にプロセスを繰り返すことで図18(h)に示した多段の部品内蔵基板を作成することができる。
特開2003−197849公報(12頁、図7) WO2005/004567公報(12頁、図4)
In FIG. 18D, a via 37 is formed for connecting the upper and lower pattern electrodes 31 and 36.
In FIG. 18E, the electronic component 39 is mounted on the pattern electrode 31 with the conductive bonding material 40.
Thereafter, as shown in FIGS. 18 (f) to 18 (h), the process is repeated in the same manner using the pattern electrode 43 and the prepreg 41 formed on the metal support layer 42. The multistage component-embedded substrate shown can be produced.
JP2003-197849A (page 12, FIG. 7) WO 2005/004567 (12 pages, FIG. 4)

しかしながら、特許文献1の構成では、多層回路基板を複数用いていることから、部品内蔵基板の低背化が課題となってくる。特許文献2では、低背化は可能であるが図18(i)に示すように接続用のビア44が傾いて位置ずれが発生するという課題がある。以下、原因を簡単に説明する。   However, in the configuration of Patent Document 1, since a plurality of multilayer circuit boards are used, it is a problem to reduce the height of the component built-in board. In Patent Document 2, although a reduction in height is possible, there is a problem in that the connection via 44 is inclined and positional displacement occurs as shown in FIG. The cause will be briefly described below.

図18(f)において、支持層42に使用している金属(SUS、銅など)は、プリプレグ41より一般的に熱膨張係数が高い。熱プレス時のプリプレグ41は、未硬化の状態であり流動性がある。そのため、プレスの熱を受けることによって支持層42がプリプレグ41より延びが大きくなる。そのとき層間接続用のビア44の前記支持層42の側が、支持層42の延びと共に広がる。この様に、ビア44の位置がずれることにより、信頼性悪化の一つの要因となる。   In FIG. 18 (f), the metal (SUS, copper, etc.) used for the support layer 42 generally has a higher thermal expansion coefficient than the prepreg 41. The prepreg 41 at the time of hot pressing is in an uncured state and has fluidity. Therefore, the support layer 42 extends more than the prepreg 41 by receiving heat from the press. At that time, the support layer 42 side of the via 44 for interlayer connection spreads with the extension of the support layer 42. As described above, the position of the via 44 is shifted, which becomes one factor of deterioration of reliability.

本発明は、前記従来の課題を解決するもので、低背化と信頼性を向上させた部品内蔵基板の製造方法を提供することを目的とする。   The present invention solves the above-described conventional problems, and an object thereof is to provide a method for manufacturing a component-embedded board that has a reduced height and improved reliability.

本発明の請求項1記載の部品内蔵基板の製造方法は、両面に部品を実装した部品実装基板を中央にして、前記部品実装基板との対向面にパターン電極を有し熱膨張係数が前記部品実装基板と同じかほぼ近い第1,第2の支持基板を積層配置するとともに、前記部品実装基板と第1,第2の支持基板との間には、層間接続用のビアと部品実装基板に実装された前記部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、第1,第2の支持基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、前記一体化の後に、前記パターン電極を残して第1,第2の支持基板を剥離して前記パターン電極を露出させることを特徴とする。   According to a first aspect of the present invention, there is provided a method of manufacturing a component-embedded substrate, wherein a component mounting substrate having components mounted on both sides is centered, and a pattern electrode is provided on a surface facing the component mounting substrate, and the thermal expansion coefficient is The first and second support substrates that are the same as or substantially the same as the mounting substrate are stacked and disposed between the component mounting substrate and the first and second supporting substrates, with vias for interlayer connection and the component mounting substrate. An insulating layer in a pre-curing state in which a space is formed corresponding to the position of the mounted component is disposed, and the insulating layer is cured by heating and pressing the first and second support substrates in the stacking direction. After the integration, the pattern electrode is exposed by peeling the first and second support substrates while leaving the pattern electrode.

本発明の請求項2記載の部品内蔵基板の製造方法は、請求項1において、前記部品実装基板のプリプレグシートを、熱硬化性樹脂と無機フィラーとを含む混合物で構成することを特徴とする。   The component-embedded substrate manufacturing method according to claim 2 of the present invention is characterized in that, in claim 1, the prepreg sheet of the component mounting substrate is composed of a mixture containing a thermosetting resin and an inorganic filler.

本発明の請求項3記載の部品内蔵基板の製造方法は、請求項1において、前記部品実装基板を、セラミック多層基板で構成することを特徴とする。
本発明の請求項4記載の部品内蔵基板の製造方法は、部品が実装された部品実装基板の実装面に、前記部品実装基板との対向面にパターン電極を有し熱膨張係数が前記部品実装基板と同じかほぼ近い第1の支持基板を積層配置するとともに、前記部品実装基板と第1の支持基板との間には、層間接続用のビアと部品実装基板に実装された前記部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、第1の支持基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、前記一体化の後に、前記部品実装基板の実装面のパターン電極と第1の支持基板の前記パターン電極を残して前記部品実装基板と第1の支持基板を剥離してパターン電極を露出させることを特徴とする。
According to a third aspect of the present invention, there is provided a component-embedded substrate manufacturing method according to the first aspect, wherein the component mounting substrate is formed of a ceramic multilayer substrate.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a component-embedded substrate, wherein a mounting surface of the component mounting substrate on which the component is mounted has a pattern electrode on the surface facing the component mounting substrate, and the coefficient of thermal expansion is the component mounting. A first support substrate that is the same as or almost the same as the substrate is stacked and disposed between the component mounting substrate and the first support substrate, and vias for interlayer connection and positions of the components mounted on the component mounting substrate An insulating layer in a pre-curing state in which a space is formed corresponding to the above is disposed, and the first supporting substrate is heated and pressed in the laminating direction to cure and integrate the insulating layer, and after the integration, The pattern electrode is exposed by peeling the component mounting substrate and the first support substrate while leaving the pattern electrode on the mounting surface of the component mounting substrate and the pattern electrode of the first support substrate.

本発明の請求項5記載の部品内蔵基板の製造方法は、互いの熱膨張係数が同じかほぼ近い第1,第2の部品実装基板を部品が実装されたそれぞれの実装面が対向するように積層配置するとともに、第1,第2の部品実装基板との間には、層間接続用のビアと第1,第2の部品実装基板に実装された前記部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、第1,第2の部品実装基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、前記一体化の後に、第1,第2の部品実装基板の実装面のパターン電極を残して第1,第2の部品実装基板を剥離してパターン電極を露出させることを特徴とする。   In the method of manufacturing a component-embedded board according to claim 5 of the present invention, the first and second component mounting boards having the same or almost the same thermal expansion coefficient as each other are arranged so that the mounting surfaces on which the components are mounted face each other. In addition to the stacked arrangement, a space is formed between the first and second component mounting boards corresponding to the positions of the vias for interlayer connection and the components mounted on the first and second component mounting boards. The pre-curing insulating layer is disposed, and the first and second component mounting boards are heated and pressed in the laminating direction to cure and integrate the insulating layer. The pattern electrode is exposed by peeling the first and second component mounting boards while leaving the pattern electrodes on the mounting surface of the two component mounting boards.

本発明の請求項6記載の部品内蔵基板の製造方法は、請求項4または請求項5に記載の部品内蔵基板を内装基板とし、この内装基板を中央にして、前記内装基板との対向面にパターン電極を有し熱膨張係数が前記内装基板と同じかほぼ近い第3,第4の部品実装基板を積層配置するとともに、前記内装基板と第3,第4の部品実装基板との間には、層間接続用のビアと第3,第4の部品実装基板に実装された部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、第3,第4の部品実装基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、前記一体化の後に、第3,第4の部品実装基板の実装面のパターン電極を残して第3,第4の部品実装基板を剥離して前記パターン電極を露出させることを特徴とする。   According to a sixth aspect of the present invention, there is provided a method of manufacturing a component-embedded substrate, wherein the component-embedded substrate according to claim 4 or 5 is used as an interior substrate, and the interior substrate is centered on a surface facing the interior substrate. A third and fourth component mounting boards having a pattern electrode and having a thermal expansion coefficient the same as or substantially the same as that of the interior board are stacked and disposed between the interior board and the third and fourth component mount boards. In addition, an insulating layer in a pre-curing state in which a space is formed corresponding to the position of the vias for interlayer connection and the parts mounted on the third and fourth component mounting boards is disposed, and the third and fourth components are arranged. The mounting substrate is heated and pressed in the stacking direction to cure and integrate the insulating layer. After the integration, the third and fourth pattern electrodes on the mounting surface of the third and fourth component mounting substrates are left. The component mounting board is peeled off to expose the pattern electrode.

本発明の請求項7記載の部品内蔵基板の製造方法は、層間接続用のビアとパターン電極を有する多層回路基板を中央にして、前記多層回路基板との対向面にパターン電極を有し熱膨張係数が前記多層回路基板と同じかほぼ近い第3,第4の部品実装基板を積層配置するとともに、前記多層回路基板と第3,第4の部品実装基板との間には、層間接続用のビアと第3,第4の部品実装基板に実装された部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、第3,第4の部品実装基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、前記一体化の後に、第3,第4の部品実装基板の実装面のパターン電極を残して第3,第4の部品実装基板を剥離して前記パターン電極を露出させることを特徴とする。   According to a seventh aspect of the present invention, there is provided a method of manufacturing a component-embedded substrate having a multilayer circuit board having interlayer connection vias and pattern electrodes as a center, and having a pattern electrode on a surface facing the multilayer circuit board, and thermal expansion. The third and fourth component mounting boards having the same or substantially the same coefficient as the multilayer circuit board are stacked and disposed between the multilayer circuit board and the third and fourth component mounting boards. An insulating layer in a pre-curing state in which a space is formed corresponding to the position of the component mounted on the via and the third and fourth component mounting boards is disposed, and the third and fourth component mounting boards are arranged in the stacking direction. After the integration, the third and fourth component mounting boards are peeled off, leaving the pattern electrodes on the mounting surfaces of the third and fourth component mounting boards. Then, the pattern electrode is exposed.

本発明の請求項8記載の部品内蔵基板の製造方法は、請求項7において、前記多層回路基板を、セラミック多層基板で構成することを特徴とする。   According to an eighth aspect of the present invention, there is provided the component built-in board manufacturing method according to the seventh aspect, wherein the multilayer circuit board is formed of a ceramic multilayer board.

請求項1,請求項4の構成では、加熱加圧して一体化する際の中央の部品実装基板と外側の第1,第2の支持基板との熱膨張係数が同じかほぼ近いので、熱膨張が発生しても部品実装基板と第1,第2の支持基板との間の層間接続用のビアの位置ずれが発生しない。   In the configuration of claims 1 and 4, the thermal expansion coefficients of the central component mounting board and the outer first and second support boards when they are integrated by heating and pressurization are the same or nearly similar. Even if this occurs, the positional displacement of the via for interlayer connection between the component mounting board and the first and second support boards does not occur.

また、請求項5の構成では、加熱加圧して一体化する際の第1,第2の支持基板の熱膨張係数が同じかほぼ近いので、熱膨張が発生しても部品実装基板と第1,第2の支持基板との間の層間接続用のビアの位置ずれが発生しない。   According to the fifth aspect of the present invention, since the thermal expansion coefficients of the first and second support substrates when they are integrated by heating and pressurizing are the same or nearly similar, even if thermal expansion occurs, , Misalignment of the via for interlayer connection with the second support substrate does not occur.

また、請求項6の構成では、加熱加圧して一体化する際の内装基板と第3,第4の部品実装基板の熱膨張係数が同じかほぼ近いので、熱膨張が発生しても内装基板と第3,第4の支持基板との間の層間接続用のビアの位置ずれが発生しない。   According to the sixth aspect of the present invention, since the thermal expansion coefficients of the interior board and the third and fourth component mounting boards when integrated by heating and pressurization are the same or nearly similar, the interior board even if thermal expansion occurs. Misalignment of interlayer connection vias between the first and third support substrates does not occur.

また、請求項7の構成では、加熱加圧して一体化する際の多層回路基板と第3,第4の部品実装基板の熱膨張係数が同じかほぼ近いので、熱膨張が発生しても多層回路基板と第3,第4の支持基板との間の層間接続用のビアの位置ずれが発生しない。   According to the seventh aspect of the present invention, since the thermal expansion coefficients of the multilayer circuit board and the third and fourth component mounting boards when they are integrated by heating and pressurizing are the same or nearly similar, even if thermal expansion occurs, the multilayer circuit board There is no misalignment of the vias for interlayer connection between the circuit board and the third and fourth support boards.

以下、本発明の部品内蔵基板の製造方法を具体的な各実施の形態に基づいて説明する。
(実施の形態1)
図1〜図4は本発明の実施の形態1を示す。
Hereinafter, a method for manufacturing a component-embedded substrate according to the present invention will be described based on specific embodiments.
(Embodiment 1)
1 to 4 show Embodiment 1 of the present invention.

図1は部品内蔵基板の仕上がり形状を示す。
プリプレグ101aの上下面に形成されたパターン電極103a,103bには、部品として抵抗104a,104bや半導体105a,105bが実装されている。プリプレグ101aの上面に実装された抵抗104aや半導体105aは、絶縁層3aに埋設されている。プリプレグ101aの下面に実装された抵抗104bや半導体105bは、絶縁層3bに埋設されている。絶縁層3aの上面に露出したパターン電極103cには、部品として抵抗104cや半導体105cが実装されている。絶縁層3bの下面に露出したパターン電極103dには、部品として抵抗104dや半導体105dが実装されている。プリプレグ101a,絶縁層3a,3bには、層間接続用のビア10が形成されている。
FIG. 1 shows the finished shape of the component-embedded substrate.
Resistors 104a and 104b and semiconductors 105a and 105b are mounted on the pattern electrodes 103a and 103b formed on the upper and lower surfaces of the prepreg 101a. The resistor 104a and the semiconductor 105a mounted on the upper surface of the prepreg 101a are embedded in the insulating layer 3a. The resistor 104b and the semiconductor 105b mounted on the lower surface of the prepreg 101a are embedded in the insulating layer 3b. A resistor 104c and a semiconductor 105c are mounted as components on the pattern electrode 103c exposed on the upper surface of the insulating layer 3a. A resistor 104d and a semiconductor 105d are mounted as components on the pattern electrode 103d exposed on the lower surface of the insulating layer 3b. Vias 10 for interlayer connection are formed in the prepreg 101a and the insulating layers 3a and 3b.

この部品内蔵基板は、図2(a)〜(c),図3(d)〜(f),図4(g)(h)の工程で製造される。
まず、図2(a)では銅貼り積層板を作成する。
This component-embedded substrate is manufactured in the steps of FIGS. 2A to 2C, FIGS. 3D to 3F, and FIGS. 4G and 4H.
First, in FIG. 2A, a copper-clad laminate is prepared.

手順は、プリプレグ101aにビア10を形成するために、層間接続用の孔(孔径180μm)をパンチングマシンで加工し、そこに導電性ペーストを充填後、9μmの銅箔102a,102bを熱プレスにて加熱加圧し接着する。銅箔102a,102bには片面粗化銅箔を用い、プリプレグ101aに相対する側に粗化面を配置した。   In order to form the via 10 in the prepreg 101a, a hole for interlayer connection (hole diameter: 180 μm) is processed by a punching machine, and after filling with a conductive paste, 9 μm copper foils 102a, 102b are hot-pressed. Heat and press to bond. One-side roughened copper foil was used for the copper foils 102a and 102b, and the roughened surface was disposed on the side facing the prepreg 101a.

図2(b)では、銅貼り積層板の銅箔102a,102bをエッチング法にて加工し、パターン電極103a,103bを形成する。
図2(c)では、パターン電極103a,103bに抵抗104a,104b,半導体105a,105bを実装し、部品実装基板1を作成する。
In FIG. 2B, the copper foils 102a and 102b of the copper-clad laminate are processed by an etching method to form pattern electrodes 103a and 103b.
In FIG. 2C, resistors 104a and 104b and semiconductors 105a and 105b are mounted on the pattern electrodes 103a and 103b, and the component mounting board 1 is created.

図3(d)の部品内蔵工程では、先ず、図2(c)の部品実装基板1を中央にして、その上側には硬化前の絶縁層3aを介して、第1の支持基板2aを配置し、部品実装基板1の下側には絶縁層3bを介して、第2の支持基板2bを配置する。   In the component built-in process in FIG. 3D, first, the component mounting board 1 in FIG. 2C is set at the center, and the first support substrate 2a is disposed on the upper side via the uncured insulating layer 3a. The second support substrate 2b is disposed below the component mounting substrate 1 via the insulating layer 3b.

なお、第1,第2の支持基板2a,2bは、プリプレグ101b,101cに銅箔をプレス工程にて加熱加圧し、片側の銅箔をエッチング法にて加工しパターン電極103c,103dを形成する。もう一方の銅箔はすべて除去した。このときの銅箔は9μmの片面粗化銅箔を使用し、プリプレグ101b,101cと接する面は光沢側とした。   In the first and second support substrates 2a and 2b, copper foil is heated and pressed on the prepregs 101b and 101c in a pressing process, and the copper foil on one side is processed by an etching method to form pattern electrodes 103c and 103d. . All the other copper foil was removed. The copper foil used here was a 9 μm single-side roughened copper foil, and the surface in contact with the prepregs 101b and 101c was the gloss side.

部品実装基板1のプリプレグ101bと第1,第2の支持基板2a,2bのプリプレグ101b,101cとは同じ材質で、ここでは日立化成工業株式会製GEA−67BE(ガラスクロス厚80μm)を用い、9μmの銅箔を温度180℃、圧力10MPaで一体化した。本実施の形態では、熱伝導性が良好なGEA−67BEを使用したが、安価で一般的なガラスエポキシ基板を使用しても構わない。   The prepreg 101b of the component mounting board 1 and the prepregs 101b and 101c of the first and second support boards 2a and 2b are made of the same material. Here, GEA-67BE (glass cloth thickness 80 μm) manufactured by Hitachi Chemical Co., Ltd. is used. A 9 μm copper foil was integrated at a temperature of 180 ° C. and a pressure of 10 MPa. In this embodiment, GEA-67BE having good thermal conductivity is used. However, an inexpensive and general glass epoxy substrate may be used.

絶縁層3a,3bは、それぞれ熱硬化性のエポキシ樹脂とシリカの混合物とし、シリカの添加量を80Wt%としたコンポジットシート107a,107bからできている。まず、1枚のコンポジットシート107aには、部品の入るスペース108を抜き型で形成する。その後もう一枚のコンポジットシート107bをコンポジットシート107aに重ね合わせ、ビア10用の孔をパンチングマシンで加工し、その孔に導電性ペーストが充填されている。   The insulating layers 3a and 3b are made of composite sheets 107a and 107b, each of which is a mixture of a thermosetting epoxy resin and silica, and the amount of silica added is 80 Wt%. First, in one composite sheet 107a, a space 108 into which a part enters is formed with a punching die. Thereafter, another composite sheet 107b is overlaid on the composite sheet 107a, and a hole for the via 10 is processed by a punching machine, and the hole is filled with a conductive paste.

図3(e)では、熱プレスにて一体化を行い部品を内蔵した。部品内蔵工程のプレス条件は、温度200℃、圧力3MPa、時間2時間、真空雰囲気で行った。
図3(f)では、第1の支持基板2aのパターン電極103cと基板2bのパターン電極103dを残して第1,第2の支持基板2a,2bを剥離してパターン電極103c,103dを露出させて部品内蔵基板ができる。
In FIG.3 (e), it integrated by the hot press and incorporated components. The press conditions for the component built-in process were a temperature of 200 ° C., a pressure of 3 MPa, a time of 2 hours, and a vacuum atmosphere.
In FIG. 3F, the pattern electrodes 103c and 103d are exposed by peeling off the first and second support substrates 2a and 2b while leaving the pattern electrode 103c of the first support substrate 2a and the pattern electrode 103d of the substrate 2b. To build a component-embedded board.

上下に配置されているプリプレグ101bを剥離したままの図4(g)に示す状態では、第1,第2の支持基板2a,2bのプリプレグの樹脂成分109が表面に付着していたので、樹脂成分109を研磨加工で取り除いて図4(h)に示すようにパターン電極103c,103dを露出させて部品内蔵基板が完成する。   In the state shown in FIG. 4G with the prepreg 101b disposed above and below being peeled off, the resin component 109 of the prepreg of the first and second support substrates 2a and 2b has adhered to the surface. The component 109 is removed by polishing to expose the pattern electrodes 103c and 103d as shown in FIG.

さらに、必要に応じて図4(i)に示すように、上面と下面のパターン電極103c,103dに部品としての抵抗104c,104dや半導体105c,105dの表面実装を実施する。   Furthermore, as shown in FIG. 4I, surface mounting of the resistors 104c and 104d and the semiconductors 105c and 105d as components is performed on the upper and lower pattern electrodes 103c and 103d as necessary.

このように、部品実装基板1のプリプレグ101aと第1,第2の支持基板2a,2bのプリプレグ101b,101cとが同じ材質であって、部品実装基板1と第1,第2の支持基板2a,2bの熱膨張係数が同じであるため、図3(d)の工程において、硬化前の絶縁層3a,3bを挟んで熱プレスして絶縁層3a,3bを硬化させて一体化する際の部品実装基板1と第1,第2の支持基板2a,2bの伸び量は略同じであるため、ビア10が従来のように傾くことが無く、信頼性の高い層間接続を期待できる。   Thus, the prepreg 101a of the component mounting board 1 and the prepregs 101b and 101c of the first and second support boards 2a and 2b are made of the same material, and the component mounting board 1 and the first and second support boards 2a. , 2b have the same coefficient of thermal expansion, and in the process of FIG. 3D, the insulating layers 3a, 3b are cured and integrated by hot pressing the insulating layers 3a, 3b before curing. Since the component mounting board 1 and the first and second support boards 2a and 2b have substantially the same amount of extension, the via 10 does not tilt as in the prior art, and a highly reliable interlayer connection can be expected.

なお、部品実装基板1のプリプレグ101aと第1,第2の支持基板2a,2bのプリプレグ101b,101cとは同じ材質であったが、熱膨張係数がほぼ同じある場合には材質が異なっていてもよい。具体的には、室温(20℃)〜熱プレス温度(200℃)における熱膨張係数の差が一定値以下なら材質が違っても使用できる。コンデンサなど受動部品および半導体など能動部品の内蔵技術を用いてシステム機能を完結させた3次元実装モジュールの場合、ランドとビアの設計は、通常、ビア径+100μm程度設計する。つまり、ビアとランドとの合致性においては50μmが目安であって、100mmサイズの3次元実装モジュールを仮定した場合、熱膨張係数の差は理想で2.7×10−6/℃以下、最大でも5.4×10−6/℃以下がよく、熱膨張係数の差は6.0×10−6/℃程度以下、さらには3.0×10−6/℃程度以下が良いと言える。部品実装基板1としてセラミック基板を採用した場合に、第1,第2の支持基板2a,2bとしてGEA−67BEまたはガラスエポキシ基板を使用することができる。 The prepreg 101a of the component mounting board 1 and the prepregs 101b and 101c of the first and second support boards 2a and 2b are made of the same material. However, when the thermal expansion coefficients are substantially the same, the materials are different. Also good. Specifically, if the difference in thermal expansion coefficient from room temperature (20 ° C.) to hot press temperature (200 ° C.) is a certain value or less, it can be used even if the material is different. In the case of a three-dimensional mounting module in which the system function is completed using a built-in technology for passive components such as capacitors and active components such as semiconductors, the land and via are usually designed to have a via diameter of about +100 μm. In other words, 50 μm is a standard for conformity between vias and lands, and assuming a 100 mm size three-dimensional mounting module, the difference in thermal expansion coefficient is ideally 2.7 × 10 −6 / ° C. or less, maximum However, it should be 5.4 × 10 −6 / ° C. or less, and the difference in thermal expansion coefficient is preferably about 6.0 × 10 −6 / ° C. or less, and more preferably about 3.0 × 10 −6 / ° C. or less. When a ceramic substrate is employed as the component mounting substrate 1, GEA-67BE or a glass epoxy substrate can be used as the first and second support substrates 2a and 2b.

図2(a)と図3(d)において、層間接続用の孔加工にはパンチングマシンを使用したが、レーザ加工機など他の加工方法でも構わない。
図3(d)において、コンポジットシート107aのスペース108は抜き型を使用したが、他の方法でも構わない。
In FIG. 2A and FIG. 3D, the punching machine is used for the hole processing for interlayer connection, but other processing methods such as a laser processing machine may be used.
In FIG. 3D, the space 108 of the composite sheet 107a uses a punching die, but other methods may be used.

図3(d)において、第1,第2の支持基板2a,2bの片側の銅箔をすべて除去したが、除去する必要はない。
また、図3(d)において、プリプレグ101b,101cの両側に銅箔を配置する必要はなく、片側は離型シートを用い熱プレス後に剥離しても構わない。
In FIG. 3D, the copper foils on one side of the first and second support substrates 2a and 2b are all removed, but it is not necessary to remove them.
Moreover, in FIG.3 (d), it is not necessary to arrange | position copper foil on both sides of prepreg 101b, 101c, and you may peel after hot press using a release sheet on one side.

また、 図3(d)では片面粗化銅箔を使用したが、両面光沢の電解銅箔または圧延銅箔でも構わない。
また、部品実装基板1のパターン電極103a,103b、第1,第2の支持基板2a,2bのパターン電極103c,103dの表面は、金などの金属をメッキしても構わない。
Moreover, although the single side | surface roughening copper foil was used in FIG.3 (d), a double-sided glossy electrolytic copper foil or a rolled copper foil may be sufficient.
The surfaces of the pattern electrodes 103a and 103b of the component mounting substrate 1 and the pattern electrodes 103c and 103d of the first and second support substrates 2a and 2b may be plated with a metal such as gold.

(実施の形態2)
図5〜図8は本発明の実施の形態2を示す。
図1に示した実施の形態1では部品実装基板1のプリプレグ101aが部品内蔵基板に残ったが、図5に示す実施の形態2では、部品内蔵基板に部品実装基板1のプリプレグ101aが残されていない。
(Embodiment 2)
5 to 8 show a second embodiment of the present invention.
In the first embodiment shown in FIG. 1, the prepreg 101a of the component mounting board 1 remains on the component built-in board. In the second embodiment shown in FIG. 5, the prepreg 101a of the component mounting board 1 remains on the component built-in board. Not.

図5は部品内蔵基板の仕上がり形状を示す。
絶縁層3aの下面ではパターン電極103aが露出し、絶縁層3aの上面ではパターン電極103cが露出している。パターン電極103aに実装された部品としての抵抗104a,半導体105aは、絶縁層3aに埋設されている。絶縁層3aには層間接続用のビア10が形成されている。
FIG. 5 shows the finished shape of the component-embedded substrate.
The pattern electrode 103a is exposed on the lower surface of the insulating layer 3a, and the pattern electrode 103c is exposed on the upper surface of the insulating layer 3a. A resistor 104a and a semiconductor 105a as components mounted on the pattern electrode 103a are embedded in the insulating layer 3a. Vias 10 for interlayer connection are formed in the insulating layer 3a.

この部品内蔵基板は、図6(a)〜(c),図7(d)〜(f),図8(g)(h)の工程で製造される。
まず、図6(a)ではプリプレグ101aに9μmの銅箔102a,102bを熱プレスにて加熱加圧し接着した銅貼り積層板を作成する。銅箔102aには片面粗化銅箔を用い、プリプレグ101aに相対する側に光沢面を配置した。
This component-embedded substrate is manufactured by the steps of FIGS. 6A to 6C, FIGS. 7D to 7F, and FIGS. 8G and 8H.
First, in FIG. 6 (a), a copper-clad laminate in which 9 μm copper foils 102a and 102b are bonded to the prepreg 101a by heating and pressing with a hot press is prepared. A single-side roughened copper foil was used as the copper foil 102a, and a glossy surface was disposed on the side facing the prepreg 101a.

次に図6(b)に示すように表面の銅箔102aをエッチング法にて加工し、パターン電極103aを形成する。もう一方の銅箔102bはすべて除去した。
次に図6(c)に示すようにパターン電極103上に部品としての抵抗104a,半導体105aを実装し部品実装基板1を作成する。
Next, as shown in FIG. 6B, the surface copper foil 102a is processed by an etching method to form a pattern electrode 103a. The other copper foil 102b was all removed.
Next, as shown in FIG. 6C, a resistor 104a and a semiconductor 105a as components are mounted on the pattern electrode 103 to produce a component mounting board 1.

図7(d)の部品内蔵工程では、図6(c)で作成した部品実装基板1の上側には絶縁層3aを介して第1の支持基板2aを配置する。
なお、第1の支持基板基板2aは、プリプレグ101bに銅箔をプレス工程にて加熱加圧し、片側の銅箔をエッチング法にて加工しパターン電極103cを形成する。もう一方の銅箔はすべて除去した。このときの銅箔は9μmの片面粗化銅箔を使用し、プリプレグ101bと接する面は光沢側とした。
In the component built-in process of FIG. 7D, the first support substrate 2a is disposed above the component mounting substrate 1 created in FIG. 6C via the insulating layer 3a.
In the first support substrate substrate 2a, a copper foil is heated and pressed on the prepreg 101b in a pressing step, and the copper foil on one side is processed by an etching method to form the pattern electrode 103c. All the other copper foil was removed. The copper foil at this time was a 9 μm single-side roughened copper foil, and the surface in contact with the prepreg 101b was the gloss side.

部品実装基板1のプリプレグ101bと第1の支持基板基板2aのプリプレグ101bとは同じ材質で、ここでは日立化成工業株式会製GEA−67BE(ガラスクロス厚80μm)を用い、9μmの銅箔を温度180℃、圧力10MPaで一体化した。本実施の形態では、熱伝導性が良好なGEA−67BEを使用したが、安価で一般的なガラスエポキシ基板を使用しても構わない。   The prepreg 101b of the component mounting board 1 and the prepreg 101b of the first support board board 2a are made of the same material, here, GEA-67BE (glass cloth thickness 80 μm) manufactured by Hitachi Chemical Co., Ltd. is used, and a 9 μm copper foil is used as the temperature. They were integrated at 180 ° C. and a pressure of 10 MPa. In this embodiment, GEA-67BE having good thermal conductivity is used. However, an inexpensive and general glass epoxy substrate may be used.

絶縁層3aは、熱硬化性のエポキシ樹脂とシリカの混合物とし、シリカの添加量を80Wt%としたコンポジットシート107a,107bからできている。まず、1枚のコンポジットシート107aには、部品の入るスペース108を抜き型で形成する。その後もう一枚のコンポジットシート107bをコンポジットシート107aに重ね合わせ、ビア10用の孔をパンチングマシンで加工し、その孔に導電性ペーストが充填されている。   The insulating layer 3a is made of a composite sheet 107a, 107b made of a mixture of a thermosetting epoxy resin and silica, and an added amount of silica of 80 Wt%. First, in one composite sheet 107a, a space 108 into which a part enters is formed with a punching die. Thereafter, another composite sheet 107b is overlaid on the composite sheet 107a, and a hole for the via 10 is processed by a punching machine, and the hole is filled with a conductive paste.

図7(e)では、熱プレスにて一体化を行い部品を内蔵した。部品内蔵工程のプレス条件は、温度200℃、圧力3MPa、時間2時間、真空雰囲気で行った。
図7(f)では、部品実装基板1のパターン電極103aと第1の支持基板2aのパターン電極103cを残して部品実装基板1と第1の支持基板2aを剥離してパターン電極103a,103cを露出させて部品内蔵基板ができる。
In FIG.7 (e), it integrated by the hot press and incorporated components. The press conditions for the component built-in process were a temperature of 200 ° C., a pressure of 3 MPa, a time of 2 hours, and a vacuum atmosphere.
In FIG. 7F, the component mounting board 1 and the first support board 2a are separated to leave the pattern electrodes 103a and 103c, leaving the pattern electrode 103a of the component mounting board 1 and the pattern electrode 103c of the first support board 2a. A substrate with built-in components can be formed by exposing.

上下に配置されているプリプレグ101a,101bを剥離したままの図8(g)に示す状態では、部品実装基板1の樹脂成分109と第1,第2の支持基板2a,2bの樹脂成分109が表面に付着していたので、樹脂成分109を研磨加工で取り除いて図8(h)に示すようにパターン電極103a,103cを露出させて部品内蔵基板が完成する。   In the state shown in FIG. 8G with the prepregs 101a and 101b disposed above and below being peeled, the resin component 109 of the component mounting board 1 and the resin components 109 of the first and second support boards 2a and 2b are the same. Since it was adhered to the surface, the resin component 109 was removed by polishing to expose the pattern electrodes 103a and 103c as shown in FIG.

さらに、必要に応じて図8(i)に示すように、上面と下面のパターン電極103c,103aに部品としての抵抗104c,104dや半導体105c,105dの表面実装を実施する。   Further, as shown in FIG. 8I, surface mounting of resistors 104c and 104d as components and semiconductors 105c and 105d is performed on the pattern electrodes 103c and 103a on the upper and lower surfaces as necessary.

また、必要に応じて図8(j)に示すように、上面のパターン電極103cに部品としての抵抗104cや半導体105cの表面実装を実施し、下面のパターン電極103aには2次実装用に半田ボール100を実装してもよい。   Further, as shown in FIG. 8 (j), the upper surface pattern electrode 103c is surface-mounted with a resistor 104c and a semiconductor 105c as necessary, and the lower surface pattern electrode 103a is soldered for secondary mounting. The ball 100 may be mounted.

このように、部品実装基板1のプリプレグ101aと第1の支持基板2aのプリプレグ101bとが同じ材質であって、部品実装基板1と第1の支持基板2aの熱膨張係数が同じであるため、図7(d)の工程において、硬化前の絶縁層3aを挟んで熱プレスして絶縁層3aを硬化させて一体化する際の部品実装基板1と第1の支持基板2aの伸び量は略同じであるため、ビア10が従来のように傾くことが無く、信頼性の高い層間接続を期待できる。   Thus, since the prepreg 101a of the component mounting board 1 and the prepreg 101b of the first support board 2a are the same material, and the thermal expansion coefficients of the component mounting board 1 and the first support board 2a are the same, In the step of FIG. 7D, the amount of elongation of the component mounting substrate 1 and the first support substrate 2a when the insulating layer 3a is cured by pressing with the insulating layer 3a before being cured is integrated. Since they are the same, the via 10 is not inclined as in the prior art, and a highly reliable interlayer connection can be expected.

なお、部品実装基板1のプリプレグ101aと第1の支持基板2aのプリプレグ101b,101cとは同じ材質であったが、熱膨張係数がほぼ同じある場合には材質が異なっていてもよい。   Although the prepreg 101a of the component mounting board 1 and the prepregs 101b and 101c of the first support board 2a are made of the same material, the materials may be different when the thermal expansion coefficients are almost the same.

図7(d)において、ビア10用の孔加工にはパンチングマシンを使用したが、レーザ加工機など他の加工方法でも構わない。
図7(d)において、コンポジットシート107aのスペース108は抜き型を使用したが、他の方法でも構わない。
In FIG. 7D, the punching machine is used for the hole processing for the via 10, but other processing methods such as a laser processing machine may be used.
In FIG. 7D, the blank 108 is used for the composite sheet 107a, but other methods may be used.

図7(d)において、第1の支持基板2aの片側の銅箔をすべて除去したが、除去する必要はない。
また、部品実装基板1のパターン電極103a、第1の支持基板2aのパターン電極103cの表面は、金などの金属をメッキしても構わない。
In FIG. 7D, all of the copper foil on one side of the first support substrate 2a is removed, but it is not necessary to remove it.
Further, the surface of the pattern electrode 103a of the component mounting substrate 1 and the pattern electrode 103c of the first support substrate 2a may be plated with a metal such as gold.

部品実装基板1と第1の支持基板2aのプリプレグ101bは熱膨張係数が同じであったが、第1の支持基板2aとして、部品実装基板1の熱膨張係数にほぼ近い材質のものを使用しても同様である。   The component mounting board 1 and the prepreg 101b of the first support board 2a have the same thermal expansion coefficient, but the first support board 2a is made of a material that is almost similar to the thermal expansion coefficient of the component mounting board 1. But the same is true.

(実施の形態3)
図9〜図12は本発明の実施の形態3を示す。
図5に示した実施の形態2では絶縁層3aに埋設された部品としての抵抗104a,半導体105aがパターン電極103aに実装されており、パターン電極103bには部品が実装されていなかったが、図9に示す実施の形態3では、パターン電極103bにも部品としての抵抗104b,半導体105bが実装されている点だけが異なっている。
(Embodiment 3)
9 to 12 show a third embodiment of the present invention.
In the second embodiment shown in FIG. 5, the resistor 104a and the semiconductor 105a as components embedded in the insulating layer 3a are mounted on the pattern electrode 103a, and no component is mounted on the pattern electrode 103b. The third embodiment shown in FIG. 9 is different only in that a resistor 104b and a semiconductor 105b as components are also mounted on the pattern electrode 103b.

この部品内蔵基板は、図10(a)〜(c),図11(d)〜(f),図12(g)(h)の工程で製造される。
まず、図10(a)〜(c)では、図6(a)〜(c)と同じにしてパターン電極103a上に部品としての抵抗104a,半導体105aを実装した第1の部品実装基板11と、パターン電極103b上に部品としての抵抗104b,半導体105bを実装した第2の部品実装基板12を作成する。
This component-embedded substrate is manufactured by the steps of FIGS. 10A to 10C, FIGS. 11D to 11F, and FIGS. 12G and 12H.
First, in FIGS. 10A to 10C, a first component mounting board 11 in which a resistor 104a and a semiconductor 105a as components are mounted on a pattern electrode 103a in the same manner as FIGS. 6A to 6C. Then, the second component mounting board 12 is prepared by mounting the resistor 104b and the semiconductor 105b as components on the pattern electrode 103b.

図11(d)の部品内蔵工程では、図10(c)で作成した第1,第2の部品実装基板11,12の部品実装面が対向するように積層配置するとともに、その間に硬化前状態の絶縁層30を配設する。絶縁層30には、層間接続用のビア10と第1,第2の部品実装基板11,12に実装された抵抗104a,104bと半導体105a,105bの位置に対応してスペース108が形成されている。   In the component built-in process in FIG. 11D, the first and second component mounting boards 11 and 12 created in FIG. 10C are stacked and disposed so that the component mounting surfaces face each other, and the state before curing is performed therebetween. An insulating layer 30 is provided. A space 108 is formed in the insulating layer 30 corresponding to the positions of the vias 10 for interlayer connection, the resistors 104a and 104b mounted on the first and second component mounting boards 11 and 12, and the semiconductors 105a and 105b. Yes.

第1,第2の部品実装基板11,12のプリプレグは互いに同じ材質で、ここでは日立化成工業株式会製GEA−67BE(ガラスクロス厚80μm)を用い、9μmの銅箔を温度180℃、圧力10MPaで一体化した。本実施の形態では、熱伝導性が良好なGEA−67BEを使用したが、安価で一般的なガラスエポキシ基板を使用しても構わない。絶縁層30は、熱硬化性のエポキシ樹脂とシリカの混合物である。   The prepregs of the first and second component mounting boards 11 and 12 are made of the same material. Here, GEA-67BE (glass cloth thickness 80 μm) manufactured by Hitachi Chemical Co., Ltd. is used, and 9 μm copper foil is heated to 180 ° C. and pressure Integrated at 10 MPa. In this embodiment, GEA-67BE having good thermal conductivity is used. However, an inexpensive and general glass epoxy substrate may be used. The insulating layer 30 is a mixture of a thermosetting epoxy resin and silica.

図11(e)では、熱プレスにて一体化を行い部品を内蔵した。部品内蔵工程のプレス条件は、温度200℃、圧力3MPa、時間2時間、真空雰囲気で行った。
図11(f)では、第1の部品実装基板11のパターン電極103aと第2の部品実装基板12のパターン電極103bを残して第1,第2の部品実装基板11,12を剥離してパターン電極103a,103bを露出させて部品内蔵基板ができる。
In FIG.11 (e), it integrated by the hot press and incorporated components. The press conditions for the component built-in process were a temperature of 200 ° C., a pressure of 3 MPa, a time of 2 hours, and a vacuum atmosphere.
In FIG. 11 (f), the first and second component mounting boards 11 and 12 are peeled off while leaving the pattern electrode 103 a of the first component mounting board 11 and the pattern electrode 103 b of the second component mounting board 12. By exposing the electrodes 103a and 103b, a component-embedded substrate can be formed.

上下に配置されている第1,第2の部品実装基板11,12を剥離したままの図12(g)に示す状態では、第1,第2の部品実装基板11,12のプリプレグ101a,101bの樹脂成分109が表面に付着していたので、樹脂成分109を研磨加工で取り除いて図12(h)に示すようにパターン電極103a,103bを露出させて部品内蔵基板が完成する。   In the state shown in FIG. 12G with the first and second component mounting boards 11 and 12 disposed above and below being peeled off, the prepregs 101a and 101b of the first and second component mounting boards 11 and 12 are provided. Since the resin component 109 was adhered to the surface, the resin component 109 was removed by polishing to expose the pattern electrodes 103a and 103b as shown in FIG.

さらに、必要に応じて図12(i)に示すように、上面と下面のパターン電極103b,103aに部品としての抵抗104c,104dや半導体105c,105dの表面実装を実施する。   Further, as shown in FIG. 12 (i), surface mounting of resistors 104c and 104d as components and semiconductors 105c and 105d is performed on the pattern electrodes 103b and 103a on the upper surface and the lower surface as necessary.

また、必要に応じて図12(j)に示すように、上面のパターン電極103cに部品としての抵抗104cや半導体105cの表面実装を実施し、下面のパターン電極103aには2次実装用に半田ボール100を実装してもよい。   Further, as shown in FIG. 12 (j), the upper surface pattern electrode 103c is surface-mounted with a resistor 104c and a semiconductor 105c as components, and the lower surface pattern electrode 103a is soldered for secondary mounting. The ball 100 may be mounted.

(実施の形態4)
図13と図14は本発明の実施の形態4を示す。
実施の形態2または実施の形態3で作成された部品内蔵基板を用い、内蔵層を多段構成としたものである。ここでは実施の形態2で作成された部品内蔵基板を内装基板4として使用した場合を例に挙げて説明する。
(Embodiment 4)
13 and 14 show a fourth embodiment of the present invention.
The component built-in board created in the second embodiment or the third embodiment is used, and the built-in layer has a multi-stage configuration. Here, a case where the component built-in board created in the second embodiment is used as the interior board 4 will be described as an example.

図13は部品内蔵基板の仕上がり形状を示す。
内装基板4の上下面に絶縁層31,32が一体化されている。
絶縁層31には、内装基板4のパターン電極103cと絶縁層31の上面に付けられたパターン電極103eとを接続する層間接続用のビア10が形成されている。絶縁層32には、内装基板4のパターン電極103aと絶縁層32の下面に付けられたパターン電極103fとを接続する層間接続用のビア10が形成されている。また、絶縁層31には、パターン電極103eに実装されている部品としての抵抗104e,半導体105eが埋設されている。絶縁層32には、パターン電極103fに実装されている部品としての抵抗104f,半導体105fが埋設されている。
FIG. 13 shows the finished shape of the component-embedded substrate.
Insulating layers 31 and 32 are integrated on the upper and lower surfaces of the interior substrate 4.
The insulating layer 31 is formed with vias 10 for interlayer connection that connect the pattern electrode 103 c of the interior substrate 4 and the pattern electrode 103 e attached to the upper surface of the insulating layer 31. The insulating layer 32 is formed with an interlayer connection via 10 that connects the pattern electrode 103 a of the interior substrate 4 and the pattern electrode 103 f attached to the lower surface of the insulating layer 32. Further, in the insulating layer 31, a resistor 104e and a semiconductor 105e are embedded as components mounted on the pattern electrode 103e. In the insulating layer 32, a resistor 104f and a semiconductor 105f as components mounted on the pattern electrode 103f are embedded.

この部品内蔵基板は、図14(a)〜(c)の工程で製造される。
図14(a)では、パターン電極103eに抵抗104eと半導体105eが実装された第3の部品実装基板21と、パターン電極103fに抵抗104fと半導体105fが実装された第4の部品実装基板22とを、内装基板4を中央にして、互いの実装面を内側にして積層配置するとともに、第3の部品実装基板21と内装基板4の間に硬化前の絶縁層31が配置され、第4の部品実装基板22と内装基板4の間に硬化前の絶縁層32が配置されている。
This component-embedded substrate is manufactured by the steps shown in FIGS.
In FIG. 14A, the third component mounting board 21 in which the resistor 104e and the semiconductor 105e are mounted on the pattern electrode 103e, and the fourth component mounting board 22 in which the resistor 104f and the semiconductor 105f are mounted on the pattern electrode 103f. Are stacked with the interior substrate 4 as the center and the mounting surfaces inside, and an insulating layer 31 before curing is disposed between the third component mounting substrate 21 and the interior substrate 4, An insulating layer 32 before curing is disposed between the component mounting board 22 and the interior board 4.

絶縁層31には、ビア10と抵抗104eと半導体105eに対応して形成されたスペース108が設けられている。絶縁層32には、抵抗104fと半導体105fに対応して形成されたスペース108が設けられている。   The insulating layer 31 is provided with a space 108 corresponding to the via 10, the resistor 104e, and the semiconductor 105e. The insulating layer 32 is provided with a space 108 formed corresponding to the resistor 104f and the semiconductor 105f.

図14(b)では、第3,第4の部品実装基板21,22を積層方向に加熱加圧して絶縁層31,32を硬化させて一体化する。
その後、第3,第4の部品実装基板21,22のパターン電極103e,103fを残して第3,第4の部品実装基板21,22を剥離してパターン電極103e,103fを露出させる。
In FIG. 14B, the third and fourth component mounting boards 21 and 22 are heated and pressed in the stacking direction to cure and integrate the insulating layers 31 and 32.
Thereafter, the pattern electrodes 103e and 103f are exposed by peeling off the third and fourth component mounting boards 21 and 22, leaving the pattern electrodes 103e and 103f of the third and fourth component mounting boards 21 and 22.

上下に配置されている第3,第4の部品実装基板21,22を剥離したままの状態では、第3,第4の部品実装基板21,22のプリプレグの樹脂成分が表面に付着しているので、この樹脂成分を研磨加工で取り除いて図14(c)に示すようにパターン電極103e,103fを露出させて部品内蔵基板が完成する。   In the state where the third and fourth component mounting boards 21 and 22 arranged above and below are peeled off, the resin components of the prepregs of the third and fourth component mounting boards 21 and 22 are attached to the surface. Therefore, the resin component is removed by polishing to expose the pattern electrodes 103e and 103f as shown in FIG. 14C, thereby completing the component-embedded substrate.

さらに、必要に応じて図14(d)に示すように、上面と下面のパターン電極103e,103fに部品としての抵抗104g,104hや半導体105g,105hの表面実装を実施する。   Further, as shown in FIG. 14D, surface mounting of resistors 104g and 104h as components and semiconductors 105g and 105h is performed on the pattern electrodes 103e and 103f on the upper and lower surfaces as required.

また、必要に応じて上面のパターン電極103eに部品としての抵抗104gや半導体105gの表面実装を実施し、下面のパターン電極103fには2次実装用に半田ボールを実装してもよい。   Further, if necessary, surface mounting of a resistor 104g or a semiconductor 105g as a component may be performed on the upper pattern electrode 103e, and a solder ball may be mounted on the lower pattern electrode 103f for secondary mounting.

熱膨張係数が内装基板4と第3,第4の部品実装基板21,22は同じであったが、熱膨張係数が内装基板4とほぼ近い第3,第4の部品実装基板21,22を使用しても同様である。   Although the internal expansion board 4 and the third and fourth component mounting boards 21 and 22 have the same thermal expansion coefficient, the third and fourth component mounting boards 21 and 22 that have a thermal expansion coefficient substantially similar to the internal expansion board 4 are The same applies when used.

(実施の形態5)
図15と図16は本発明の実施の形態5を示す。
実施の形態4で作成された部品内蔵基板は、中心の層が部品が実装された内装基板4であったが、この実施の形態5では部品内蔵基板では中心の層が部品が実装されていない多層回路基板7である点だけが異なっている。
(Embodiment 5)
15 and 16 show a fifth embodiment of the present invention.
The component built-in board created in the fourth embodiment is the interior board 4 on which the component is mounted on the central layer. However, in the fifth embodiment, the component is not mounted on the central layer in the component built-in substrate. Only the multi-layer circuit board 7 is different.

図15は部品内蔵基板の仕上がり形状を示す。
多層回路基板7には、層間接続用のビア10とパターン電極103g,103hが形成されている。この多層回路基板7を中央にして、多層回路基板7の上面には絶縁層31を介してパターン電極103eが設けられている。パターン電極103eには部品としての抵抗104e,半導体105eが実装されており、この抵抗104e,半導体105eは絶縁層31に埋設されている。多層回路基板7の下面には絶縁層32を介してパターン電極103fが設けられている。パターン電極103fには部品としての抵抗104f,半導体105fが実装されており、この抵抗104f,半導体105fは絶縁層32に埋設されている。
FIG. 15 shows the finished shape of the component-embedded substrate.
In the multilayer circuit board 7, vias 10 for interlayer connection and pattern electrodes 103g and 103h are formed. A pattern electrode 103e is provided on the upper surface of the multilayer circuit board 7 through an insulating layer 31 with the multilayer circuit board 7 as the center. A resistor 104e and a semiconductor 105e as components are mounted on the pattern electrode 103e. The resistor 104e and the semiconductor 105e are embedded in the insulating layer 31. A pattern electrode 103 f is provided on the lower surface of the multilayer circuit board 7 via an insulating layer 32. A resistor 104f and a semiconductor 105f as components are mounted on the pattern electrode 103f, and the resistor 104f and the semiconductor 105f are embedded in the insulating layer 32.

この部品内蔵基板は、図16(a)〜(c)の工程で製造される。
図16(a)では、パターン電極103eに抵抗104eと半導体105eが実装された第3の部品実装基板21と、パターン電極103fに抵抗104fと半導体105fが実装された第4の部品実装基板22とを、多層回路基板7を中央にして、互いの実装面を内側にして積層配置するとともに、第3の部品実装基板21と多層回路基板7の間に硬化前の絶縁層31が配置され、第4の部品実装基板22と多層回路基板7の間に硬化前の絶縁層32が配置されている。
This component-embedded substrate is manufactured by the steps shown in FIGS.
In FIG. 16A, the third component mounting board 21 in which the resistor 104e and the semiconductor 105e are mounted on the pattern electrode 103e, and the fourth component mounting board 22 in which the resistor 104f and the semiconductor 105f are mounted on the pattern electrode 103f. Are laminated with the multilayer circuit board 7 in the center and the mounting surfaces inside, and an insulating layer 31 before curing is disposed between the third component mounting board 21 and the multilayer circuit board 7, An insulating layer 32 before curing is disposed between the component mounting board 22 and the multilayer circuit board 7.

ここでは、多層回路基板7と第3,第4の部品実装基板21,22のプリプレグは互いに同じ材質で、ここでは日立化成工業株式会製GEA−67BE(ガラスクロス厚80μm)を用い、9μmの銅箔を温度180℃、圧力10MPaで一体化した。本実施の形態では、熱伝導性が良好なGEA−67BEを使用したが、安価で一般的なガラスエポキシ基板を使用しても構わない。絶縁層31,32は、熱硬化性のエポキシ樹脂とシリカの混合物である。   Here, the prepregs of the multilayer circuit board 7 and the third and fourth component mounting boards 21 and 22 are made of the same material. Here, GEA-67BE (glass cloth thickness 80 μm) manufactured by Hitachi Chemical Co., Ltd. is used, and the prepreg is 9 μm. The copper foil was integrated at a temperature of 180 ° C. and a pressure of 10 MPa. In this embodiment, GEA-67BE having good thermal conductivity is used. However, an inexpensive and general glass epoxy substrate may be used. The insulating layers 31 and 32 are a mixture of a thermosetting epoxy resin and silica.

絶縁層31には、多層回路基板7のパターン電極103gと第3の部品実装基板21のパターン電極103eとの層間接続用のビア10と、抵抗104eと半導体105eに対応して形成されたスペース108が設けられている。絶縁層32には、多層回路基板7のパターン電極103hと第4の部品実装基板22のパターン電極103fとの層間接続用のビア10と、抵抗104fと半導体105fに対応して形成されたスペース108が設けられている。   In the insulating layer 31, a space 108 formed corresponding to the interlayer connection via 10 between the pattern electrode 103g of the multilayer circuit board 7 and the pattern electrode 103e of the third component mounting board 21, the resistor 104e, and the semiconductor 105e. Is provided. In the insulating layer 32, a space 108 formed corresponding to the interlayer connection via 10 between the pattern electrode 103h of the multilayer circuit board 7 and the pattern electrode 103f of the fourth component mounting board 22, the resistor 104f, and the semiconductor 105f. Is provided.

図16(b)では、第3,第4の部品実装基板21,22を積層方向に加熱加圧して絶縁層31,32を硬化させて一体化する。
その後、第3,第4の部品実装基板21,22のパターン電極103e,103fを残して第3,第4の部品実装基板21,22を剥離してパターン電極103e,103fを露出させる。パターン電極103e,103fが光沢箔で有るため簡単に剥離できる。
In FIG. 16B, the third and fourth component mounting boards 21 and 22 are heated and pressed in the stacking direction to cure and integrate the insulating layers 31 and 32.
Thereafter, the pattern electrodes 103e and 103f are exposed by peeling off the third and fourth component mounting boards 21 and 22, leaving the pattern electrodes 103e and 103f of the third and fourth component mounting boards 21 and 22. Since the pattern electrodes 103e and 103f are glossy foils, they can be easily peeled off.

上下に配置されている第3,第4の部品実装基板21,22を剥離したままの状態では、第3,第4の部品実装基板21,22のプリプレグの樹脂成分が表面に付着しているので、この樹脂成分を研磨加工で取り除いて図16(c)に示すようにパターン電極103e,103fを露出させて部品内蔵基板が完成する。   In the state where the third and fourth component mounting boards 21 and 22 arranged above and below are peeled off, the resin components of the prepregs of the third and fourth component mounting boards 21 and 22 are attached to the surface. Therefore, the resin component is removed by polishing to expose the pattern electrodes 103e and 103f as shown in FIG. 16C, thereby completing the component-embedded substrate.

さらに、必要に応じて図16(d)に示すように、上面と下面のパターン電極103e,103fに部品としての抵抗104g,104hや半導体105g,105hの表面実装を実施する。   Further, as shown in FIG. 16D, surface mounting of resistors 104g and 104h as components and semiconductors 105g and 105h is performed on the upper and lower pattern electrodes 103e and 103f as required.

また、必要に応じて上面のパターン電極103eに部品としての抵抗104gや半導体105gの表面実装を実施し、下面のパターン電極103fには2次実装用に半田ボールを実装してもよい。   Further, if necessary, surface mounting of a resistor 104g or a semiconductor 105g as a component may be performed on the upper pattern electrode 103e, and a solder ball may be mounted on the lower pattern electrode 103f for secondary mounting.

ここで抵抗104g,104hや半導体105g,105hとしては、チップサイズが1005以上の物で、0603以下のサイズの物には空隙の発生は無かった。チップサイズの部品実装は、一般の半田を用いて実装を行った。環境に配慮して鉛フリー半田を使用した。   Here, as the resistors 104g and 104h and the semiconductors 105g and 105h, those having a chip size of 1005 or more and those having a size of 0603 or less had no voids. Chip size component mounting was performed using general solder. In consideration of the environment, lead-free solder was used.

多層回路基板7と第3,第4の部品実装基板21,22は熱膨張係数が同じであったが、第3,第4の部品実装基板21,22として多層回路基板7の熱膨張係数にほぼ近い材質のものを使用しても同様である。   The multilayer circuit board 7 and the third and fourth component mounting boards 21 and 22 have the same thermal expansion coefficient. However, the third and fourth component mounting boards 21 and 22 have the same thermal expansion coefficient as the multilayer circuit board 7. The same applies to the use of materials that are close to each other.

実施の形態2〜実施の形態4では、すべての絶縁材料がコンポジットシートであるため、温度変化などによる基板反りの発生が無いため、高信頼性の部品内蔵基板を提供できる。また、実施の形態1および実施の形態5においても絶縁材料が対称系に積層されているため、基板の反りなどは抑えられる。   In Embodiments 2 to 4, since all insulating materials are composite sheets, there is no occurrence of substrate warpage due to temperature change or the like, so that a highly reliable component-embedded substrate can be provided. Further, in the first and fifth embodiments, since the insulating material is laminated in a symmetrical system, warping of the substrate and the like can be suppressed.

上記の各実施の形態において、内蔵部品実装用の半田と表面実装の半田とは同じ物を用いても構わないが、リフロー温度に注意が必要である。表面実装時に内蔵部品用の半田を溶かしてしまうと、半田が流れ出し、回路のショートなど不良が発生する可能性があるが内蔵用の半田の融点を高くすることで上記課題は解決される。   In each of the above embodiments, the same solder may be used as the built-in component mounting solder and the surface mounting solder, but attention should be paid to the reflow temperature. If the solder for the built-in component is melted during surface mounting, the solder may flow out and a defect such as a short circuit may occur, but the above problem can be solved by increasing the melting point of the built-in solder.

上記の各実施の形態において、部品としての半導体はベアチップを用いフリップチップ実装したが、その実装方式にはとらわれない。内蔵する半導体には部品下の空隙対策としてアンダーフィルを設ける方がよい。ワイヤボンディング方式で実装する場合は、モールドする方が良い。   In each of the above embodiments, the semiconductor as a component is flip-chip mounted using a bare chip, but the mounting method is not limited. It is better to provide an underfill for the built-in semiconductor as a measure against the gap under the component. When mounting by wire bonding method, it is better to mold.

上記の各実施の形態において、前記無機フィラーが、Al、MgO、BN、AlN及びSiOから選ばれた少なくとも1つを含んでいる。
上記の各実施の形態において、内蔵される部品は抵抗または半導体であったが、チップ状のコンデンサ、インダクタなどでもよい。
In each of the embodiments described above, the inorganic filler contains at least one selected from Al 2 O 3 , MgO, BN, AlN, and SiO 2 .
In each of the above embodiments, the built-in component is a resistor or a semiconductor. However, a chip-shaped capacitor, an inductor, or the like may be used.

本発明の部品内蔵基板は、電子機器の小型、高機能、高密度化の要求に容易に対応可能であり、かつ低背化が可能で有るため、携帯機器用の基板の用途にも適用できる。   The component-embedded substrate according to the present invention can easily meet the demands for small size, high functionality, and high density of electronic devices, and can be reduced in height, and thus can be applied to the use of a substrate for portable devices. .

本発明の実施の形態1における部品内蔵基板の断面図Sectional drawing of the component built-in board | substrate in Embodiment 1 of this invention 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 本発明の実施の形態2における部品内蔵基板の断面図Sectional drawing of the component built-in board | substrate in Embodiment 2 of this invention 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 本発明の実施の形態3における部品内蔵基板の断面図Sectional drawing of the component built-in board | substrate in Embodiment 3 of this invention 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 本発明の実施の形態4における部品内蔵基板の断面図Sectional drawing of the component built-in board | substrate in Embodiment 4 of this invention 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 本発明の実施の形態5における部品内蔵基板の断面図Sectional drawing of the component built-in board | substrate in Embodiment 5 of this invention 同実施の形態の製造工程の断面図Sectional drawing of the manufacturing process of the embodiment 特許文献1の部品内蔵基板の工程の断面図Sectional drawing of process of component built-in substrate of Patent Document 1 特許文献2の部品内蔵基板の工程の断面図Sectional drawing of process of component built-in substrate of Patent Document 2

符号の説明Explanation of symbols

1 部品実装基板
2a,2b 第1,第2の支持基板
3a,3b,30,31,32 絶縁層
4 内装基板
7 多層回路基板
10 層間接続用のビア
11,12 第1,第2の部品実装基板
21,22 第3,第4の部品実装基板
100 半田ボール
101a,101b,101c プリプレグ
102a,102b 銅箔
103a,103b,103c,103d,103e,103f パターン電極
103g,103h パターン電極
104a,104b,104c,104d 抵抗(部品)
104e,104f,104g,104h 抵抗(部品)
105a,105b,105c,105d 半導体(部品)
105e,105f,105g,105h 半導体(部品)
107a,107b コンポジットシート
108 スペース
109 樹脂成分
DESCRIPTION OF SYMBOLS 1 Component mounting board 2a, 2b 1st, 2nd support board 3a, 3b, 30, 31, 32 Insulating layer 4 Interior board 7 Multilayer circuit board 10 Via for interlayer connection 11, 12 1st, 2nd component mounting Substrates 21, 22 Third and fourth component mounting boards 100 Solder balls 101a, 101b, 101c Prepregs 102a, 102b Copper foils 103a, 103b, 103c, 103d, 103e, 103f Pattern electrodes 103g, 103h Pattern electrodes 104a, 104b, 104c 104d Resistance (components)
104e, 104f, 104g, 104h Resistance (components)
105a, 105b, 105c, 105d Semiconductor (component)
105e, 105f, 105g, 105h Semiconductor (component)
107a, 107b Composite sheet 108 Space 109 Resin component

Claims (8)

両面に部品を実装した部品実装基板を中央にして、前記部品実装基板との対向面にパターン電極有し熱膨張係数が前記部品実装基板と同じかほぼ近い第1,第2の支持基板を積層配置するとともに、前記部品実装基板と第1,第2の支持基板との間には、層間接続用のビアと部品実装基板に実装された前記部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、
第1,第2の支持基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、
前記一体化の後に、前記パターン電極を残して第1,第2の支持基板を剥離して前記パターン電極を露出させる
部品内蔵基板の製造方法。
A component mounting board having components mounted on both sides is centered, and first and second supporting boards having a pattern electrode on the surface facing the component mounting board and having the same or almost the same thermal expansion coefficient as the component mounting board are stacked. In addition to the arrangement, a space is formed between the component mounting board and the first and second support boards corresponding to the positions of the vias for interlayer connection and the parts mounted on the component mounting board. Arrange the previous insulation layer,
The first and second support substrates are heated and pressed in the stacking direction to cure and integrate the insulating layer,
A method of manufacturing a component-embedded substrate in which, after the integration, the first and second support substrates are peeled off leaving the pattern electrode to expose the pattern electrode.
前記部品実装基板のプリプレグシートを、熱硬化性樹脂と無機フィラーとを含む混合物で構成する
請求項1記載の部品内蔵基板の製造方法。
The manufacturing method of the component built-in board | substrate of Claim 1 which comprises the prepreg sheet | seat of the said component mounting board | substrate with the mixture containing a thermosetting resin and an inorganic filler.
前記部品実装基板を、セラミック多層基板で構成する
請求項1記載の部品内蔵基板の製造方法。
The method for manufacturing a component built-in substrate according to claim 1, wherein the component mounting substrate is formed of a ceramic multilayer substrate.
部品が実装された部品実装基板の実装面に、前記部品実装基板との対向面にパターン電極を有し熱膨張係数が前記部品実装基板と同じかほぼ近い第1の支持基板を積層配置するとともに、前記部品実装基板と第1の支持基板との間には、層間接続用のビアと部品実装基板に実装された前記部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、
第1の支持基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、
前記一体化の後に、前記部品実装基板の実装面のパターン電極と第1の支持基板の前記パターン電極を残して前記部品実装基板と第1の支持基板を剥離してパターン電極を露出させる
部品内蔵基板の製造方法。
A first support substrate having a pattern electrode on the mounting surface of the component mounting substrate on which the component is mounted and having a pattern electrode on the surface facing the component mounting substrate and having a thermal expansion coefficient that is the same as or close to that of the component mounting substrate is stacked and disposed. In addition, an insulating layer in an uncured state in which a space corresponding to the position of the component mounted on the component mounting board is formed between the component mounting board and the first support board. Arranged,
The first support substrate is heated and pressed in the laminating direction to cure and integrate the insulating layer,
Built-in component that, after the integration, leaves the pattern electrode on the mounting surface of the component mounting substrate and the pattern electrode of the first support substrate, and peels off the component mounting substrate and the first support substrate to expose the pattern electrode. A method for manufacturing a substrate.
互いの熱膨張係数が同じかほぼ近い第1,第2の部品実装基板を部品が実装されたそれぞれの実装面が対向するように積層配置するとともに、第1,第2の部品実装基板との間には、層間接続用のビアと第1,第2の部品実装基板に実装された前記部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、
第1,第2の部品実装基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、
前記一体化の後に、第1,第2の部品実装基板の実装面のパターン電極を残して第1,第2の部品実装基板を剥離してパターン電極を露出させる
部品内蔵基板の製造方法。
The first and second component mounting boards having the same or nearly the same coefficient of thermal expansion as each other are stacked so that the mounting surfaces on which the components are mounted face each other, and the first and second component mounting boards Between the vias for interlayer connection and an insulating layer in a pre-curing state in which spaces are formed corresponding to the positions of the components mounted on the first and second component mounting boards,
The first and second component mounting boards are heated and pressed in the stacking direction to cure and integrate the insulating layer,
A method of manufacturing a component-embedded substrate in which, after the integration, the first and second component mounting boards are peeled off while leaving the pattern electrodes on the mounting surfaces of the first and second component mounting boards.
請求項4または請求項5に記載の部品内蔵基板を内装基板とし、この内装基板を中央にして、前記内装基板との対向面にパターン電極を有し熱膨張係数が前記内装基板と同じかほぼ近い第3,第4の部品実装基板を積層配置するとともに、前記内装基板と第3,第4の部品実装基板との間には、層間接続用のビアと第3,第4の部品実装基板に実装された部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、
第3,第4の部品実装基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、
前記一体化の後に、第3,第4の部品実装基板の実装面のパターン電極を残して第3,第4の部品実装基板を剥離して前記パターン電極を露出させる
部品内蔵基板の製造方法。
The component-embedded substrate according to claim 4 or 5 is used as an interior substrate, the interior substrate is in the center, a pattern electrode is provided on a surface facing the interior substrate, and a thermal expansion coefficient is substantially the same as or substantially equal to that of the interior substrate. Near third and fourth component mounting boards are stacked and disposed between the interior board and the third and fourth component mounting boards, vias for interlayer connection and third and fourth component mounting boards. An insulating layer in a pre-curing state in which a space is formed corresponding to the position of the component mounted on is disposed,
The third and fourth component mounting boards are heated and pressed in the stacking direction to cure and integrate the insulating layer,
A method of manufacturing a component-embedded board in which, after the integration, the third and fourth component mounting boards are peeled off to leave the pattern electrodes on the mounting surfaces of the third and fourth component mounting boards, and the pattern electrodes are exposed.
層間接続用のビアとパターン電極を有する多層回路基板を中央にして、前記多層回路基板との対向面にパターン電極を有し熱膨張係数が前記多層回路基板と同じかほぼ近い第3,第4の部品実装基板を積層配置するとともに、前記多層回路基板と第3,第4の部品実装基板との間には、層間接続用のビアと第3,第4の部品実装基板に実装された部品の位置に対応してスペースが形成された硬化前状態の絶縁層を配設し、
第3,第4の部品実装基板を積層方向に加熱加圧して前記絶縁層を硬化させて一体化し、
前記一体化の後に、第3,第4の部品実装基板の実装面のパターン電極を残して第3,第4の部品実装基板を剥離して前記パターン電極を露出させる
部品内蔵基板の製造方法。
A multilayer circuit board having vias for interlayer connection and a pattern electrode is provided at the center, and the third and fourth fourth and fourth patterns have a pattern electrode on the surface facing the multilayer circuit board and have a thermal expansion coefficient that is the same as or substantially the same as that of the multilayer circuit board. And a component mounted on the third and fourth component mounting boards between the multilayer circuit board and the third and fourth component mounting boards. An insulating layer in a pre-curing state in which a space is formed corresponding to the position of
The third and fourth component mounting boards are heated and pressed in the stacking direction to cure and integrate the insulating layer,
A method of manufacturing a component-embedded board in which, after the integration, the third and fourth component mounting boards are peeled off to leave the pattern electrodes on the mounting surfaces of the third and fourth component mounting boards, and the pattern electrodes are exposed.
多層回路基板を、セラミック多層基板で構成する
請求項7記載の部品内蔵基板の製造方法。
8. The method of manufacturing a component built-in board according to claim 7, wherein the multilayer circuit board is formed of a ceramic multilayer board.
JP2007165725A 2007-06-25 2007-06-25 Manufacturing method for board with built-in components Pending JP2009004664A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012094682A (en) * 2010-10-27 2012-05-17 Ngk Spark Plug Co Ltd Method for manufacturing multilayer wiring board
CN104470267A (en) * 2014-12-10 2015-03-25 深圳崇达多层线路板有限公司 Method for improving alignment precision between HDI board layers made of mixed pressure materials

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012094682A (en) * 2010-10-27 2012-05-17 Ngk Spark Plug Co Ltd Method for manufacturing multilayer wiring board
US8826526B2 (en) 2010-10-27 2014-09-09 Ngk Spark Plug Co., Ltd. Method of manufacturing multilayer wiring substrate
CN104470267A (en) * 2014-12-10 2015-03-25 深圳崇达多层线路板有限公司 Method for improving alignment precision between HDI board layers made of mixed pressure materials

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