JP2009003764A - Semiconductor integrated circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which hardly malfunctions even in a steep variation in a power-supply voltage and has low power consumption. <P>SOLUTION: The integrated circuit device 1 is operated with a difference between a VDD (first potential) supplied by a VDD supply line 60 (first potential supply line) and a VSS (second potential) supplied by a VSS supply line 70 (second potential supply line), as the power-supply voltage. The integrated circuit device 1 includes a constant voltage generation circuit 10 for generating a fixed constant voltage 12 based on the first and second potentials and a power-supply voltage variation detecting circuit 20 for detecting a variation having a prescribed width of the power-supply voltage. The constant voltage generation circuit 10 increases a current flowing to a differential stage circuit, for a prescribed period when the power-supply voltage variation detecting circuit 20 detects the variation in the power-supply voltage. The power-supply voltage variation detecting circuit 20 can include a power-supply voltage rise detecting circuit 30 for detecting a variation in the power-supply voltage in a rising direction and a power-supply voltage fall detecting circuit 40 for detecting a variation in the power-supply voltage in a falling direction. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and an electronic apparatus.

  In an integrated circuit device (IC) mounted on a portable device, in order to make the battery life as long as possible, the power sources used in the system operation and the backup operation are different. For example, a large capacity lithium ion battery (for example, 3.0V) is used during system operation, and a small capacity button type battery (for example, 1.5V) is used during backup operation. In particular, clocks (RTC) ICs mounted on many portable devices are unlikely to be clocked, so they must operate during both system operation and backup operation, and the clock IC is stopped when the power supply voltage is switched. I can't do that either.

On the other hand, a clock IC is required to have low power consumption in order to increase the operation duration. Therefore, a constant voltage generation circuit for generating a low constant voltage is provided inside the IC, and a technique for operating a circuit with high power consumption, for example, a crystal oscillation circuit or a part of a frequency dividing circuit at a low constant voltage is often used. .
Japanese Patent Laid-Open No. 5-40535

  FIG. 12 shows a configuration of a conventional constant voltage generation circuit. In general, the constant voltage generation circuit includes a differential stage circuit and an output stage circuit, and the speed (slew rate (sec / V)) at which the constant voltage generation circuit operates differentially is the current i1 flowing through the differential stage circuit. And the load capacitance (phase compensation capacitor, etc.) of the differential stage output signal that controls the output stage circuit. That is, the larger the current i1, the shorter the time for charging and discharging the load capacity of the differential stage output signal, and the slew rate is improved. However, when the current i1 is increased, the power consumption of the constant voltage generation circuit is increased.

  When the current i1 is small, if the power supply voltage changes abruptly at the time of switching between the system operation and the backup operation, the output voltage Vreg of the constant voltage generation circuit may also fluctuate, which may cause an instantaneous stop or malfunction of the IC. FIG. 13 shows an example of how the constant voltage output Vreg fluctuates when the power supply voltage VDD fluctuates in the constant voltage generation circuit shown in FIG. When VDD is switched from 3.0V to 1.5V, Vreg decreases momentarily from 1.0V following the fluctuation of VDD. If Vreg is reduced to 0V, an instantaneous operation stop of a circuit operating at Vreg is caused. Further, when VDD is switched from 1.5 V to 3.0 V, Vreg rises momentarily following the fluctuation of VDD, which may cause malfunction of a circuit operating at Vreg.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor integrated circuit device that is less likely to malfunction even with a sudden fluctuation in power supply voltage and that consumes less power. To do.

(1) The semiconductor integrated circuit device of the present invention is
A semiconductor integrated circuit device that operates using a difference between a first potential supplied by a first potential supply line and a second potential lower than the first potential supplied by a second potential supply line as a power supply voltage. There,
A constant voltage generating circuit for generating a constant voltage based on the first potential and the second potential;
A power supply voltage fluctuation detection circuit for detecting a fluctuation in a predetermined width of the power supply voltage,
The constant voltage generation circuit includes:
A differential stage circuit that operates differentially based on a given reference voltage and the constant voltage;
An output stage circuit that outputs the constant voltage based on the output of the differential stage circuit,
When the power supply voltage fluctuation detection circuit detects the fluctuation of the power supply voltage, the current flowing in the differential stage circuit is increased only for a predetermined period.

  The first potential may be a potential (for example, 3V or 1.5V) supplied from a power source such as an AC adapter or a battery. The second potential may be a ground potential (0 V).

  For a given reference voltage, for example, a second terminal (which may be a ground potential) is used as a reference, and the other end of the constant current source whose one end is connected to the first potential supply line is connected to the gate terminal and the drain terminal. The voltage output from the drain terminal of the Nch transistor whose source terminal is connected to the second potential supply line may be used. A circuit (reference voltage generation circuit) included in the constant voltage generation circuit may generate the reference voltage, or the reference voltage generation circuit may be provided outside the constant voltage generation circuit. The reference voltage may be supplied from the outside of the semiconductor integrated circuit device.

  The fluctuation of the predetermined width of the power supply voltage may be generated when the first potential fluctuates, or may be generated when the second potential fluctuates. In addition, for example, when a plurality of potentials are switched and supplied to at least one of the first potential supply line and the second potential supply line, the power supply voltage may vary when switching. In this case, the means for switching the supplied potential may be inside or outside the semiconductor integrated circuit device. For example, the fluctuation of the predetermined width of the power supply voltage may be a case where the fluctuation of the power supply voltage occurs due to noise generated in the first potential supply line or the second potential supply line.

  According to the present invention, it is possible to shorten the time for charging and discharging the capacitance (phase compensation capacitor, parasitic capacitance, etc.) attached to the output of the differential stage circuit when the power supply voltage varies. Therefore, the output of the constant voltage generation circuit can be maintained at a constant constant voltage even when the power supply voltage varies.

  In addition, according to the present invention, it is possible to increase the current only when a fluctuation of a predetermined width of the power supply voltage is detected. Accordingly, since the constant voltage generation circuit can be operated with a very small current (for example, 10 nA) except when the first potential or the second potential is switched, the current increase is extremely small and the power consumption is extremely small. Can do.

  Therefore, it is possible to provide a semiconductor integrated circuit device that is less likely to malfunction even when the power supply voltage changes sharply and that consumes less power.

(2) The semiconductor integrated circuit device of the present invention is
The power supply voltage fluctuation detection circuit includes:
A power supply voltage rise detection circuit for detecting fluctuations in the power supply voltage rising direction;
The power supply voltage rising detection circuit is
A first capacitor circuit including at least one capacitor;
A first constant current supply circuit for supplying a predetermined constant current,
One end of the first capacitor circuit is connected to the first potential supply line,
One end of the first constant current supply circuit is connected to the second potential supply line,
The other end of the first capacitor circuit and the other end of the first constant current supply circuit are connected at a first connection point;
Based on the potential at the first connection point, a change in the power supply voltage in the increasing direction is detected.

  The first capacitor circuit may be composed of only one capacitor, or a combination of capacitors connected between the first potential supply line and the first connection point is arbitrarily selected from a plurality of capacitors. It is good also as a possible structure.

  The first constant current supply circuit may be composed of only one constant current source, or a constant current source connected between the first connection point and the second potential supply line from a plurality of constant current sources. It is good also as a structure which can select the combination of an electric current source arbitrarily.

  The fluctuation of the power supply voltage in the increasing direction may occur when the first potential increases, or may occur when the second potential decreases.

  According to the present invention, the potential at the first connection point rises following the fluctuation of the power supply voltage in the increasing direction, so that the fluctuation of the power supply voltage in the increasing direction can be detected.

  In addition, according to the present invention, since a simple power supply voltage rise detection circuit composed only of a constant current source and a capacitor is added, fluctuations in the power supply voltage increase direction can be detected with only a slight increase in cost. The fluctuation of the constant voltage output from the voltage generation circuit can be prevented.

  Further, according to the present invention, the adjustment of the capacitance value of the first capacitor circuit and the constant current value of the first constant current supply circuit can be made in accordance with the speed of fluctuation of the detected power supply voltage in the increasing direction. , Power supply voltage fluctuations can be detected quickly.

  Therefore, it is possible to provide a semiconductor integrated circuit device that is less likely to malfunction even when the power supply voltage is rapidly changed.

(3) A semiconductor integrated circuit device according to the present invention includes:
The power supply voltage rising detection circuit is
A second constant current supply circuit for supplying a predetermined constant current;
An Nch transistor,
One end of the second constant current supply circuit is connected to the first potential supply line,
A source terminal of the Nch transistor is connected to the second potential supply line;
A gate terminal of the Nch transistor is connected to the first connection point;
The other end of the second constant current supply circuit is connected to the drain terminal of the Nch transistor.

  According to the present invention, the difference between the potential of the first connection point and the second potential (the voltage between the gate and the source of the Nch transistor) that rises following the fluctuation of the power supply voltage in the increasing direction is the Nch transistor. When the threshold value is exceeded, a signal near the second potential (L level) is generated at the drain terminal of the Nch transistor. Therefore, it is possible to detect a fluctuation in the increasing direction of the power supply voltage.

  Further, according to the present invention, by adjusting the threshold value of the Nch transistor, it is possible to detect the fluctuation of the power supply voltage only when the fluctuation in the increase direction of the power supply voltage is a predetermined width or more.

(4) A semiconductor integrated circuit device according to the present invention includes:
The power supply voltage rising detection circuit is
Including inverter circuit,
An input terminal of the inverter circuit is connected to the first connection point.

  In the inverter circuit, for example, both gate terminals of a Pch transistor whose source terminal is connected to the first potential supply line and an Nch transistor whose source terminal is connected to the second potential supply line are connected to the first connection point. The inverter circuit may constitute an input terminal, and both drain terminals are connected to constitute an output terminal.

  According to the present invention, by adjusting the logic threshold value of the inverter circuit, an L-level signal is output to the output of the inverter circuit only when the fluctuation in the power supply voltage in the increasing direction is not less than a predetermined width. be able to.

(5) A semiconductor integrated circuit device according to the present invention includes:
The power supply voltage rising detection circuit is
It includes at least one of a circuit for switching a capacitance value of the first capacitor circuit and a circuit for switching a constant current value of the first constant current supply circuit.

  The circuit that switches the capacitance value of the first capacitor circuit may be configured to switch the capacitance value according to a control signal supplied from an external terminal or an internal register of the semiconductor integrated circuit device, for example.

  The circuit for switching the constant current value of the first constant current supply circuit may be configured to switch the constant current value according to a control signal supplied from an external terminal or an internal register of the semiconductor integrated circuit device, for example.

  According to the present invention, only by switching at least one of the capacitance value of the first capacitor circuit and the constant current value of the first constant current supply circuit, according to the speed of fluctuation in the rising direction of the power supply voltage to be detected. , Power supply voltage fluctuations can be detected quickly.

  Therefore, it is possible to provide a semiconductor integrated circuit device that is less likely to malfunction even when the power supply voltage is rapidly changed.

(6) The semiconductor integrated circuit device of the present invention is
The power supply voltage fluctuation detection circuit includes:
A power supply voltage falling detection circuit for detecting a change in the power supply voltage in a decreasing direction,
The power supply voltage falling detection circuit is:
A second capacitor circuit including at least one capacitor;
A third constant current supply circuit for supplying a predetermined constant current,
One end of the second capacitor circuit is connected to the second potential supply line,
One end of the third constant current supply circuit is connected to the first potential supply line,
The other end of the second capacitor circuit and the other end of the third constant current supply circuit are connected at a second connection point;
Based on the potential at the second connection point, a change in the power supply voltage in the decreasing direction is detected.

  The second capacitor circuit may be composed of only one capacitor, or a combination of capacitors connected between the second connection point and the second potential supply line is arbitrarily selected from a plurality of capacitors. It is good also as a possible structure.

  The third constant current supply circuit may be composed of only one constant current source, or a constant current source connected between the first potential supply line and the second connection point from a plurality of constant current sources. It is good also as a structure which can select the combination of an electric current source arbitrarily.

  The fluctuation of the power supply voltage in the decreasing direction may occur when the first potential decreases, or may occur when the second potential increases.

  According to the present invention, since the potential at the second connection point decreases after the power supply voltage decreases in the decreasing direction, the power supply voltage decreases in the decreasing direction based on the difference between the second connection point and the first potential. Fluctuations can be detected.

  In addition, according to the present invention, since a simple power supply voltage fall detection circuit composed only of a constant current source and a capacitor is only added, a fluctuation in the power supply voltage drop direction is detected with only a slight cost increase, The fluctuation of the constant voltage output from the constant voltage generation circuit can be prevented.

  Further, according to the present invention, the adjustment of the capacitance value of the second capacitor circuit and the constant current value of the third constant current supply circuit can be made in accordance with the speed of fluctuation of the detected power supply voltage in the decreasing direction. , Power supply voltage fluctuations can be detected quickly.

  Therefore, it is possible to provide a semiconductor integrated circuit device that is less likely to malfunction even when the power supply voltage is rapidly changed in the downward direction.

(7) A semiconductor integrated circuit device according to the present invention includes:
The power supply voltage falling detection circuit is:
A fourth constant current supply circuit for supplying a predetermined constant current;
Including a Pch transistor,
One end of the fourth constant current supply circuit is connected to the second potential supply line,
A source terminal of the Pch transistor is connected to the second connection point;
A gate terminal of the Pch transistor is connected to the first potential supply line;
The other end of the fourth constant current supply circuit is connected to the drain terminal of the Pch transistor.

  According to the present invention, the difference between the first potential and the potential at the second connection point that rises with a delay in the downward direction of the power supply voltage (the voltage between the gate and the source of the Pch transistor) is the threshold of the Pch transistor. When the value is lower, a signal near the first potential (H level) is generated at the drain terminal of the Pch transistor. Therefore, it is possible to detect fluctuations in the power supply voltage in the decreasing direction.

  Further, according to the present invention, by adjusting the threshold value of the Pch transistor, it is possible to detect the fluctuation of the power supply voltage only when the fluctuation of the power supply voltage in the decreasing direction is a predetermined width or more.

(8) A semiconductor integrated circuit device according to the present invention includes:
The power supply voltage falling detection circuit is:
It includes at least one of a circuit for switching the capacitance value of the second capacitor circuit and a circuit for switching the constant current value of the third constant current supply circuit.

  The circuit that switches the capacitance value of the second capacitor circuit may be configured to switch the capacitance value according to a control signal supplied from an external terminal or an internal register of the semiconductor integrated circuit device, for example.

  The circuit for switching the constant current value of the third constant current supply circuit may be configured to switch the constant current value according to a control signal supplied from an external terminal or an internal register of the semiconductor integrated circuit device, for example.

  According to the present invention, only by switching at least one of the capacitance value of the second capacitor circuit and the constant current value of the third constant current supply circuit, according to the speed of fluctuation of the detected power supply voltage in the decreasing direction. , Power supply voltage fluctuations can be detected quickly.

  Therefore, it is possible to provide a semiconductor integrated circuit device that is less likely to malfunction even when the power supply voltage is rapidly changed in the downward direction.

(9) The semiconductor integrated circuit device of the present invention is
It includes supply potential switching control means for switching at least one of the first potential and the second potential between a plurality of potentials.

  The supply potential switching control means may be realized as a dedicated circuit (hardware) or may be realized by a program (software) executed by the CPU.

  According to the present invention, for example, when the potential supplied by the battery or the like as the first potential drops and falls below a predetermined potential, the first potential is automatically switched to the potential supplied by the backup battery, for example. be able to.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device that is less likely to malfunction even when a sharp fluctuation in power supply voltage occurs during switching and that consumes less power.

(10) A semiconductor integrated circuit device according to the present invention includes:
It includes a clock means.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device that is less likely to malfunction even when a clock means that is not allowed to stop at all times, for example, does not malfunction even when a sudden fluctuation in power supply voltage occurs and that consumes less power. .

(11) A semiconductor integrated circuit device according to the present invention comprises:
Any of the above semiconductor integrated circuit devices;
Means for receiving input information;
Means for outputting a result processed by the semiconductor integrated circuit device based on input information.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Moreover, not all of the configurations described below are essential constituent requirements of the present invention.

1. Semiconductor Integrated Circuit Device FIG. 1 is a functional block diagram of the semiconductor integrated circuit device of the present embodiment.

  The semiconductor integrated circuit device 1 includes a VDD (first potential) supplied by a VDD supply line 60 (first potential supply line) and a VSS (first potential supply line) supplied by a VSS supply line 70 (second potential supply line). 2 potentials) is used as a power supply voltage.

  The semiconductor integrated circuit device 1 includes a constant voltage generation circuit 10. The constant voltage generation circuit 10 generates a constant voltage 12 based on VDD (first potential) and VSS (second potential), and supplies the constant voltage 12 to the operation circuit 80. Constant voltage generating circuit 10 includes a differential stage circuit (not shown) and an output stage circuit (not shown).

  The semiconductor integrated circuit device 1 includes a power supply voltage fluctuation detection circuit 20. The power supply voltage fluctuation detection circuit 20 operates to detect a fluctuation of a predetermined width of the power supply voltage. The power supply voltage fluctuation detection circuit 20 may include a power supply voltage rise detection circuit 30 that detects fluctuations in the power supply voltage in the increasing direction. Further, the power supply voltage fluctuation detection circuit 20 may include a power supply voltage falling detection circuit 40 that detects fluctuations in the power supply voltage in the decreasing direction.

  The semiconductor integrated circuit device 1 may include supply potential switching control means 50. The supply potential switching control unit 50 operates to switch VDD (first potential) between a plurality of potentials (VDD-1 to n). Accordingly, the power supply voltage fluctuates when the supply potential switching control means 50 switches VDD. Although not shown, the supply potential switching control unit 50 may operate to switch VSS (second potential) between a plurality of potentials.

  The constant voltage generation circuit 10 operates so as to increase the current flowing through the differential stage circuit only for a predetermined period when the power supply voltage fluctuation detection circuit 20 detects the fluctuation of the power supply voltage.

  FIG. 2 is a diagram for explaining a configuration example of a constant voltage generation circuit included in the semiconductor integrated circuit device of the present embodiment.

  The constant voltage generation circuit 10 includes a differential stage circuit 100 and an output stage circuit 150. The constant voltage generation circuit 10 may include a reference voltage supply circuit 180.

  The reference voltage supply circuit 180 includes a constant current source 184 and an N channel type MOSFET 182. The source terminal of the N-channel MOSFET 182 is connected (grounded) to the VSS supply line 70, and the gate terminal and the drain terminal are connected. The gate terminal and the drain terminal are connected to the node P. The node P is also connected to the gate terminal of the N-channel MOSFET 104 and the other end of the constant current source 184 whose one end is connected to VDD. The difference between the potential of the node P and VSS is input to the differential stage circuit 100 as a reference voltage. Reference voltage supply circuit 180 may be external to constant voltage generation circuit 10 or may be external to semiconductor integrated circuit device 1 (see FIG. 1).

  The differential stage circuit 100 includes constant current sources 102 and 122, N-channel MOSFETs 104, 106, and 120, and load-side P-channel MOSFETs 108 and 110.

  The other end of the constant current source 102 with one end grounded is connected to the source terminals of the N-channel MOSFETs 104 and 106 and one end of the constant current source 122. The other end of the constant current source 122 is connected to the drain terminal of an N-channel MOSFET 120 whose source terminal is grounded.

  The output terminal of the two-input OR circuit 130 is connected to the gate terminal of the N-channel MOSFET 120. The two inputs of the two-input OR circuit 130 are supplied with the output 32 of the power supply voltage rise detection circuit 30 (see FIG. 1) and the output 42 of the power supply voltage fall detection circuit 40 (see FIG. 1), respectively.

  The drain terminals of the N-channel MOSFETs 104 and 106 are connected to the drain terminals of the P-channel MOSFETs 108 and 110 on the load side, respectively.

  The gate terminals of the P-channel MOSFETs 108 and 110 on the load side are connected to each other, and the gate terminal and the drain terminal of the P-channel MOSFET 110 are connected. Thereby, a mirror circuit is configured on the load side.

  The output stage circuit 150 includes a constant current source 152 and P-channel MOSFETs 154 and 156, and may further include a phase compensation capacitor 158.

  One end of the constant current source 152 is grounded, and the other end is connected to the node P ′. The node P ′ is also connected to the gate terminal of the N-channel MOSFET 106 and the drain terminal of the P-channel MOSFET 154.

  The gate terminal and the drain terminal of the P-channel type MOSFET 154 are connected to each other, and the source terminal is connected to the node Q. This node Q is also connected to one end of the capacitor 158 and the drain terminal of the N-channel MOSFET 156. A constant voltage value Vreg is output from the node Q with respect to VSS.

  The gate terminal of the P-channel MOSFET 156 is connected to the drain terminal of the N-channel MOSFET 104, the drain terminal of the P-channel MOSFET 108, and the other end of the capacitor 158. A source terminal of the P-channel MOSFET 156 is connected to the VDD supply line 60. This P-channel MOSFET 156 is an output control transistor.

  Hereinafter, an outline of the operation of the constant voltage generation circuit 10 will be described.

  The potential of the drain terminal of the N-channel MOSFET 182, that is, the potential of the node P is set so that the constant current value supplied by the constant current source 184 flows. The potential of the node P is input to the gate terminal of the N-channel MOSFET 104 which is one input terminal of the differential pair comparator.

  A potential controlled by the output control P-channel type MOSFET 156 and the P-channel type MOSFET 154 is generated at the node P ′, and the potential of the node P ′ is an N-channel which is the other input terminal of the differential pair comparator. Negative feedback is provided to the gate terminal of the type MOSFET 106. With this configuration, the node P and the node P ′ are controlled to have the same potential by the operations of the differential pair N-channel MOSFETs 104 and 106 and the output control P-channel MOSFET 156. Since the current flowing through the node P ′ is constant by the constant current source 152, the potential difference between the node Q and the node P ′ becomes a constant voltage controlled by the P-channel MOSFET 154.

  By doing so, a constant voltage Vreg equal to the sum of the potential difference generated in the N-channel MOSFET 182 and the potential difference generated in the P-channel MOSFET 154 is output with VSS as the reference potential.

  By the way, when the power supply voltage fluctuates, the speed at which the constant voltage generation circuit 10 operates differentially (slew rate (sec / V)) is the current i1 flowing through the constant current source 102 of the differential stage circuit 100 and the output stage. It is determined by the relationship between the load capacitance of the differential stage output that controls the circuit 150 (the sum of the capacitance of the phase compensation capacitor 158 and the parasitic capacitance). That is, the slew rate increases as the time until the load capacitance of the differential stage output is charged / discharged by the current i1, and the constant voltage Vreg is less affected by fluctuations in the power supply voltage.

  Here, if the load capacity of the differential stage output is reduced, the slew rate is improved. However, for the stable operation of the constant voltage generation circuit, the capacity of the phase compensation capacitor 158 cannot be made extremely small, and the parasitic capacity is also increased to some extent.

  On the other hand, although the slew rate is improved even if the current i1 is increased, in order to reduce the power consumption of the constant voltage generation circuit 10, it is desirable that the current i1 that always flows is as small as possible.

  Therefore, in the constant voltage generation circuit 10 in FIG. 2, a constant current source 122 and a current for supplying a current i2 to the N-channel MOSFETs 104 and 106 of the differential pair are compared with the conventional constant voltage generation circuit shown in FIG. An N-channel MOSFET 120 that operates as a switch for controlling whether or not to pass i2 is added. The ON / OFF of the N-channel MOSFET 120 is controlled by the output signal of the 2-input OR circuit 130.

  When the power supply voltage fluctuates in the upward direction, the power supply voltage rise circuit 30 (see FIG. 1) outputs an H level (VDD) signal (rise detection signal) from the output 32. When the power supply voltage fluctuates in the downward direction, the power supply voltage falling circuit 40 (see FIG. 1) outputs an H level (VDD) signal (falling detection signal) from the output 42. That is, when the power supply voltage fluctuates, an H level (VDD) signal is generated at the output of the two-input OR circuit. Then, since the N-channel MOSFET 120 is turned on, a current of i1 + i2 flows through the N-channel MOSFETs 104 and 106 of the differential pair. Since the load capacitance of the differential stage output is charged / discharged by this current i1 + i2, the slew rate when the power supply voltage fluctuates can be improved.

  On the other hand, when the power supply voltage does not fluctuate, both the output 32 of the power supply voltage rising circuit 30 (see FIG. 1) and the output 42 of the power supply voltage falling circuit 40 output an L level (VSS) signal. Therefore, the output of the 2-input OR circuit is L level (VSS), and the N-channel MOSFET 120 is OFF. As a result, only the current i1 flows through the N-channel MOSFETs 104 and 106 of the differential pair.

  For example, if the current i1 is 10 nA, the current i2 is 10 μA, and the load capacitance of the differential stage output signal A is 10 pF, the slew rate when the power supply voltage varies is about 1 μs / V. That is, the differential operation of the constant voltage generation circuit 10 can follow a steep power supply fluctuation of 1 μs / V.

  Therefore, the constant voltage generation circuit 10 can maintain a constant voltage (Vreg) output even when a sudden power supply fluctuation occurs. On the other hand, when the power supply voltage does not fluctuate, only the current i1 (10 nA) flows through the differential pair N-channel MOSFETs 104 and 106, so that the power consumption of the constant voltage generation circuit 10 can be reduced.

  FIG. 3 is a diagram for explaining a configuration example of a power supply voltage rise detection circuit included in the semiconductor integrated circuit device of the present embodiment.

  The power supply voltage rise detection circuit 30 includes a capacitor 302 (first capacitor circuit), a constant current source 304 (first constant current supply circuit), a constant current source 306 (second constant current supply circuit), and an N-channel MOSFET 308. (Nch transistor), and further includes an N-channel MOSFET 312 and a P-channel MOSFET 310.

  The node A (first connection point) includes the other end of the capacitor 302 whose one end is connected to the VDD supply line 60, the other end of the constant current source 304 whose one end is connected (grounded) to the VSS supply line 70, the source A gate terminal of an N-channel MOSFET 308 whose terminal is grounded is connected.

  At node B, the other end of the constant current source 306 having one end connected to the VDD supply line 60, the drain terminal of the N-channel MOSFET 308, the gate terminal of the N-channel MOSFET 312 grounded at the source terminal, and the source terminal supplied with VDD. A gate terminal of a P-channel MOSFET 310 connected to the line 60 is connected.

  The node C is connected to the drain terminal of the N-channel MOSFET 312 and the drain terminal of the P-channel MOSFET 310. That is, the N-channel MOSFET 312 and the P-channel MOSFET 310 constitute an inverter circuit. Therefore, the nodes B and C become the input and output of the inverter circuit, respectively, and the potentials of the nodes B and C are in a relationship in which the H level and the L level are inverted.

  The output (node C) of the inverter circuit becomes the output 32 of the power supply voltage rising detection circuit 30. The inverter circuit is added to output the rising detection signal from the output 32 with positive logic, and is not an essential component of the power supply voltage rising detection circuit 30.

  FIG. 4 is a timing chart for explaining the operation of the power supply voltage rise detection circuit. The operation of the power supply voltage rise detection circuit described with reference to FIG. 3 will be described below with reference to FIG.

  Since the power supply voltage has not changed before time T1, the potential of the node A is pulled to the VSS side by the constant current source 304 and is at the L level (0 V). Therefore, the N-channel MOSFET 308 is turned off because the voltage between the gate and the source is below the threshold value, and the potential of the node B is H level (3.0 V) near VDD by the constant current source 306. Therefore, the potential of the node C is L level (0 V).

  From time T1 to time T2, VDD is switched from 3.0 V to 1.5 V, and the power supply voltage is steeply changed in the decreasing direction. However, the constant current source 304 maintains the potential of the node A at the L level (0 V). Accordingly, the potentials of the nodes B and C are also maintained at the H level (3.0 V to 1.5 V) and the L level (0 V), respectively. That is, the fluctuation of the power supply voltage in the decreasing direction is not detected.

  Since the power supply voltage does not fluctuate from time T2 to T3, the potentials of the nodes A, B, and C are maintained at the L level (0 V), the H level (1.5 V), and the L level (0 V), respectively.

  From time T3 to T5, VDD is switched from 1.5V to 3.0V, and the power supply voltage is steeply changed in the increasing direction. Then, the potential of the node A rises because it is pulled to the VDD side by the capacitor 302. As the potential of the node A rises, the voltage between the gate and the source of the N-channel MOSFET 308 reaches the threshold at time T4, so that the N-channel MOSFET 308 is turned on. Therefore, the potential of the node B becomes L level (0 V), and the potential of the node C becomes H level (1.5 V to 3.0 V).

  Since the power supply voltage does not fluctuate after time T5, the potential of the node A is pulled to the VSS side by the constant current source 304 and starts decreasing from time T5.

  After time T6, since the voltage between the gate and the source of the N-channel MOSFET 308 is below the threshold value, the N-channel MOSFET 308 is turned off. Therefore, the potential of the node B becomes H level (3.0 V), and the potential of the node C becomes L level (0 V).

  As described above, with the fluctuation of the power supply voltage in the rising direction at times T3 to T5, the output 32 (node C) of the power supply voltage rising detection circuit 30 is at the H level (1.5 to 3) only during the time T4 to T6. .0V) signal (rising edge detection signal) is generated.

  The power supply voltage rise detection circuit 30 shown in FIG. 3 can detect fluctuations in the power supply voltage in the increasing direction based on the potential of the node A (first connection point).

  FIG. 5 is a diagram for explaining a first modification of the power supply voltage rise detection circuit. The same components as those in FIG.

  In the power supply voltage rise detection circuit 30 shown in FIG. 5, a P-channel MOSFET 314 is used instead of the constant current source 306 in FIG. The source terminal, gate terminal, and drain terminal of the P-channel MOSFET 314 are connected to the VDD supply line 60, the node A, and the node B, respectively. Accordingly, the N-channel MOSFET 308 and the P-channel MOSFET 314 constitute an inverter circuit.

  Here, the input terminal of the inverter circuit is connected to the node A (first connection point). The output terminal of the inverter circuit is connected to the node B. That is, the nodes A and B are the input and output of the inverter circuit, respectively, and the potentials of the nodes A and B are in a relationship in which the H level and the L level are inverted.

  In FIG. 3, the width of the power supply voltage fluctuation for generating the rising detection signal is determined by the threshold value of the N-channel MOSFET 308. On the other hand, in the power supply voltage rise detection circuit 30 shown in FIG. 5, the width of the power supply voltage fluctuation for generating the rise detection signal is determined by the logic threshold value of the inverter circuit constituted by the N-channel MOSFET 308 and the P-channel MOSFET 314. I have decided. Therefore, for example, by adjusting the W / L of the N-channel MOSFET 308 and the P-channel MOSFET 314 to change the logic threshold value of the inverter circuit, the width of the power supply voltage fluctuation for generating the rising detection signal can be simplified. Can be changed.

  The operation of power supply voltage rise detection circuit 30 shown in FIG. 5 is almost the same as the operation of power supply voltage rise detection circuit 30 shown in FIG. 3, and its timing chart is the same as the timing chart of FIG. Omitted.

  FIG. 6 is a diagram for explaining a second modification of the power supply voltage rise detection circuit. The same components as those in FIG.

  In the power supply voltage rise detection circuit 30 shown in FIG. 6, a first capacitor circuit is configured by n capacitors 302-1 to 30-n and n P-channel MOSFETs 316-1 to 316-n instead of the capacitor 302 in FIG. Has been.

  Further, instead of the constant current source 304 in FIG. 5, a first constant current supply circuit is configured by m constant current sources 304-1 to m and m N channel MOSFETs 320-1 to 320-m.

  That is, the other end of each capacitor 302-j (j is an integer from 1 to n) whose one end is connected to the VDD supply line 60 is connected to the source terminal of each P-channel MOSFET 316-j. The drain terminal of the channel MOSFET 316-j is connected to the node A (first connection point). The other end of each constant current source 304-k (k is an integer from 1 to m) whose one end is connected (grounded) to the VSS supply line 70 is connected to the source terminal of each N-channel MOSFET 320-k. The drain terminal of each N-channel MOSFET 320-k is connected to the node A.

  Further, a control signal 318-j is supplied to the gate terminal of each P-channel MOSFET 316-j. Therefore, when the control signal 318-j is at the L level, the P-channel MOSFET 316-j is turned on, and one end of the capacitor 302-j is electrically connected to the node A via the P-channel MOSFET 316-j. When the control signal 318-j is at the H level, the P-channel MOSFET 316-j is turned off, and the capacitor 302-j is not electrically connected to the node A. Therefore, by setting the control signals 318-1 to n to any combination of L level or H level, any of the capacitors 302-1 to 302-n electrically connected between the VDD supply line 60 and the node A can be selected. Combinations can be realized.

  That is, the P-channel MOSFETs 316-1 to 316-n function as a circuit that switches the capacitance value of the first capacitor circuit, and the capacitance value between the VDD supply line 60 and the node A can be selected from a plurality of capacitance values. .

  A control signal 322-k is supplied to the gate terminal of each N-channel MOSFET 320-k. Therefore, when the control signal 322-k is at the H level, the N-channel MOSFET 320-k is turned on, and one end of the constant current source 304-k is electrically connected to the node A via the N-channel MOSFET 320-k. The When the control signal 322-k is at the L level, the N-channel MOSFET 320-k is turned off, and the constant current source 304-k is not electrically connected to the node A. Therefore, by setting the control signals 322-1 to m to an arbitrary combination of the H level and the L level, the constant current sources 304-1 to 304-m electrically connected between the node A and the VSS supply line 70 are set. Any combination can be realized.

  That is, the N-channel MOSFETs 320-1 to 320-m function as a circuit for switching the constant current value of the first constant current supply circuit, and select a constant current value flowing from the node A to the VSS supply line 70 from a plurality of current values. be able to.

  As described above, the power supply voltage rise detection circuit 30 shown in FIG. 6 can variably control the capacitance value and the constant current value of the capacitor for detecting the fluctuation of the power supply voltage. Accordingly, it is possible to easily select an appropriate capacitance value and constant current value of the capacitor in order to quickly detect the fluctuation of the power supply voltage in accordance with the speed of the fluctuation of the power supply voltage to be detected.

  The operation of the power supply voltage rise detection circuit 30 shown in FIG. 6 is almost the same as the operation of the power supply voltage rise detection circuit 30 shown in FIGS. 3 and 5, and its timing chart is the same as the timing chart of FIG. Therefore, it is omitted.

  FIG. 7 is a diagram for explaining a configuration example of a power supply voltage falling detection circuit included in the semiconductor integrated circuit device of the present embodiment.

  The power supply voltage falling detection circuit 40 includes a capacitor 402 (second capacitor circuit), a constant current source 404 (third constant current supply circuit), a constant current source 406 (fourth constant current supply circuit), a P-channel type. It includes a MOSFET 408 (Pch transistor), and further includes N-channel MOSFETs 412 and 416 and P-channel MOSFETs 410 and 414.

  The node D (second connection point) has one end connected to the VSS supply line 70 (grounded), the other end of the capacitor 402, the other end connected to the VDD supply line 60, the other end of the constant current source 404, a gate A source terminal of a P-channel MOSFET 408 whose terminal is connected to the VDD supply line 60 is connected.

  The node E is connected to the other end of the constant current source 406 whose one end is grounded, the drain terminal of the P-channel MOSFET 408, the gate terminal of the N-channel MOSFET 412 whose source terminal is grounded, and the source terminal to the VDD supply line 60. The gate terminal of the P-channel MOSFET 410 is connected.

  The node F includes a drain terminal of an N-channel MOSFET 412, a drain terminal of a P-channel MOSFET 410, a gate terminal of an N-channel MOSFET 416 whose source terminal is grounded, and a P-channel MOSFET 414 whose source terminal is connected to a VDD supply line 60. The gate terminal is connected. That is, the inverter circuit 1 is configured by the N-channel MOSFET 412 and the P-channel MOSFET 410. Therefore, the nodes E and F become the input and output of the inverter circuit 1, respectively, and the potentials of the nodes E and F are in a relationship in which the H level and the L level are inverted.

  The node G is connected to the drain terminal of the N-channel MOSFET 416 and the drain terminal of the P-channel MOSFET 414. That is, the inverter circuit 2 is configured by the N-channel MOSFET 416 and the P-channel MOSFET 414. Therefore, the nodes F and G become the input and output of the inverter circuit 2, respectively, and the potentials of the nodes F and G are in a relationship in which the H level and the L level are inverted.

  The output (node G) of the inverter circuit 2 becomes the output 42 of the power supply voltage falling detection circuit 40. The inverter circuit 1 is added to shape the waveform of the signal at the node E, and is not an essential component of the power supply voltage falling detection circuit 40. The inverter circuit 2 is added to output a falling detection signal from the output 42 with positive logic, and is not an essential component of the power supply voltage falling detection circuit 40.

  FIG. 8 is a timing chart for explaining the operation of the power supply voltage falling detection circuit. The operation of the power supply voltage falling detection circuit described with reference to FIG. 7 will be described below with reference to FIG.

  Since the power supply voltage has not changed before time T1, the potential of the node D is pulled to the VDD side by the constant current source 404 and is at the H level (3.0 V). Therefore, the P-channel MOSFET 408 is turned off because the gate-source voltage exceeds the threshold value, and the potential of the node E is at the L level (0 V) near VSS by the constant current source 406. Therefore, the potentials of the nodes F and G are H level (3.0 V) and L level (0 V), respectively.

  At time T1 to T3, when VDD changes from 3.0 V to 1.5 V and the power supply voltage changes steeply in the downward direction, the potential at node D follows VDD with a slight delay (time T2 to T5). Since the power supply voltage does not fluctuate from time T3 to time T6, the potential of the node D becomes VDD (1.5 V) at time T5.

  Here, since the voltage between the gate and the source of the P-channel MOSFET 408 is below the threshold value during the time T2 to T4, the P-channel MOSFET 408 is turned on. Therefore, during time T2 to T4, the potential of the node E is at the H level (3.0 V to 1.5 V) that is substantially equal to the potential of the node D. Therefore, the potentials of the nodes F and G are L level (0 V) and H level (3.0 V to 1.5 V), respectively.

  Since the power supply voltage does not change from time T4 to T6, the potentials of the nodes D, E, F, and G are H level (1.5 V), L level (0 V), H level (1.5 V), and L level, respectively. (0V).

  When VDD is switched from 1.5 V to 3.0 V at time T6 to T8 and the power supply voltage fluctuates sharply in the increasing direction, the potential of the node D follows VDD with a slight delay (time T7 to T9). However, since the voltage between the gate and the source of the P-channel MOSFET 408 does not fall below the threshold value, the P-channel MOSFET 408 remains OFF. Therefore, at times T6 to T9, the potentials of the nodes E, F, and G are maintained at the L level (0 V), the H level (1.5 V to 3.0 V), and the L level (0 V), respectively. That is, fluctuations in the power supply voltage increase direction are not detected.

  Since the power supply voltage does not fluctuate after time T9, the potentials of nodes D, E, F, and G are H level (3.0 V), L level (0 V), H level (3.0 V), and L level (0 V), respectively. To maintain.

  As described above, the output 42 (node G) of the power supply voltage falling detection circuit 40 is set to the H level (3.0 V to 3.0V) only during the time T2 to T4 with the fluctuation of the power supply voltage in the time T1 to T3. 1.5V) signal (falling detection signal) is generated.

  According to the power supply voltage falling detection circuit shown in FIG. 7, it is possible to detect a fluctuation of the power supply voltage in the decreasing direction based on the potential of the node D (second connection point).

  FIG. 9 is a diagram for explaining a modification of the power supply voltage falling detection circuit. The same components as those in FIG.

  In the power supply voltage falling detection circuit 40 shown in FIG. 9, a second capacitor circuit is formed by n capacitors 402-1 to n and n N-channel MOSFETs 418-1 to n instead of the capacitor 402 in FIG. It is configured.

  Further, a third constant current supply circuit is configured by m constant current sources 404-1 to 404-m and m P channel type MOSFETs 422-1 to m instead of the constant current source 404 in FIG. 7.

  That is, one end is connected (grounded) to the VSS supply line 70, but the other end of each capacitor 402-j (j is an integer from 1 to n) is connected to the source terminal of each N-channel MOSFET 418-j. The drain terminal of each N-channel MOSFET 418-j is connected to the node D (second connection point). The other end of each constant current source 404-k (k is an integer of 1 to m) whose one end is connected to the VDD supply line 60 is connected to the source terminal of each P-channel MOSFET 422-k. The drain terminal of each P-channel MOSFET 422-k is connected to the node D.

  Further, a control signal 420-j is supplied to the gate terminal of each N-channel MOSFET 418-j. Therefore, when the control signal 420-j is at the H level, the N-channel MOSFET 418-j is turned on, and one end of the capacitor 402-j is electrically connected to the node D through the N-channel MOSFET 418-j. When the control signal 420-j is at the L level, the N-channel MOSFET 418-j is turned off and the capacitor 402-j is not electrically connected to the node D. Therefore, by setting the control signals 420-1 to 420-n to any combination of H level or L level, any of the capacitors 402-1 to 40-n that are electrically connected between the node D and the VSS supply line 70. Combinations can be realized.

  That is, the N-channel MOSFETs 418-1 to 418-n function as a circuit that switches the capacitance value of the second capacitor circuit, and the capacitance value between the node D and the VSS supply line 70 can be selected from a plurality of capacitance values. .

  A control signal 424-k is supplied to the gate terminal of each P-channel MOSFET 422-k. Therefore, when the control signal 424-k is at the L level, the P-channel MOSFET 422-k is turned on, and one end of the constant current source 404-k is electrically connected to the node D via the P-channel MOSFET 422-k. The When the control signal 424-k is at the H level, the P-channel MOSFET 422-k is turned off, and the constant current source 404-k is not electrically connected to the node D. Therefore, by setting the control signals 424-1 to m to any combination of L level or H level, the constant current sources 404-1 to 404-m electrically connected between the VDD supply line 60 and the node D are set. Any combination can be realized.

  That is, the P-channel MOSFETs 422-1 to 422-m function as a circuit that switches the constant current value of the third constant current supply circuit, and selects a constant current value that flows from the VDD supply line 60 to the node D from a plurality of current values. be able to.

  As described above, the power supply voltage fall detection circuit 40 shown in FIG. 9 can variably control the capacitance value and the constant current value of the capacitor for detecting the fluctuation of the power supply voltage. Accordingly, it is possible to easily select an appropriate capacitance value and constant current value of the capacitor in order to quickly detect the fluctuation of the power supply voltage in accordance with the speed of the fluctuation of the power supply voltage to be detected.

  The operation of the power supply voltage falling detection circuit 40 shown in FIG. 9 is almost the same as the operation of the power supply voltage falling detection circuit 40 shown in FIG. 7, and its timing chart is the same as the timing chart of FIG. I will omit it.

2. Electronic Device FIG. 10 shows an example of a block diagram of an electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, a sound output unit 860, and a clock (RTC) IC (semiconductor integrated circuit device).

  Here, the input unit 820 is for inputting various data. The semiconductor integrated circuit device 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  A clock (RTC) IC 870 is an IC having a function of keeping the current time (clock means), and is an example of the semiconductor integrated circuit device of the present embodiment. The clock (RTC) IC 870 operates with the system power supply while the microcomputer 810 is operating, but continues to operate with the backup power supply even when the system operation is stopped. The clock (RTC) IC 870 is less likely to malfunction even when switching between the system power supply and the backup power supply occurs and the power supply voltage fluctuates sharply because the internal constant voltage generation circuit holds the constant voltage output.

  FIG. 11A illustrates an example of an external view of a cellular phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 11B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 11C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the semiconductor integrated circuit device of this embodiment into the electronic devices in FIGS. 11A to 11C, an electronic device that is less likely to malfunction even with abrupt fluctuations in power supply voltage and has low power consumption. Equipment can be provided.

  As electronic devices that can use this embodiment, in addition to those shown in FIGS. 11 (A), (B), and (C), a portable information terminal, a pager, an electronic desk calculator, a device including a touch panel, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

1 is a functional block diagram of a semiconductor integrated circuit device of an embodiment. 4 is a diagram for explaining a configuration example of a constant voltage generation circuit included in the semiconductor integrated circuit device of this embodiment. FIG. FIG. 6 is a diagram for explaining a configuration example of a power supply voltage rising detection circuit included in the semiconductor integrated circuit device of this embodiment. 6 is a timing chart for explaining the operation of the power supply voltage rise detection circuit. The figure for demonstrating the 1st modification of a power supply voltage rise detection circuit. The figure for demonstrating the 2nd modification of a power supply voltage rise detection circuit. FIG. 6 is a diagram for explaining a configuration example of a power supply voltage falling detection circuit included in the semiconductor integrated circuit device of this embodiment. 6 is a timing chart for explaining the operation of the power supply voltage falling detection circuit. The figure for demonstrating the modification of a power supply voltage fall detection circuit. An example of a block diagram of an electronic device including a semiconductor integrated circuit device is shown. 11A, 11B, and 11C are examples of external views of various electronic devices. The figure for demonstrating the structure of the conventional constant voltage generation circuit. The figure for demonstrating the fluctuation | variation of the constant voltage output Vreg when the power supply voltage VDD fluctuates in the conventional constant voltage generation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device, 10 Constant voltage generation circuit, 12 Constant voltage output, 20 Power supply voltage fluctuation detection circuit, 30 Power supply voltage rise detection circuit, 32 Rise detection signal, 40 Power supply voltage fall detection circuit, 42 Fall detection signal, 50 supply potential switching control means, 60 VDD supply line, 70 VSS supply line, 80 operation circuit, 100 differential stage circuit, 102 constant current source, 104 N channel type MOSFET, 106 N channel type MOSFET, 108 P channel type MOSFET, 110 P-channel MOSFET, 120 N-channel MOSFET, 122 constant current source, 130 2-input OR circuit, 150 output stage circuit, 152 constant current source, 154 P-channel MOSFET, 156 P-channel MOSFET, 158 capacitor, 180 Quasi-voltage supply circuit, 182 P-channel MOSFET, 184 constant current source, 302 capacitor, 302-1 to n capacitor, 304 constant current source, 304-1 to m constant current source, 306 constant current source, 308 N-channel MOSFET 310 P-channel MOSFET, 312 N-channel MOSFET, 314 P-channel MOSFET, 316-1 to n P-channel MOSFET, 318-1 to n control signal, 320-1 to m N-channel MOSFET, 322-1 ~ M control signal, 402 capacitor, 402-1 to n capacitor, 404 constant current source, 404-1 to m constant current source, 406 constant current source, 408 P channel MOSFET, 410 P channel MOSFET, 412 N channel type MOSFET, 414 P channel MOSFET, 416 N-channel MOSFET, 418-1 to n N-channel MOSFET, 420-1 to n control signal, 422-1 to m P-channel MOSFET, 424-1 to m control signal, 800 electronic device, 810 micro Computer (ASIC), 820 input unit, 830 memory, 840 power generation unit, 850 LCD, 860 sound output unit, 870 IC for clock (RTC), 950 mobile phone, 952 dial button, 954 LCD, 956 speaker, 960 portable type Game device, 962 operation button, 964 cross key, 966 LCD, 968 speaker, 970 personal computer, 972 keyboard, 976 sound output unit

Claims (11)

A semiconductor integrated circuit device that operates using a difference between a first potential supplied by a first potential supply line and a second potential lower than the first potential supplied by a second potential supply line as a power supply voltage. There,
A constant voltage generating circuit for generating a constant voltage based on the first potential and the second potential;
A power supply voltage fluctuation detection circuit for detecting a fluctuation in a predetermined width of the power supply voltage,
The constant voltage generation circuit includes:
A differential stage circuit that operates differentially based on a given reference voltage and the constant voltage;
An output stage circuit that outputs the constant voltage based on the output of the differential stage circuit,
A semiconductor integrated circuit device characterized in that, when the power supply voltage fluctuation detection circuit detects a fluctuation in the power supply voltage, a current flowing through the differential stage circuit is increased only for a predetermined period. In claim 1,
The power supply voltage fluctuation detection circuit includes:
A power supply voltage rise detection circuit for detecting fluctuations in the power supply voltage rising direction;
The power supply voltage rising detection circuit is
A first capacitor circuit including at least one capacitor;
A first constant current supply circuit for supplying a predetermined constant current,
One end of the first capacitor circuit is connected to the first potential supply line,
One end of the first constant current supply circuit is connected to the second potential supply line,
The other end of the first capacitor circuit and the other end of the first constant current supply circuit are connected at a first connection point;
A semiconductor integrated circuit device that detects a change in the power supply voltage in an increasing direction based on a potential at the first connection point. In claim 2,
The power supply voltage rising detection circuit is
A second constant current supply circuit for supplying a predetermined constant current;
An Nch transistor,
One end of the second constant current supply circuit is connected to the first potential supply line,
A source terminal of the Nch transistor is connected to the second potential supply line;
A gate terminal of the Nch transistor is connected to the first connection point;
A semiconductor integrated circuit device, wherein the other end of the second constant current supply circuit is connected to the drain terminal of the Nch transistor. In claim 2,
The power supply voltage rising detection circuit is
Including inverter circuit,
A semiconductor integrated circuit device, wherein an input terminal of the inverter circuit is connected to the first connection point. In any of claims 2 to 4,
The power supply voltage rising detection circuit is
A semiconductor integrated circuit device comprising at least one of a circuit for switching a capacitance value of the first capacitor circuit and a circuit for switching a constant current value of the first constant current supply circuit. In any one of Claims 1 thru | or 5,
The power supply voltage fluctuation detection circuit includes:
A power supply voltage falling detection circuit for detecting a change in the power supply voltage in a decreasing direction,
The power supply voltage falling detection circuit is:
A second capacitor circuit including at least one capacitor;
A third constant current supply circuit for supplying a predetermined constant current,
One end of the second capacitor circuit is connected to the second potential supply line,
One end of the third constant current supply circuit is connected to the first potential supply line,
The other end of the second capacitor circuit and the other end of the third constant current supply circuit are connected at a second connection point;
A semiconductor integrated circuit device that detects a change in the power supply voltage in a decreasing direction based on a potential of the second connection point. In claim 6,
The power supply voltage falling detection circuit is:
A fourth constant current supply circuit for supplying a predetermined constant current;
Including a Pch transistor,
One end of the fourth constant current supply circuit is connected to the second potential supply line,
A source terminal of the Pch transistor is connected to the second connection point;
A gate terminal of the Pch transistor is connected to the first potential supply line;
A semiconductor integrated circuit device, wherein the other end of the fourth constant current supply circuit is connected to the drain terminal of the Pch transistor. In claim 6 or 7,
The power supply voltage falling detection circuit is:
A semiconductor integrated circuit device comprising at least one of a circuit for switching a capacitance value of the second capacitor circuit and a circuit for switching a constant current value of the third constant current supply circuit. In any one of Claims 1 thru | or 8.
A semiconductor integrated circuit device comprising supply potential switching control means for switching at least one of the first potential and the second potential between a plurality of potentials. In any one of Claims 1 thru | or 9,
A semiconductor integrated circuit device comprising a clock means. A semiconductor integrated circuit device according to any one of claims 1 to 10,
Means for receiving input information;
Means for outputting a result processed by the semiconductor integrated circuit device based on input information.

Images