JP2010191869A - Constant voltage circuit and its operation control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a constant voltage circuit and its operation control method for controlling a plurality of output transistors with simple circuit configurations. <P>SOLUTION: This constant voltage circuit is provided with: first and second output transistors M1 and M2 for outputting currents corresponding to a control signal input to a gate from an input terminal IN to an output terminal OUT, and for controlling an output voltage Vout; a differential amplifier circuit 3 for amplifying and outputting a voltage difference between a prescribed reference voltage Vref and a feedback voltage Vfb proportional to the output voltage Vout; and first and second amplifier circuits 4 and 5 for amplifying the output voltage Va of the differential amplifier circuit 3, and for outputting it to the gate of each of the first and the second output transistors M1 and M2. The first and the second amplifier circuits 4 and 5 successively turn on the corresponding first and second output transistors M1 and M2 in a prescribed order to make those respective output transistors M1 and M2 operate in accordance with the input voltage Va from the differential amplifier circuit 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a constant voltage circuit configured to control so that current output is shared by a plurality of output transistors.

Conventionally, in a constant voltage circuit in which the output current greatly fluctuates, the capacity of the output transistor has been designed in accordance with the maximum output current, and thus a large capacity output transistor has been required. In particular, when such a constant voltage circuit is formed in a semiconductor device including the output transistor, the large capacity output transistor has a very large gate capacity, and it takes time to charge and discharge the gate capacity. There was a problem that the performance deteriorated and the ripple removal rate decreased.
In order to quickly charge and discharge the gate capacitance, it is necessary to increase the output capacitance of the amplifier circuit in the previous stage, but in this case, the current consumption of the power supply circuit itself increases in a region where the output current is small. There was a problem that the power supply efficiency was lowered.
In addition, since phase compensation is performed over a wide range of current values, it is necessary to increase the phase compensation capacitor. Furthermore, heat generation is concentrated at one point of the output transistor, so it is necessary to consider heat dissipation. was there.

Therefore, a method of sharing current output by a plurality of transistors has been proposed. By sharing the current output with a plurality of transistors, the size of each output transistor can be reduced, and the gate capacitance of each output transistor can be reduced. As a result, the output capacity of the preceding amplifier circuit can be reduced. In addition, since the heat generation points can be dispersed, the temperature of the chip can be averaged, heat dissipation is simplified, and in some cases it is unnecessary.
In addition, there has been a technique for measuring a voltage drop of a current detection resistor connected in series to each output transistor and performing control so that output currents flowing through the respective output transistors are substantially equal (for example, Patent Document 1 and 2). Furthermore, there is a technique in which an average output current is dispersed by operating a plurality of output transistors alternately (see, for example, Patent Document 2).

  However, in the conventional system as described above, a current detection resistor is provided in series with the output transistor in order to control the output current output from the plurality of output transistors to be equal. For this reason, as the output current increases, the power loss due to the current detection resistor increases, and the efficiency of the power supply decreases. Further, since a comparator for comparing the voltage drop of the current detection resistor is provided for each output transistor, there is a problem that the circuit becomes large.

  The present invention has been made to solve such a problem, and can control a plurality of output transistors with a simple circuit configuration without using a current detection resistor connected in series to the output transistor. An object of the present invention is to obtain a constant voltage circuit and an operation control method thereof.

A constant voltage circuit according to the present invention is a constant voltage circuit that converts an input voltage input from an input terminal into a predetermined voltage and outputs the voltage as an output voltage from an output terminal.
A plurality of output transistors for controlling the output voltage by outputting a current according to a control signal input to the control electrode from the input terminal to the output terminal;
A differential amplifier circuit unit that amplifies and outputs a voltage difference between a predetermined reference voltage and a feedback voltage proportional to the output voltage;
Amplifying circuit portions provided corresponding to the output transistors for amplifying the output voltage of the differential amplifier circuit portion and outputting the amplified output voltage to the control electrodes of the corresponding output transistors;
With
Each of the amplifier circuit units is operated by sequentially turning on the corresponding output transistors in a predetermined order according to the input voltage from the differential amplifier circuit unit.

  Specifically, each of the output transistors is formed so that the sum of currents that are turned on and output is equal to or less than a predetermined maximum value.

  In addition, each of the amplifier circuit units constitutes a common-source amplifier circuit having a MOS transistor that performs voltage control of the control electrode of the corresponding output transistor, and the threshold voltages of the MOS transistors are different. By forming each MOS transistor so as to have a value, the corresponding output transistors are turned on and operated in a predetermined order according to the input voltage from the differential amplifier circuit section.

  In this case, the MOS transistor of the amplifier circuit unit that turns on the output transistor corresponding to the (n + 1) th (n is a positive integer) outputs the output of the amplifier circuit unit that turns on the output transistor corresponding to the nth. The threshold voltage is set to be the same voltage as the output voltage of the differential amplifier circuit section when the voltage is saturated.

  In addition, each output transistor includes a current limiting circuit unit that limits the output current from the output transistor so that the output current output from the corresponding output transistor is less than or equal to the corresponding maximum allowable current value. It may be provided corresponding to each.

  In this case, the MOS transistor of the amplifier circuit section that turns on the output transistor corresponding to the (n + 1) th is the differential amplifier circuit when the output transistor that operates nth reaches the maximum allowable current value. The threshold voltage is set to be the same voltage as the output voltage of the part.

  The threshold voltages of the MOS transistors of the amplifier circuits are set by changing the ratio of the gate width to the gate length.

  The threshold voltage of each of the MOS transistors in each of the amplifier circuit units may be set by changing a current value supplied to the drain.

  Further, the MOS transistors of the amplifier circuit units may be set to have threshold voltages by changing the ratio of the gate width to the gate length and the current value supplied to the drain.

The operation control method of the constant voltage circuit according to the present invention controls the output voltage output from the output terminal by outputting a current corresponding to the control signal input to the control electrode from the input terminal to the output terminal. Provided with a plurality of output transistors, the operation of each output transistor is controlled so that the feedback voltage proportional to the output voltage becomes a predetermined reference voltage, and the input voltage input from the input terminal is converted into the predetermined voltage In the operation control method of the constant voltage circuit that outputs as the output voltage from the output terminal,
When the output current output from the output terminal reaches the maximum allowable current value of the output transistor turned on first, the second output transistor is maintained while maintaining the maximum allowable current from the output transistor turned on first. And
Hereinafter, when the output current exceeds the sum of the maximum allowable currents in the first to nth (n is a positive integer) output transistors in the turn-on order, the currents from the first to nth output transistors While maintaining each maximum allowable current, operating the (n + 1) th output transistor,
As the output current increases, the output transistors are sequentially turned on and operated in a predetermined order.

  Specifically, the operation of each output transistor is controlled so that the sum of the currents output from each output transistor is not more than a predetermined maximum value.

  In addition, the output current value from each output transistor may be limited so that each output current output from each output transistor is correspondingly less than or equal to the maximum allowable current value respectively set. .

  According to the constant voltage circuit and the operation control method of the present invention, the maximum output current per output transistor can be made smaller than the maximum output current of the constant voltage circuit, and a small-sized output transistor can be used. Therefore, for example, when a MOS transistor is used as the output transistor, the required response speed can be ensured even if the gate capacity can be reduced and the driving capability of the amplifier circuit part is reduced, and the ripple removal rate is also improved. Can be high. In addition, the capacitance of the phase compensation capacitor connected to the output transistor can be reduced, and the size of the capacitor can also be reduced. In addition, the current detection resistor and the comparator connected in series with the output transistor, which are required in the past, are not required, and the circuit scale can be reduced. As a result, the chip size can be reduced and the cost can be reduced. be able to.

  In addition, since the output current value from each output transistor is limited, the output current can be shared with a more accurate current.

It is the figure which showed the circuit example of the constant voltage circuit in the 1st Embodiment of this invention. FIG. 2 is a diagram illustrating an operation example of the constant voltage circuit 1 of FIG. 1. It is the figure which showed the circuit example of the constant voltage circuit in the 2nd Embodiment of this invention. FIG. 4 is a diagram illustrating an operation example of the constant voltage circuit 1a of FIG.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a constant voltage circuit according to the first embodiment of the present invention.
In FIG. 1, a constant voltage circuit 1 is a series regulator that converts an input voltage Vin input from a DC power supply 10 to an input terminal IN into a predetermined constant voltage and outputs the voltage as an output voltage Vout from an output terminal OUT.
The constant voltage circuit 1 includes first and second output transistors M1 and M2, a reference voltage generation circuit 2 that generates and outputs a predetermined reference voltage Vref, and output voltage detection resistors R1 and R2. The dynamic amplifying circuit 3, first and second amplifying circuits 4 and 5, an output capacitor Co, phase compensation resistors R3 and R4, and phase compensation capacitors C3 and C4 are included.

The differential amplifier circuit 3 includes NMOS transistors M11 and M12, PMOS transistors M13 and M14, and a constant current source 11 that supplies a predetermined bias current i1. The first amplifier circuit 4 includes a PMOS transistor M15 and a constant current source 12 that supplies a predetermined constant current i2, and the second amplifier circuit 5 supplies a PMOS transistor M16 and a predetermined constant current i3. A constant current source 13 is used.
The reference voltage generating circuit 2, the differential amplifier circuit 3, and the resistors R1 and R2 form a differential amplifier circuit section, and the first and second amplifier circuits 4 and 5 each form an amplifier circuit section. Further, in the constant voltage circuit 1 of FIG. 1, each circuit except the output capacitor Co may be integrated in one IC. In some cases, the first and second output transistors M1, M2 and the output capacitor Each circuit except Co may be integrated in one IC.

  The first and second output transistors M1 and M2 are connected in parallel between the input terminal IN and the output terminal OUT, and the output capacitor Co is connected between the output terminal OUT and the ground voltage GND. Resistors R1 and R2 are connected in series. The resistors R1 and R2 divide the output voltage Vout to generate and output a feedback voltage Vfb. A series circuit of a resistor R3 and a capacitor C3 is connected between the gate and drain of the first output transistor M1, and a resistor R4 and a capacitor C4 are connected between the gate and drain of the second output transistor M2. A series circuit is connected.

  In the differential amplifier circuit 3, the sources of NMOS transistors M11 and M12 forming a differential pair are connected, and a constant current source 11 is connected between the connection portion and the ground voltage GND. The reference voltage Vref is input to the gate of the NMOS transistor M11, and the feedback voltage Vfb is input to the gate of the NMOS transistor M12. The PMOS transistors M13 and M14 form a current mirror circuit and form a load of the differential pair. In the PMOS transistors M13 and M14, each source is connected to the input voltage Vin, and each gate is connected to the PMOS transistor. Connected to the drain of M13. The drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M11, the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M12, and the connection between the PMOS transistor M14 and the NMOS transistor M12 is connected to the output terminal of the differential amplifier circuit 3. There is no.

The first amplifier circuit 4 is a grounded source amplifier circuit. In the first amplifier circuit 4, the source of the PMOS transistor M15 is connected to the input voltage Vin, and the gate of the PMOS transistor M15 is connected to the differential amplifier circuit 3. Connected to the output end of the. The constant current source 12 is connected between the drain of the PMOS transistor M15 and the ground voltage GND, and the connection between the PMOS transistor M15 and the constant current source 12 forms the output terminal of the first amplifier circuit 4, and the output terminal is Are connected to the gate of the first output transistor M1.
Similarly, the second amplifier circuit 5 is a grounded source amplifier circuit. In the second amplifier circuit 5, the source of the PMOS transistor M16 is connected to the input voltage Vin, and the gate of the PMOS transistor M16 is differential. The amplifier 3 is connected to the output terminal. A constant current source 13 is connected between the drain of the PMOS transistor M16 and the ground voltage GND, and a connection portion between the PMOS transistor M16 and the constant current source 13 forms an output terminal of the second amplifier circuit 5, and the output terminal is , Connected to the gate of the second output transistor M2.

  In such a configuration, the differential amplifier circuit 3 amplifies the voltage difference between the reference voltage Vref and the feedback voltage Vfb, generates a voltage Va, and outputs the voltage Va to the first and second amplifier circuits 4 and 5, respectively. . The first amplifier circuit 4 amplifies the input voltage Va and outputs it to the gate of the first output transistor M1, and the second amplifier circuit 5 amplifies the input voltage Va and outputs a second output. The current output from each of the first and second output transistors M1 and M2 is controlled so that the feedback voltage Vfb becomes the reference voltage Vref by outputting to the gate of the transistor M2. The threshold voltages Vth1 and Vth2 of the first and second output transistors M1 and M2 are the same, and the threshold voltage Vth15 of the PMOS transistor M15 is larger than the threshold voltage Vth16 of the PMOS transistor M16. Is set to a value.

  FIG. 2 is a diagram illustrating an operation example of the constant voltage circuit 1 of FIG. 1, and the operation of the constant voltage circuit 1 of FIG. 1 will be described with reference to FIG. In FIGS. 1 and 2, the gate voltage of the first output transistor M1 is Vg1, the drain current of the first output transistor M1 is io1, the gate voltage of the second output transistor M2 is Vg2, and the second The drain current of the output transistor M2 is io2. That is, the output current io output from the output terminal OUT is (io1 + io2). Further, Vth1 is the threshold voltage of the first output transistor M1, Vth2 is the threshold voltage of the second output transistor M2, Vth15 is the threshold voltage of the PMOS transistor M15, and Vth16 is the threshold voltage of the PMOS transistor M16. Each threshold voltage is shown, and imax1 shows the maximum allowable current value of the first output transistor M1. FIG. 2 shows an example in which the maximum value of the output current io is 200 mA, and the maximum allowable currents of the first and second output transistors M1 and M2 are both 100 mA. Is the voltage and current, and the horizontal axis is the output current io.

  Further, although the threshold voltages of the first output transistor M1 and the second output transistor M2 are smaller than those of the PMOS transistor M16 in FIG. 2, the first and second output transistors M1 and M2 respectively. Are not particularly related to the threshold voltages Vth15 and Vth16 of the PMOS transistors M15 and M16, and the thresholds of the first and second output transistors M1 and M2 are not particularly related. The value voltages Vth1 and Vth2 may be larger than the threshold voltage Vth15 of the PMOS transistor M15, or may be between the threshold voltages Vth15 and Vth16 of the PMOS transistors M15 and M16.

  When the output current io is as small as 1 mA or less, the output voltage Va of the differential amplifier circuit 3 is slightly smaller than the threshold voltage Vth15 of the PMOS transistor M15. Therefore, the PMOS transistor M15 is on, and the gate voltage Vg1 that forms the drain voltage of the PMOS transistor M15 is near the threshold voltage Vth1 of the first output transistor M1. At this time, since the PMOS transistor M16 is completely turned on, the drain voltage of the PMOS transistor M16 has risen to nearly the input voltage Vin, so that the second output transistor M2 is turned off and becomes a cut-off state. ing.

  As the output current io increases, the voltage Va gradually increases. Then, since the gate-source voltage of the PMOS transistor M15 becomes small, the drain current of the PMOS transistor M15 decreases. As the drain current of the PMOS transistor M15 decreases, the drain voltage of the PMOS transistor M15, that is, the gate voltage Vg1 of the first output transistor M1 decreases, so the drain current io1 of the first output transistor M1 increases. However, when the drain current io1 is less than about 100 mA, since the output voltage Va of the differential amplifier circuit 3 is equal to or lower than the threshold voltage Vth16 of the PMOS transistor M16, the PMOS transistor M16 is on, The drain current io2 of the output transistor M2 does not flow yet. That is, in the region where the output current io is less than about 100 mA, the output current io is all supplied from the first output transistor M1.

  When the output current io becomes about 100 mA, the output voltage of the first amplifier circuit 4, that is, the gate voltage Vg1 of the first output transistor M1 saturates at a level close to the ground voltage GND, and does not decrease below this. That is, the drain current io1 of the first output transistor M1 does not increase any more. However, with such an output current io, the output voltage Va of the differential amplifier circuit 3 rises to the threshold voltage Vth16 of the PMOS transistor M16, so the drain current of the PMOS transistor M16 begins to decrease, and the drain of the PMOS transistor M16 The voltage, that is, the gate voltage Vg2 of the second output transistor M2 starts to decrease, and the drain current io2 starts to flow through the second output transistor M2.

When the output current io exceeds 100 mA, the drain current io2 of the second output transistor M2 increases, and the output current io is supplied from both the first and second output transistors M1 and M2.
When the output current io reaches 200 mA, the output voltage of the second amplifier circuit 5, that is, the gate voltage Vg2 of the second output transistor M2 is saturated and decreases to near the ground voltage GND, and the drain of the second output transistor M2 The current io2 does not increase any more.

  As described above, in the constant voltage circuit according to the first embodiment, the threshold voltage Vth15 of the PMOS transistor M15 is larger than the threshold voltage Vth16 of the PMOS transistor M16, and the output current io is small. When the output current io is supplied from the first output transistor M1 and the gate voltage Vg1 of the first output transistor M1 is saturated, the second output transistor M2 is activated. For this reason, since the maximum output current per output transistor can be made smaller than the maximum output current of the constant voltage circuit, a small output transistor can be used, and the gate capacity of the output transistor is also reduced. Since it can be reduced, the required response speed can be ensured and the ripple removal rate can be increased even if the driving capability of the amplifier circuit is reduced.

Further, since the capacitances of the phase compensation capacitors C3 and C4 can be reduced, the size of each capacitor can also be reduced. Furthermore, a current detection resistor and a comparator connected in series with the output transistor are not required, and the circuit scale can be reduced. As a result, the chip size can be reduced and the cost can be reduced.
The difference in threshold voltage between the PMOS transistors M15 and M16 can be realized by changing the ratio between the gate width W and the gate length L in the PMOS transistors M15 and M16, and the ratio between the gate width W and the gate length L is the same. Thus, it can be realized by changing the values of the constant currents i2 and i3, or changing both the ratio of the gate width W and the gate length L and the values of the constant currents i2 and i3.

  In the first embodiment, the maximum allowable currents of the first output transistor M1 and the second output transistor M2 are both set to 100 mA. However, it is not always necessary to set the same value. The maximum allowable current of the output transistor M1 may be set to 50 mA, and the maximum allowable current of the second output transistor M2 may be set to 150 mA.

Second embodiment.
The constant voltage circuit in the first embodiment may be provided with a current limiting circuit for limiting the current output from each output transistor, and such a configuration is used in the second embodiment of the present invention. And
FIG. 3 is a diagram illustrating a circuit example of a constant voltage circuit according to the second embodiment of the present invention. In FIG. 3, the same or similar parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted here, and only differences from FIG. 1 will be described.
3 is different from FIG. 1 in that the first and second current limiting circuits 21 and 22 are added to FIG. 1, and accordingly, the constant voltage circuit 1 of FIG. 1 is replaced with the constant voltage circuit 1a. I made it.

In FIG. 3, the constant voltage circuit 1a forms a series regulator that converts the input voltage Vin input from the DC power supply 10 to the input terminal IN into a predetermined constant voltage and outputs the voltage from the output terminal OUT as the output voltage Vout.
The constant voltage circuit 1a includes first and second output transistors M1 and M2, a reference voltage generation circuit 2, output voltage detection resistors R1 and R2, a differential amplifier circuit 3, and first and second output transistors M1 and M2. Amplifier circuits 4 and 5, output capacitor Co, phase compensation resistors R 3 and R 4, phase compensation capacitors C 3 and C 4, and first and second current limiting circuits 21 and 22. ing.

  Each of the first and second current limiting circuits 21 and 22 forms a current limiting circuit unit. Further, in the constant voltage circuit 1a of FIG. 3, each circuit other than the output capacitor Co may be integrated in one IC. In some cases, the first and second output transistors M1, M2 and the output capacitor Each circuit except Co may be integrated in one IC.

The first current limiting circuit 21 is a circuit that limits the current io1 output from the first output transistor M1, and includes PMOS transistors M21 and M22, NMOS transistors M23 and M24, and a resistor Rs1.
Similarly, the second current limiting circuit 22 is a circuit that limits the current io2 output from the second output transistor M2, and includes PMOS transistors M25 and M26, NMOS transistors M27 and M28, and a resistor Rs2. Yes.
In the first current limiting circuit 21, the source of the PMOS transistor M21 is connected to the input voltage Vin, and the gate of the PMOS transistor M21 is connected to the output terminal of the first amplifier circuit 4, that is, the gate of the first output transistor M1. ing.

  The NMOS transistors M23 and M24 form a current mirror circuit. In the NMOS transistors M23 and M24, each source is connected to the ground voltage GND, each gate is connected, and the connection portion is connected to the drain of the NMOS transistor M23. Has been. The drain of the NMOS transistor M23 is connected to the drain of the PMOS transistor M21, and a resistor Rs1 is connected between the input voltage Vin and the drain of the NMOS transistor M24. A PMOS transistor M22 is connected between the input voltage Vin and the gate of the first output transistor M1, and the gate of the PMOS transistor M22 is connected to the drain of the NMOS transistor M24.

  Similarly, in the second current limiting circuit 22, the source of the PMOS transistor M25 is connected to the input voltage Vin, and the gate of the PMOS transistor M25 is the output terminal of the second amplifier circuit 5, that is, the gate of the second output transistor M2. It is connected to the. The NMOS transistors M27 and M28 form a current mirror circuit. In the NMOS transistors M27 and M28, each source is connected to the ground voltage GND, each gate is connected, and the connection portion is connected to the drain of the NMOS transistor M27. Has been. The drain of the NMOS transistor M27 is connected to the drain of the PMOS transistor M25, and a resistor Rs2 is connected between the input voltage Vin and the drain of the NMOS transistor M28. A PMOS transistor M26 is connected between the input voltage Vin and the gate of the second output transistor M2, and the gate of the PMOS transistor M26 is connected to the drain of the NMOS transistor M28.

In such a configuration, the operation of the first and second current limiting circuits 21 and 22 is the same as that of the constant voltage circuit 1 of FIG. 1 except for the first and second current limiting circuits 21 and 22. Will be described.
The drain current io21 proportional to the output current io1 from the first output transistor M1 flows through the PMOS transistor M21. The drain current io21 is supplied to the resistor Rs1 after the direction of the current is turned back by a current mirror circuit composed of NMOS transistors M23 and M24, and the voltage difference between both ends of the resistor Rs1 increases as the output current io increases. When the voltage at the connection between the NMOS transistor M24 and the resistor Rs1 reaches the threshold voltage of the PMOS transistor M22, the impedance of the PMOS transistor M22 decreases, and the decrease in the gate voltage Vg1 of the first output transistor M1 is suppressed. .

  FIG. 4 is a diagram showing an operation example of the constant voltage circuit 1a of FIG. 3. The conditions and symbols in FIG. 4 are the same as those in FIG. As shown in FIG. 4, the gate voltage Vg1 remains at a voltage at which the output current of the first output transistor M1 maintains 100 mA and does not decrease below that. For this reason, the output current io1 output from the first output transistor M1 is limited to 100 mA, which is a limit current value. The threshold voltage of the PMOS transistor M16 is set to be substantially equal to the output voltage Va of the differential amplifier circuit 3 when the current limit for the first output transistor M1 is activated. For this reason, when the current limit is applied to the first output transistor M1, the second output transistor M2 operates and the output current io2 is supplied from the second output transistor M2.

In the PMOS transistor M25, a drain current io25 proportional to the output current io2 from the second output transistor M2 flows. The drain current io25 is supplied to the resistor Rs2 by turning the direction of the current in a current mirror circuit composed of NMOS transistors M27 and M28, and the voltage difference between both ends of the resistor Rs2 increases as the output current io increases. When the voltage at the connection between the NMOS transistor M28 and the resistor Rs2 reaches the threshold voltage of the PMOS transistor M26, the impedance of the PMOS transistor M26 decreases, and the decrease in the gate voltage Vg2 of the second output transistor M2 is suppressed. .
For this reason, when the output current io reaches 200 mA, the second current limiting circuit 22 limits the current to the second output transistor M2 and protects the output current io from exceeding 200 mA.

  As described above, in the constant voltage circuit according to the second embodiment, the current limiting circuit corresponding to each of the first and second output transistors M1 and M2 is different from the constant voltage circuit according to the first embodiment. Thus, the same effect as that of the first embodiment can be obtained, and the output current can be distributed to the first and second output transistors with a more accurate current. Can be made.

In the description of the second embodiment, the current limit values of the first output transistor M1 and the second output transistor M2 are both set to 100 mA. However, this is an example. For example, the first output transistor The current limit value of M1 may be changed to 50 mA, and the current limit value of the second output transistor M2 may be changed to 150 mA.
In each of the first and second embodiments, the case where two amplifier circuits and two output transistors are provided has been described as an example. However, this is an example, and the present invention includes a plurality of output transistors and a plurality of output transistors. This is applied when a plurality of amplifier circuits are provided corresponding to each output transistor.

1, 1a constant voltage circuit 2 reference voltage generation circuit 3 differential amplifier circuit 4 first amplifier circuit 5 second amplifier circuit 10 DC power supply 21 first current limiting circuit 22 second current limiting circuit M1 first output Transistor M2 Second output transistor R1-R4 Resistor Co Output capacitor C3, C4 Capacitor

Japanese Utility Model Publication No. 3-17811 JP-A-11-143558

Claims (12)

In the constant voltage circuit that converts the input voltage input from the input terminal to a predetermined voltage and outputs it as an output voltage from the output terminal,
A plurality of output transistors for controlling the output voltage by outputting a current according to a control signal input to the control electrode from the input terminal to the output terminal;
A differential amplifier circuit unit that amplifies and outputs a voltage difference between a predetermined reference voltage and a feedback voltage proportional to the output voltage;
Amplifying circuit portions provided corresponding to the output transistors for amplifying the output voltage of the differential amplifier circuit portion and outputting the amplified output voltage to the control electrodes of the corresponding output transistors;
With
Each of the amplifying circuit units operates by sequentially turning on the corresponding output transistors in a predetermined order in accordance with an input voltage from the differential amplifying circuit unit.   2. The constant voltage circuit according to claim 1, wherein each of the output transistors is formed so that a sum of currents that are turned on and output is equal to or less than a predetermined maximum value.   Each of the amplifier circuit sections is a source-grounded amplifier circuit having a MOS transistor for controlling the voltage of the control electrode of the corresponding output transistor, and the threshold voltages of the MOS transistors have different values. The MOS transistors are formed so that the corresponding output transistors are turned on and operated in a predetermined order in accordance with an input voltage from the differential amplifier circuit unit. 3. The constant voltage circuit according to 1 or 2.   The MOS transistor of the amplifier circuit section that turns on the output transistor corresponding to the (n + 1) th (n is a positive integer) is saturated with the output voltage of the amplifier circuit section that turns on the output transistor corresponding to the nth 4. The constant voltage circuit according to claim 3, wherein the threshold voltage is set so as to be the same voltage as the output voltage of the differential amplifier circuit section when the voltage is applied.   Corresponding to each output transistor is a current limiting circuit that limits the output current from the output transistor so that the output current output from the corresponding output transistor is less than or equal to the corresponding maximum allowable current value. The constant voltage circuit according to claim 3, wherein each of the constant voltage circuits is provided.   The MOS transistor of the amplifier circuit section that turns on the output transistor corresponding to the (n + 1) th is an output of the differential amplifier circuit section when the output transistor that operates nth reaches the maximum allowable current value. 6. The constant voltage circuit according to claim 5, wherein a threshold voltage is set so as to be the same voltage as the voltage.   7. The constant voltage circuit according to claim 3, wherein the threshold voltage of each of the MOS transistors of each amplifier circuit section is set by changing a ratio of a gate width to a gate length.   7. The constant voltage circuit according to claim 3, wherein the MOS transistor of each amplifier circuit section has a threshold voltage set by changing a current value supplied to a drain.   5. The threshold voltage of each of the MOS transistors of each amplifier circuit section is set by changing a ratio of a gate width to a gate length and a current value supplied to a drain, respectively. 5. The constant voltage circuit according to 5 or 6. A feedback voltage proportional to the output voltage, comprising a plurality of output transistors for controlling the output voltage output from the output terminal by outputting a current corresponding to the control signal input to the control electrode from the input terminal to the output terminal. A constant voltage circuit that controls the operation of each of the output transistors so that the voltage becomes a predetermined reference voltage, converts the input voltage input from the input terminal into a predetermined voltage, and outputs the voltage as the output voltage from the output terminal In the operation control method of
When the output current output from the output terminal reaches the maximum allowable current value of the output transistor turned on first, the second output transistor is maintained while maintaining the maximum allowable current from the output transistor turned on first. And
Hereinafter, when the output current exceeds the sum of the maximum allowable currents in the first to nth (n is a positive integer) output transistors in the turn-on order, the currents from the first to nth output transistors While maintaining each maximum allowable current, operating the (n + 1) th output transistor,
An operation control method for a constant voltage circuit, wherein the output transistors are sequentially turned on to operate in a predetermined order as the output current increases.   11. The operation control method for a constant voltage circuit according to claim 10, wherein operation control of each output transistor is performed so that a sum of currents output from each output transistor is not more than a predetermined maximum value.   The output current value from each output transistor is limited so that each output current output from each output transistor is less than or equal to a corresponding maximum allowable current value. An operation control method for a constant voltage circuit according to 10 or 11.

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