JP2008543046A - Trench-type metal oxide semiconductor field effect transistor - Google Patents

Abstract

  A trench cell type or closed cell type trench type metal oxide semiconductor field effect transistor (TMOSFET) is provided. A stripe cell type or closed cell type TMOSFET has a source region, a body region disposed above the source region, a drift region disposed above the body region, and a drain region disposed above the drift region. The gate region is disposed above the source region and adjacent to the body region. A gate insulator region electrically insulates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region.

Description

  Embodiments of the present invention relate to metal oxide semiconductor field effect transistors (MOSFETs), and more specifically to vertical MOSFET devices having a trench gate structure. A drain side gate trench MOSFET (TMOSFET) is described.

  Referring to FIG. 1, a perspective cross-sectional view of a TMOSFET 100 having a striped trench according to the prior art is shown. The striped TMOSFET 100 includes a plurality of source contacts 110, a plurality of source regions 115, a plurality of gate regions 120, a plurality of gate insulator regions 125, a plurality of body regions 130, drain regions 135 and 140, and a drain contact 145. is doing. The drain regions 135 and 140 include a first drain portion 140 and a second drain portion 135 as required.

  Body region 130 is arranged above drain regions 135 and 140. The source region 115, the gate region 120, and the gate insulator region 125 are disposed in the body region 130. The gate region 120 and the gate insulator region 125 are formed as parallel elongated structures. Gate insulator region 125 surrounds gate region 120. Therefore, the gate region 120 is electrically isolated from the surrounding region by the gate insulator region 125. Gate region group 120 is coupled to form a common gate for device 100. Source region group 115 is coupled by source contact 110 to form a common source for device 100. Although source contact 110 is illustrated as a plurality of individual source contacts 110, it will be appreciated that source contact 110 may be provided as a single conductive layer that couples all source regions 115. Source contact 110 also couples source region 115 to body region 130.

  Source region 115 and drain region 140 are highly n-type doped (N +) semiconductors, such as silicon doped with phosphorus or arsenic. The body region 130 is a p-type doped (P-type) semiconductor, such as silicon doped with boron. The gate region 120 is a heavily n-type doped (N +) semiconductor, such as polysilicon doped with phosphorus. The gate insulator region 125 is an insulator such as silicon dioxide.

  When the potential of the gate region 120 relative to the source region 115 is raised above the threshold voltage of the device 100, a conductive channel is generated along the outer periphery of the gate insulator region 125 in the body region 130. The stripe TMOSFET 100 conducts current between the drain region 140 and the source region 115. Therefore, the device 100 is turned on.

  When the potential of the gate region 120 is lowered below the threshold voltage, the channel is no longer generated. As a result, the voltage applied between the drain region 140 and the source region 115 does not pass current between them. Therefore, the device 100 is turned off, and the junction formed by the body region 130 and the drain region 140 supports the applied voltage between the source and the drain.

  When the drain regions 135, 140 have a second drain portion 135 disposed on the first drain portion 140, the second portion 135 of the drain region is n lightly doped, such as silicon doped with phosphorus or arsenic. The first portion 140 of the drain region is a highly n-type doped (N +) semiconductor, such as silicon doped with phosphorus or arsenic, for example. The second portion 135 of the lightly n-doped (N-type) drain region provides a depletion region that extends into both the body region 130 and the second portion 135 of the drain region, thereby punch-through. The effect is suppressed. Accordingly, the second portion 135 of the lightly doped n-type (N− type) drain region serves to increase the breakdown voltage of the stripe TMOSFET 100.

  The channel width of the striped TMOSFET 100 is a function of the length of the plurality of source regions 115. Therefore, the striped TMOSFET 100 provides a large channel width to length ratio. Therefore, the striped TMOSFET can be advantageously used for power MOSFET applications such as a switching element in a pulse width modulation (PWM) voltage regulator.

  Referring to FIG. 2, a perspective cross-sectional view of a TMOSFET 200 having a closed cell type trench according to the prior art is shown. The closed cell type TMOSFET 200 includes a plurality of source contacts 210, a plurality of source regions 215, a gate region 220, a gate insulator region 225, a plurality of body regions 230, drain regions 235 and 240, and a drain contact 245. . The drain regions 235 and 240 include a first drain portion 240 and a second drain portion 235 as necessary.

  The body region 230, the source region 215, the gate region 220, and the gate insulator region 225 are disposed above the drain regions 235 and 240. The first portions of the gate region 220 and the gate insulator region 225 are formed as elongated structures 221 that are substantially parallel. The second portion of the gate region 220 and the gate insulator region 225 is formed as a substantially vertical, parallel elongated structure 222. The first portion and the second portion of the gate region 220 are all connected to each other to form a plurality of cells. Body region 230 is disposed in a plurality of cells formed by gate region 220.

  A gate insulator region 225 surrounds the gate region 220. Thus, the gate region 220 is electrically isolated from the surrounding region by the gate insulator region 225. The source region 215 is disposed in the plurality of cells along the outer periphery of the gate insulator region 225.

  Source region group 215 is coupled by source contact 210 to form a common source for device 200. Although source contact 210 is illustrated as a plurality of individual source contacts 210, as will be appreciated, source contact 210 may include a plurality of conductive strips, each strip joining a plurality of source regions 215, or all It may be provided as a single conductive layer or the like that couples the source region 215. Source contact 210 also couples source region 215 to body region 230.

  Source region 215 and drain region 240 are highly n-type doped (N +) semiconductors, such as silicon doped with phosphorus or arsenic. The body region 230 is a p-type doped (P-type) semiconductor, such as silicon doped with boron. The gate region 220 is a highly n-doped (N +) semiconductor, such as polysilicon doped with phosphorus. The gate insulator region 225 is an insulator such as silicon dioxide.

  When the potential of the gate region 220 relative to the source region 215 is raised above the threshold voltage of the device 200, a conductive channel is generated in the body region 230 along the outer periphery of the gate insulator region 225. Device 200 then conducts current between drain region 240 and source region 215. Therefore, the device 200 is turned on.

  When the potential of the gate region 220 is lowered below the threshold voltage, the channel is no longer generated. As a result, the voltage applied between the drain region 240 and the source region 215 does not pass current between them. Therefore, the device 200 is turned off, and the junction formed by the body region 230 and the drain region 240 supports the applied voltage between the source and the drain.

  If the drain regions 235, 240 have a second drain portion 235 disposed on the first drain portion 240, the second portion 235 of the drain region is n lightly doped, such as silicon doped with phosphorus or arsenic. The first portion 240 of the drain region is a highly n-type doped (N +) semiconductor, such as silicon doped with phosphorus, for example. The second portion 235 of the lightly n-doped (N-type) drain region provides a depletion region extending within both the body region 230 and the second portion 235 of the drain region, thereby punch-through. The effect is suppressed. Therefore, the second portion 235 of the lightly doped n-type (N− type) drain region serves to increase the breakdown voltage of the closed cell TMOSFET 200.

  The channel width of the closed cell type TMOSFET 200 is a function of the total width of the source region group 215. Therefore, the closed cell type TMOSFET 200 increases the width of the channel region in a geometrically advantageous manner as compared with the stripe type TMOSFET 100. Therefore, the closed cell type TMOSFET 200 has a lower channel resistance (for example, on-resistance) than the stripe type TMOSFET 100. This low channel resistance makes the power dissipated in the closed cell TMOSFET 200 less than the power dissipated in the striped TMOSFET 100.

  Similarly, the gate-drain capacitance (hereinafter referred to as gate-drain capacitance) of the closed cell type TMOSFET 200 is a function of the area where the bottom of the gate region 220 and the drain region 240 overlap. Therefore, the structure of the closed cell type TMOSFET 200 has a problem in that it has a larger gate-drain capacity than the stripe type TMOSFET 100. A large gate-drain capacitance compared to the striped TMOSFET 100 limits the switching speed of the closed cell TMOSFET 200.

  Embodiments of the present invention provide a stripe-cell or closed-cell trench-type metal oxide semiconductor field effect transistor (TMOSFET) having a reduced gate-drain capacitance while having an on-resistance equivalent to that of the prior art. For the purpose.

  A trench-type metal oxide semiconductor field effect transistor (TMOSFET) provided in accordance with an embodiment of the present invention has a gate region and a drain region on the same side, while a source region is disposed on the opposite side. ing.

  A stripe cell type or closed cell type TMOSFET provided according to an embodiment of the present invention includes a source region, a body region disposed above the source region, a drift region disposed above the body region, and a drift region. A drain region is disposed above. The gate region is disposed above the source region and adjacent to the body region. A gate insulator region electrically insulates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region.

  In addition, a method of manufacturing a stripe-type or closed-cell type TMOSFET provided according to an embodiment of the present invention includes growing a p-type doped epitaxial silicon layer on an n-type doped silicon substrate, and the p-type doping. And growing an n-type doped epitaxial silicon layer on the formed silicon layer. These epitaxially grown silicon layers and a portion of the substrate are selectively etched to form a set of trenches. The silicon adjacent to the trench is oxidized to form a gate oxide region. The first portion of the trench is filled with polysilicon and the remaining portion of the trench is filled with dielectric. N-type impurities are implanted so as to form a drift region and a drain region. P-type impurities are implanted so as to form the body region of the N-channel MOSFET.

  The invention is illustrated by way of example and not limitation by the figures shown in the accompanying drawings. In the drawings, like reference numerals refer to similar elements.

  Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in connection with these embodiments, it will be understood that the invention is not limited to these embodiments. The invention, on the contrary, is intended to cover modifications, improvements and equivalents falling within the scope of the invention as defined by the appended claims. In the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

  Referring to FIG. 3, a perspective cross-sectional view of a stripe cell type trench type metal oxide semiconductor field effect transistor (TMOSFET) 300 according to an embodiment of the present invention is shown. The stripe cell type TMOSFET 300 includes a source contact 310, a source region 315, a plurality of gate regions 320, a plurality of gate insulator regions 325, a plurality of body regions 330, a plurality of drift regions 335, a plurality of drain regions 340, and a drain contact 345. have. The striped TMOSFET 300 may further include a first source-body contact region 350, a second source-body contact region 355, and a source-body contact insulator region 360.

  The plurality of gate regions 320, the plurality of gate insulator regions 325, the plurality of body regions 330, the plurality of drift regions 335, and the plurality of drain regions 340 are disposed above the source region 315. The gate region 320 and the gate insulator region 325 are formed as substantially parallel elongated structures. The body region 330 is disposed between the parallel elongated structures formed by the gate region 320 and the gate insulator region 325 above the source region 315. Drift region 335 is disposed above body region 330 and between parallel elongated structures formed by gate region 320 and gate insulator region 325. Drain region 340 is disposed above drift region 335 and between parallel elongated structures formed by gate region 320 and gate insulator region 325.

  Gate region 320 is surrounded by a corresponding gate insulator region 325. Thus, the gate region 320 is electrically isolated from the surrounding regions (eg, source region 315, body region 330, drift region 335, drain region 340, and drain contact 345) by the gate insulator region 325. Although not shown, the gate region groups 320 are connected to each other (eg, by gate contacts in the peripheral region of the device). The plurality of drain regions 340 are coupled by drain contacts 345 to form a common drain for the device. As can be recognized from the above description, the stripe-type TMOSFET 300 has the gate region 320 and the drain region 340 on substantially the same side.

  In one embodiment, source region 315 and drain region 340 are heavily n-type doped (N +) semiconductors, such as silicon doped with phosphorus or arsenic. The body region 330 is a p-type doped (P-type) semiconductor, such as silicon doped with boron. The drift region 335 is a lightly n-type doped (N-type) semiconductor, such as silicon doped with phosphorus or arsenic. The gate region 320 is heavily n-doped (N +) semiconductor, such as phosphorous or arsenic doped polysilicon, or heavily p-doped, such as boron doped polysilicon. (P + type) semiconductor. The gate insulator region 325 is an oxide such as silicon dioxide.

  In another embodiment, source region 315 and drain region 340 are heavily p-doped (P +) semiconductors, such as silicon doped with boron. The body region 330 is a lightly n-type doped (N-type) semiconductor, such as silicon doped with phosphorus or arsenic. The drift region 335 is a lightly p-type doped (P-type) semiconductor, such as silicon doped with boron. The gate region 320 is heavily n-doped (N +) semiconductor, such as phosphorous or arsenic doped polysilicon, or heavily p-doped, such as boron doped polysilicon. (P + type) semiconductor. The gate insulator region 325 is an oxide such as silicon dioxide.

  Body region 330 is electrically coupled to source region 315. In one embodiment, body region 330 is coupled to source region 315 by first and second source-body contact regions 350,355. The second source-body contact region 355 is a silicide such as tungsten silicide. The first source-body contact region 350 is a heavily p-doped (P +) semiconductor, such as silicon doped with boron. Source-body contact regions 350, 355 are electrically isolated from surrounding regions (eg, drift region 335) by source-body contact insulator region 360. In one embodiment, the source-body contact insulator region 360 is an oxide such as silicon dioxide. In another embodiment, the source-body contact insulator region 360 may be p-type doped polysilicon, silicon nitride, or the like.

  When the potential of the gate region 320 relative to the source region 315 is raised above the threshold voltage of the device 300, a conductive channel is generated along the outer periphery of the gate insulator region 325 in the body region 330. The device 300 then conducts current between the plurality of drain regions 340 and the source region 315. Therefore, the device 300 is turned on. When the potential of the plurality of gate regions 320 is lowered below the threshold voltage, the channel is no longer generated. As a result, the voltage applied between the plurality of drain regions 340 and the source region 315 does not pass current between them. Accordingly, the device 300 is turned off and the junction formed by the body region 330 and the drift region 335 supports the voltage applied between the source region 315 and the drain region 340.

  The channel width is a function of the total length of the drain region group 340. Therefore, the width of the channel region is substantially equal to that of the conventional stripe cell type TMOSFET 100. Therefore, the on-resistance (Rds-on) of the device 300 is substantially equal to that of the conventional stripe cell type TMOSFET 100.

  In conventional stripe cell type TMOSFETs, lead wires are used to connect the source on the die to an external device. The source leads increase the effective source inductance in the conventional stripe cell TMOSFET 100. The source of the stripe cell type TMOSFET 300 according to the present invention can be directly connected to a PCB or a conventional stripe cell type TMOSFET (for example, the source contact covers the bottom surface of the die, which is soldered to the PCB or the like with a wave solder) Can be attached). The source lead can be eliminated, thus reducing the effective source inductance.

  The stripe cell type TMOSFET 300 can be manufactured such that the gate region 320 does not overlap the drain region 340. Therefore, the separation distance between the gate region 320 and the drain region 340 is increased. Accordingly, the gate-drain capacitance (Cgd) can be substantially reduced as compared with the conventional stripe cell type TMOSFET 100. For example, in one embodiment, the gate region substantially overlaps the body region and does not substantially overlap the drift region or drain region.

  Furthermore, the stripe cell TMOSFET 300 has a relatively large gate-source capacitance (Cgs) as a result of the overlap of the gate region 320 with the source region 315. Therefore, the gate-source capacitance (Cgs) of the stripe cell type TMOSFET 300 according to the present invention is generally larger than the gate-source capacitance (Cgs) of the conventional stripe cell type TMOSFET 100. Accordingly, the ratio of the gate-drain capacitance (Cgd), which is a figure of merit, to the gate-source capacity (Cgs) is smaller in the stripe cell type TMOSFET 300 according to the present invention than in the conventional stripe cell type TMOSFET 100 (good figure of merit). Have). It will also be appreciated that the ratio of gate-drain capacitance (Cgd) to gate-source capacitance (Cgs) is such that the portion of the gate oxide region 325 proximate to the source region 315 and / or the gate proximate to the drain region 340. It may be adjusted by adjusting the thickness of the portion of the insulator region 325.

  The overlap of the gate region 320 and the drift region 335 increases the accumulation in the conductive channel when the device 300 is in the on state. Thus, when the gate region 320 extends so as to overlap the body region 330 and the drift region 335, the on-resistance (Rds-on) of the stripe cell type TMOSFET 300 according to the present invention can be further reduced.

  With continued reference to FIG. 4, a perspective cross-sectional view of a stripe cell type trench metal oxide semiconductor field effect transistor (TMOSFET) 400 according to another embodiment of the present invention is shown. The stripe cell type TMOSFET 400 is the same as that described with reference to FIG. 3 except that a plurality of super source regions 365 are added. Super source region 365 is formed as a substantially parallel elongated structure disposed above gate region 320. The gate insulator region 325 also surrounds the super source region 365, and the super source region 365 is surrounded by surrounding regions (eg, the gate region 320, the body region 330, the drift region 335, the drain region 340, and the drain contact 345). It is electrically insulated.

  Although not shown, the super source region 365 is electrically coupled to the source region 315 (eg, by a contact in the outer peripheral region). The super source region 365 is adapted to reduce the resistance in the on state (Rds-on) and increase the breakdown voltage in the off state.

  Also, the drain contact 345 is shown substantially cut away so that the stripe cell structure is illustrated in detail. However, as will be appreciated, the drain contact 345 covers the surface of the central region of the stripe cell TMOSFET 400.

  With continued reference to FIGS. 5A-5D, a flow diagram of a method of manufacturing a stripe cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention is shown. A method of manufacturing a striped cell TMOSFET according to an embodiment of the present invention is also illustrated in FIGS. 6A-6O. As shown in FIGS. 5A and 6A, the process begins at step 502 with various initial steps, such as cleaning, deposition, doping, etching, etc. on the substrate 502 '. In one embodiment, the substrate 502 'comprises (N +) silicon heavily doped with phosphorus. As will be appreciated, the semiconductor substrate 502 'will substantially constitute the source region of the TMOSFET upon completion of this manufacturing process.

  In step 504, a first semiconductor layer 504 'is epitaxially grown on the substrate 502'. In one embodiment, the first semiconductor layer 504 'comprises p-type doped (P-type) silicon. Epitaxially grown silicon can be doped by introducing desired impurities such as boron into the epitaxial reaction chamber. In another example, the doping of the first semiconductor layer 504 'may be realized by high energy implantation (ion implantation) using a p-type dopant such as boron.

  In step 506, a second semiconductor layer 506 'is epitaxially grown on the first semiconductor layer 504'. In one embodiment, the second semiconductor layer 506 'comprises lightly p-doped (P-type) silicon. The epitaxially grown silicon can be doped by introducing desired impurities, such as boron, into the reaction chamber. In another example, the doping of the second semiconductor layer 506 'may be realized by high energy implantation using a p-type dopant such as boron.

  A sacrificial oxide layer 508 ′ is formed on the second semiconductor layer 506 ′ in step 508 as necessary. In one embodiment, the sacrificial oxide layer 508 'is formed by oxidizing the surface of the second semiconductor layer 506'. In step 510, a photoresist is deposited and patterned by any known lithographic process to form a gate trench resist layer 510 '.

  In step 512, the exposed portions of the sacrificial oxide layer 508 ′, the second semiconductor layer 506 ′, the first semiconductor layer 504 ′, and a portion of the substrate 502 ′ are formed using any known anisotropic etching method (eg, Etching is performed by dry etching. In one embodiment, an ionic etchant interacts with the sacrificial oxide layer 508 ′, the second semiconductor layer 506 ′, the first semiconductor layer 504 ′, and the substrate 502 ′ exposed by the gate trench resist layer 510 ′. . By this etching process, a plurality of first trenches 512 'are formed as a substantially parallel structure.

  At step 514, the gate trench resist layer 510 'is removed using a suitable resist strip or resist ashing process. At step 516, a dielectric layer 516 'is formed along the plurality of first trenches 512'. In one embodiment, dielectric layer 516 'is formed by oxidizing the exposed surface of silicon to form a silicon dioxide layer. The resulting dielectric layer 516 'along the trench walls forms a first portion of the gate insulator region.

At step 518, a polysilicon layer is deposited in the plurality of first trenches 512 ′. In one embodiment, the polysilicon is deposited in the trench 512 ′ by a method such as, for example, decomposition of silane (SiH ₄ ). The polysilicon is doped with an n-type impurity such as phosphorus or arsenic. This polysilicon can be doped by introducing impurities during the deposition process. At step 520, an etch back process is performed to remove excess polysilicon material to form gate region 520 '. The polysilicon layer is etched back to obtain the desired spacing / overlap between the gate region formed from the polysilicon layer in the trench and the body, drift and drain regions to be formed later. In one embodiment, excess polysilicon is removed by a combination of a chemical mechanical polishing (CMP) process and an anisotropic etching method.

  In one embodiment selected as needed, a dielectric layer is formed over the gate region 520 '. In one embodiment, the polysilicon in the gate region 512 'is oxidized to form a silicon dioxide layer. A second polysilicon layer is deposited on the dielectric layer formed over the gate region 520 '. Another etch back process is used to form a super source region from the second polysilicon layer.

  As shown in FIGS. 5B and 6E, at step 522, a dielectric layer is deposited in the plurality of first trenches 512 '. In one embodiment, the dielectric is deposited in the trench by a method such as, for example, tetraethylorthosilicate (TEOS) decomposition, or high density plasma filling (HDP). At step 524, excess dielectric is removed to complete the gate insulator region 524 '. In one embodiment, excess dielectric is removed by a chemical mechanical polishing (CMP) process.

  In step 526, the first semiconductor layer 504 'is p-type doped to adjust the doping concentration to form a body region 526' between the plurality of first trenches 512 '. In one embodiment, the doping process implants (implants) a p-type impurity 527 ', such as boron, into the first semiconductor layer 504'. In step 528, a thermal cycle is used to push (eg, diffuse) the implanted impurities substantially throughout the depth of the first semiconductor layer 504 ′, thereby forming a body region 526 ′. . In step 530, the second semiconductor layer 506 'is n-doped. In one embodiment, this doping process implants an n-type impurity 531 'such as phosphorus or arsenic into the second semiconductor layer 506'. In step 532, a thermal cycle is used to push (eg, diffuse) the implanted impurities into substantially the entire depth of the second semiconductor layer 506 '. In step 534, the upper portion of the second semiconductor layer 506 ′ is heavily n-doped, and the drain region 534 ′ above the second semiconductor layer 506 ′ and the lower drift between the plurality of first trenches 512 ′. Region 530 'is formed. In one embodiment, the doping process implants an n-type impurity 533 ', such as phosphorus or arsenic, on top of the second semiconductor layer 506'. In step 536, a third thermal cycle may be used to force this third implanted impurity to achieve the desired depth of drain region 534 '.

  In step 538, as necessary, a second sacrificial oxide layer 538 'is formed on the wafer. In one embodiment, the sacrificial oxide layer 538 'is formed by oxidizing the wafer surface. In step 542, a photoresist is deposited and patterned by any known lithography process to form a source-body contact trench resist layer 542 '.

  As shown in FIGS. 5C and 6J, in step 544, the exposed portions of the second sacrificial oxide layer 538 ′, the drain region 534 ′, and the drift region 530 ′ are etched by any known anisotropic etching method. Is done. In one embodiment, an ionic etchant interacts with the sacrificial oxide layer 538 ', drain region 534', and drift region 530 'exposed by the source-body contact trench resist layer 542'. This etching process forms a plurality of substantially parallel second trenches 544 '. Each of the plurality of second trenches 544 'is disposed between each of the plurality of first trenches 512'.

  In step 546, the exposed body region 526 'is heavily p-doped to form a first source-body contact 546'. In one embodiment, this doping process implants a p-type impurity 545 ', such as boron, into the body region 526'. Thermal cycling may be used to push the source-body implanted impurities substantially over the exposed portion of the body region 526 '. As will be appreciated, some of the implanted impurities diffuse laterally into the unexposed portions of body region 526 ', the exposed portions of which are adjacent.

  At step 548, the source-body contact trench resist layer 542 'is removed using a suitable resist strip or resist ashing process. At step 550, a dielectric layer 550 'is formed along the plurality of second trenches 544'. In one embodiment, dielectric layer 550 'is formed by oxidizing the exposed surface of silicon to form a silicon dioxide layer.

  At step 552, the dielectric formed at the bottom of the plurality of second trenches 544 'and the exposed portions of the body region 526' are etched by any well-known anisotropic etching method. This etching process is performed until the plurality of second trenches 552 'extends partially into the source region 502' (eg, the substrate). This etching process exposes adjacent portions of the body region 526 ′ and the source region 502 ′, while the drift region 530 ′ and drain region remain protected by the dielectric layer 550 ′ along the sidewalls. . As will be appreciated, the portion of the source-body contact implant impurity that diffused laterally into the unexposed portion of the body region 526 'remains substantially left after this etching process. The remaining portion of the source-body contact implantation impurity forms the first source-body contact.

  In step 554, a first metal layer 554 'is deposited on the bottom of the plurality of second trenches 552', and this metal layer 554 'is reacted with the source region 502' and the body region 526 '. In one embodiment, titanium is sputtered and subjected to rapid thermal annealing (RTA) to form titanium silicide (TiSi) along the exposed portions of source region 502 'and body region 526'. The titanium silicide forms a second source-body contact 556 ', which combines with the first source-body contact 546' to form the body region 526 'as the source region 502. 'Electrically coupled to. At step 556, unreacted portions of metal along the walls of the source-body trench lined with dielectric are etched.

  At step 558, a second dielectric is deposited in the plurality of second trenches 552 'to form source-body insulator regions 560'. In one embodiment, the dielectric is deposited in the trench by a method such as, for example, tetraethylorthosilicate (TEOS) decomposition, or high density plasma filling (HDP).

  In step 564, a photoresist is deposited and patterned by any known lithography process to form a gate contact resist layer (not shown). The gate contact is formed in a peripheral region (not shown). At step 566, the exposed portion of gate insulator 524 'is etched by any known anisotropic etching method (not shown). In one embodiment, an ionic etchant interacts with the gate oxide exposed by the gate contact resist layer. A gate contact opening extends to the underlying gate 520 '. In step 568, the gate contact resist layer is removed using a suitable resist stripping or resist ashing process (not shown).

  In step 570, a photoresist is deposited and patterned by any known lithography process to form a drain contact resist layer (not shown). At step 572, the exposed portion of the third sacrificial oxide is etched (not shown) by any known anisotropic etching method. In one embodiment, an ionic etchant interacts with the third sacrificial oxide and excess second dielectric material to form a drain contact opening. The drain contact opening extends to the underlying drain region. In step 574, the drain contact resist layer is removed using a suitable resist stripping or resist ashing process.

  At step 576, a second metal layer is deposited on the wafer. In one embodiment, the second metal layer, for example aluminum, is deposited by any known method such as sputtering. The second metal layer covers the top of drain region 534 ', gate insulator 524' and source-body contact insulator 560 '. The second metal layer extends into the gate contact opening and makes electrical contact with the gate 520 ', and extends into the drain contact opening and makes electrical contact with the drain. Thereafter, in step 578, the second metal layer is patterned using a photoresist mask and selective etching to form a gate contact layer (not shown) and a drain contact layer 578 '.

  At step 584, various backside fabrication processes are continued to form source contacts. These various processes generally include etching, deposition, doping, cleaning, annealing, passivation, cutting, and the like.

  With continued reference to FIG. 7, a perspective cross-sectional view of a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) 700 in accordance with one embodiment of the present invention is shown. The closed cell type TMOSFET 700 includes a source contact 710, a source region 715, a gate region 720, a gate insulator region 725, a plurality of body regions 730, a plurality of drift regions 735, a plurality of drain regions 740, and a drain contact 745. Yes. The closed cell TMOSFET 700 may further include a plurality of first source-body contact regions 750, a plurality of second source-body contact regions 755, and a plurality of source-body contact insulator regions 760. .

  The gate region 720, the gate insulator region 725, the plurality of body regions 730, the plurality of drift regions 735, and the plurality of drain regions 740 are disposed above the source region 715. The first portion of the gate region 720 and the gate insulator region 725 is formed as a substantially parallel elongated structure. The second portion of the gate region 720 and the gate insulator region 725 is formed as a substantially vertical, parallel elongated structure (eg, the second portion of the gate region and the gate insulator region within the surface of the wafer). Has a plurality of substantially parallel elongated structures formed perpendicular to the gate region and the first portion of the gate insulator region). The first portion and the second portion of the gate region 720 are all connected to each other to form a plurality of cells. Body region 730 is disposed in the plurality of cells above source region 715. The drift region 735 is disposed in the plurality of cells above the body region 330. The drain region 740 is disposed in the plurality of cells above the drift region 735. The drain contact 745 is shown substantially cut away so that a closed cell structure is illustrated in detail. However, as will be appreciated, the drain contact 745 covers the entire surface of the central region.

  Gate region 720 is surrounded by a gate insulator region 725. Thus, the gate region 720 is electrically isolated from the surrounding regions (eg, source region 715, body region 730, drift region 735, drain region 740 and drain contact 745) by the gate insulator region 725. The plurality of drain regions 740 are coupled by a drain contact 745 to form a common drain of the device. As will be appreciated from the above description, the closed cell type TMOSFET 700 has its gate terminal and drain terminal on the same surface side.

  In one embodiment, source region 715 and drain region 740 are heavily n-type doped (N +) semiconductors, such as silicon doped with phosphorus or arsenic. The body region 730 is a p-type doped (P-type) semiconductor, such as silicon doped with boron. The drift region 735 is a lightly n-type doped (N-type) semiconductor, such as silicon doped with phosphorus or arsenic. Gate region 720 is heavily n-type doped (N +) semiconductor, such as polysilicon doped with phosphorus or arsenic, or heavily p-type doped, eg, polysilicon doped with boron. (P + type) semiconductor. The gate insulator region 725 is an oxide such as silicon dioxide.

  In another embodiment, source region 715 and drain region 740 are heavily p-type doped (P +) semiconductors, such as silicon doped with boron. The body region 730 is a lightly n-type doped (N-type) semiconductor, such as silicon doped with phosphorus or arsenic. The drift region 735 is a lightly p-type doped (P-type) semiconductor, such as silicon doped with boron. The gate region 720 is heavily n-type doped, such as heavily p-type doped (P +) semiconductor, eg, boron doped polysilicon, or polysilicon, eg, doped with phosphorus or arsenic. (N + type) semiconductor. The gate insulator region 725 is an oxide such as silicon dioxide.

  Body region 730 is electrically coupled to source region 715. In one embodiment, body region 730 is coupled to source region 715 by first and second source-body contact regions 750, 755. The second source-body contact region 755 is silicide such as tungsten silicide. The first source-body contact region 750 is a highly p-doped (P +) semiconductor, such as silicon doped with boron. Source-body contact regions 750 and 755 are electrically isolated from surrounding drift region 735 by source-body contact insulator region 760. In one embodiment, the source-body contact insulator region 760 is an oxide such as silicon dioxide. In another embodiment, the source-body contact insulator region 760 may be p-type doped polysilicon, silicon nitride, or the like. Source-body contact regions 750 and 755 and source-body insulator region 760 are formed substantially in the center of each cell. The front corners of this cross-sectional view are cut to show the structure of the source-body contact regions 750, 755 and the source-body insulator region 760 in detail.

  When the potential of the gate region 720 relative to the source region 715 is raised above the threshold voltage of the device 700, a conductive channel is generated in the body region 730 along the periphery of the gate insulator region 725. Device 700 then conducts current between a plurality of drain regions 740 and source regions 715. Therefore, the device 700 is turned on. When the potential of the plurality of gate regions 720 is lowered below the threshold voltage, the channel is no longer generated. As a result, the voltage applied between the plurality of drain regions 740 and the source region 715 does not pass current between them. Thus, device 700 is turned off and the junction formed by body region 730 and drift region 735 supports the voltage applied between source region 715 and drain region 740.

  The channel width is a function of the total perimeter of the drain region group 740 adjacent to the gate insulator region 725. Therefore, the width of the channel region is substantially equal to that of the conventional closed cell type TMOSFET 200. Thus, the on-resistance (Rds-on) of device 700 is substantially equal to that of conventional closed cell TMOSFET 200.

  In conventional closed cell TMOSFET 200, leads are used to connect the source on the die to an external device. The source leads increase the effective source inductance in the conventional closed cell TMOSFET 200. The source of the closed cell TMOSFET 700 according to the present invention can be directly connected to a PCB or a conventional closed cell TMOSFET 200 (eg, the source contact covers the bottom of the die, which is soldered to the PCB etc. with a wave solder) Can be attached). The source lead can be eliminated, thus reducing the effective source inductance of the closed cell TMOSFET 700 according to the present invention.

  The closed cell TMOSFET 700 can be manufactured such that the gate region 720 does not overlap the drain region 740. Therefore, the distance between the gate region 720 and the drain region 740 is increased. By increasing the separation distance, the gate-drain capacitance (Cgd) is reduced. Therefore, the gate-drain capacitance (Cgd) of the closed cell type TMOSFET 700 according to the present invention is reduced as compared with that of the conventional closed cell type TMOSFET 200.

  Further, the closed cell TMOSFET 700 has a relatively large gate-source capacitance (Cgs) as a result of the overlap of the gate region 720 with the source region 715. Therefore, the gate-source capacitance (Cgs) of the closed cell type TMOSFET 700 according to the present invention is generally larger than the gate-source capacitance (Cgs) of the conventional closed cell type TMOSFET 200. Accordingly, the ratio of the gate-drain capacitance (Cgd), which is a figure of merit, to the gate-source capacity (Cgs) is smaller in the closed cell type TMOSFET 700 according to the present invention than in the conventional closed cell type TMOSFET 200 (good figure of merit). Have). It will also be appreciated that the ratio of gate-drain capacitance (Cgd) to gate-source capacitance (Cgs) is such that the portion of the gate insulator region 725 proximate the source region 715 and / or the gate proximate to the drain region 740. It may be adjusted by adjusting the thickness of the portion of the insulator region 725.

  The overlap of the gate region 720 and the drift region 735 increases the accumulation in the conductive channel when the device 700 is on. Thus, when the gate region 720 extends so as to overlap the body region 730 and the drift region 735, the on-resistance (Rds-on) of the closed cell TMOSFET 700 according to the present invention can be further reduced.

  Although not shown, as will also be appreciated, the closed cell TMOSFET 700 may further include a super source region. The super source region is formed as a substantially parallel elongated structure disposed above the gate region 720. The gate insulator region 725 also surrounds the super source region and electrically isolates the super source region from surrounding regions (eg, gate region 720, body region 730, drift region 735, drain region 740, and drain contact 745). To do. The super source region is electrically coupled to the source region 715 (eg, by a contact in the outer peripheral region). The super source region is adapted to further reduce the on-state resistance (Rds-on) of the closed-cell TMOSFET 700 and increase the breakdown voltage in the off state.

  With continued reference to FIGS. 8A-8D, a flow diagram of a method of fabricating a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) according to one embodiment of the present invention is shown. A method of manufacturing a closed cell TMOSFET according to an embodiment of the present invention is also illustrated in FIGS. 9A-9N. As shown in FIGS. 8A and 9A, the process begins at step 802 with various initial steps such as cleaning, deposition, doping, etching, etc., on the substrate 802 '. In one embodiment, the substrate 802 'comprises (N +) silicon heavily doped with phosphorus. The semiconductor substrate 802 'will substantially constitute the source region of the TMOSFET upon completion of this manufacturing process.

  In step 804, a first semiconductor layer 804 'is epitaxially grown on the substrate 802'. In one embodiment, the first semiconductor layer 804 'is comprised of heavily p-doped (P +) silicon. Epitaxially grown silicon can be doped by introducing desired impurities such as boron into the epitaxial reaction chamber. In another example, the doping of the first semiconductor layer may be realized by high energy implantation (ion implantation) using a p-type dopant such as boron.

  In step 806, a second semiconductor layer 806 'is epitaxially grown on the first semiconductor layer 804'. In one embodiment, the second semiconductor layer 806 'comprises n-type doped (N-type) silicon. Epitaxially grown silicon can be doped by introducing desired impurities such as phosphorus or arsenic into the reaction chamber. In another example, doping of the second semiconductor layer may be achieved by high energy implantation using an n-type dopant such as phosphorus or arsenic.

  In step 808, as necessary, a first sacrificial oxide layer 808 'is formed on the second semiconductor layer 806'. In one embodiment, the sacrificial oxide layer 808 'is formed by oxidizing the surface of the second semiconductor layer 806'. In step 810, a photoresist is deposited and patterned by any known lithographic process to form a gate trench resist layer 810 '.

  In step 812, the exposed portions of the sacrificial oxide layer 808 ′, the second semiconductor layer 806 ′, the first semiconductor layer 804 ′, and a portion of the substrate 802 ′ are formed by any known anisotropic etching method (eg, Etching is performed by dry etching. In one embodiment, an ionic etchant interacts with the sacrificial oxide layer 808 ′, the second semiconductor layer 806 ′, the first semiconductor layer 804 ′, and the substrate 802 ′ exposed by the gate trench resist layer 810 ′. . By this etching process, a plurality of trenches 812 'having a plurality of cells disposed therein are obtained. The plurality of trenches 812 ′ are formed to have a first portion having a substantially parallel structure and a second portion having a parallel structure substantially perpendicular thereto.

  At step 814, the gate trench resist layer 810 'is removed using a suitable resist strip or resist ashing process. In step 816, a first dielectric layer 816 'is formed along the plurality of trenches 812'. In one embodiment, the first dielectric layer 816 'is formed by oxidizing the exposed surface of silicon to form a silicon dioxide layer. The dielectric 816 'obtained along the trench wall forms the first part of the gate insulator region.

At step 818, a polysilicon layer 820 ′ is deposited in the plurality of trenches 812 ′. In one embodiment, polysilicon 820 ′ is deposited in trench 812 ′ by a method such as, for example, decomposition of silane (SiH ₄ ). The polysilicon may be doped with n-type impurities such as phosphorus or arsenic. This polysilicon can be doped by introducing impurities during the deposition process. At step 820, an etch back process is performed to remove excess polysilicon material and form a gate region. The polysilicon layer is etched back to obtain the desired spacing / overlap between the gate region formed from the polysilicon layer in the trench and the body, drift and drain regions to be formed later. In one embodiment, excess polysilicon is removed by a combination of a chemical mechanical polishing (CMP) process and an anisotropic etching method.

  In one embodiment, selected as needed, a dielectric layer is formed on the gate. In one embodiment, the gate polysilicon is oxidized to form a silicon dioxide layer. A second polysilicon layer is deposited on the dielectric layer formed on the gate. Another etch back process is used to form a supersource from the second polysilicon layer.

  As shown in FIGS. 8B and 9E, at step 822, a second dielectric 824 'is deposited in the plurality of trenches 812'. In one embodiment, the dielectric is deposited in the trench by a method such as, for example, tetraethylorthosilicate (TEOS) decomposition, or high density plasma filling (HDP). At step 824, excess dielectric is removed and the gate insulator region is completed. In one embodiment, excess dielectric is removed by a chemical mechanical polishing (CMP) process.

  In step 826, the first semiconductor layer 804 'is p-type doped to adjust the doping concentration of the body region 826' between the plurality of trenches 812 '. In one embodiment, the doping process implants (implants) a p-type impurity 827 ', such as boron, into the first semiconductor layer 804'. At step 828, a thermal cycle is used to push (eg, diffuse) the implanted impurities substantially throughout the depth of the first semiconductor layer 804 ', thereby forming a body region 826'. . At step 830, the second semiconductor layer 806 'is n-doped. In one embodiment, the doping process implants an n-type impurity 831 'such as phosphorous or arsenic into the second semiconductor layer 806'. At step 832, a thermal cycle is used to push (eg, diffuse) the implanted impurities into substantially the entire depth of the second semiconductor layer 806 '. In step 834, the upper portion of the second semiconductor layer 806 ′ is heavily n-type doped, and the drain region 834 ′ above the second semiconductor layer 806 ′ and the lower drift region 830 ′ are interposed between the plurality of trenches 812 ′. And are formed. In one embodiment, the doping process implants an n-type impurity 833 ', such as phosphorus or arsenic, on top of the second semiconductor layer 806'. In step 836, a third thermal cycle may be used to push the implanted impurity into the drain region to achieve the desired depth of drain region 834 '.

  In step 838, a second sacrificial oxide layer 838 'is formed on the wafer. In one embodiment, the second sacrificial oxide layer 838 'is formed by oxidizing the wafer surface. In step 840, a photoresist is deposited and patterned by any known lithography process to form a source-body contact opening resist layer 840 '.

  As shown in FIGS. 8C and 9J, in step 842, the exposed portions of the second sacrificial oxide layer 838 ′, the drain region 834 ′, and the drift region 830 ′ are etched by any known anisotropic etching method. Is done. In one embodiment, an ionic etchant interacts with the sacrificial oxide layer 838 ', drain region 834' and drift region 830 'exposed by the source-body contact opening resist layer 840'. By this etching process, a plurality of source-body contact openings 842 'are formed. Each source-body contact opening 842 'is disposed in a cell formed by a plurality of trenches 812'.

  In step 844, the exposed portion of body region 826 'is heavily doped to form first source-body contact region 844'. In one embodiment, the doping process implants a p-type impurity 843 ', such as boron, into the body region 826'. Thermal cycling may be used to force the source-body implanted impurities into substantially the entire exposed portion of body region 826 '. As will be appreciated, some of the implanted impurities diffuse laterally into the unexposed portions of body region 826 ', the exposed portions of which are adjacent.

  At step 846, the source-body contact opening resist layer 840 'is removed using a suitable resist strip or resist ashing process. At step 848, a dielectric 848 'is formed along the source-body contact opening 842'. In one embodiment, the dielectric 848 'is formed by oxidizing the exposed surface of silicon to form a silicon dioxide layer.

  At step 850, the dielectric 848 'formed at the bottom of the source-body contact opening 842' and the exposed portion of the body region 826 'are etched by any known anisotropic etching method. This etching process is performed until the source-body contact opening 850 'extends partially into the source region 802' (e.g., the substrate). This etching process exposes adjacent portions of body region 826 'and source region 802', while drift region 830 'and drain region 834' remain protected by dielectric layer 848 '. As will be appreciated, the portion of the source-body contact implant impurity 844 'that has diffused laterally into the unexposed portion of the body region 826' remains substantially left after this etching process. The remaining portion of the source-body contact implantation impurity forms the first source-body contact 844 '.

  In step 852, a first metal 852 'is deposited at the bottom of the source-body contact opening 850', and this metal 852 'is reacted with the exposed body region 826' and source region 802 '. In one example, titanium is sputtered into the opening and subjected to rapid thermal annealing (RTA) to form titanium silicide (TiSi). The titanium silicide forms a second source-body contact 854 ′, which is combined with the first source-body contact to make the body region 826 ′ a source region 802 ′. Connect electrically. At step 854, unreacted portions of titanium along the walls of the source-body contact opening 850 'lined with dielectric are etched away.

  In step 856, a third dielectric is deposited in the source-body contact opening 850 'to form a source-body insulator region 856'. In one embodiment, the dielectric 856 'is deposited in the opening 850' by methods such as, for example, tetraethylorthosilicate (TEOS) decomposition, or high density plasma filling (HDP).

  In step 862, a photoresist is deposited and patterned by any known lithography process to form a gate contact resist layer (not shown). The gate contact is formed in a peripheral region (not shown). As shown in FIG. 8D, at step 864, the exposed portion of gate insulator region 824 'is etched by any known anisotropic etching method to form a gate contact in the peripheral region (not shown). In one embodiment, an ionic etchant interacts with the gate oxide exposed by the gate contact resist layer. A gate contact opening extends to the underlying gate region 820 '. At step 866, the gate contact resist layer is removed using a suitable resist strip or resist ashing process.

  In step 868, a photoresist is deposited and patterned by any known lithography process to form a drain contact resist layer (not shown). At step 870, the excess dielectric material in the central region and the exposed portion of the third sacrificial oxide are etched by any known anisotropic etching method to form drain contact openings (not shown). In one embodiment, an ionic etchant interacts with excess dielectric material and a third sacrificial oxide to form a drain contact opening. The drain contact opening extends to the underlying drain region 834 '. In step 872, the drain contact resist layer is removed using a suitable resist stripping or resist ashing process (not shown).

  At step 874, a second metal layer is deposited on the wafer. In one embodiment, the second metal layer, for example aluminum, is deposited by any known method such as sputtering. This metal layer covers the top of drain region 834 ', gate insulator region 824' and source-body contact insulator region 856 '. The second metal layer extends into the gate contact opening and makes electrical contact with the gate region, and extends into the drain contact opening and makes electrical contact with the drain region 834 '. Thereafter, in step 876, the second metal layer is patterned using a photoresist mask and selective etching to form a gate contact layer (not shown) and a drain contact layer 876 '.

  At step 882, various backside fabrication processes are continued to form source contacts. These various processes generally include etching, deposition, doping, cleaning, annealing, passivation, cutting, and the like.

  With continued reference to FIGS. 10A-10D, a flow diagram of a method of fabricating a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) according to another embodiment of the present invention is shown. . A method of manufacturing a closed cell TMOSFET according to another embodiment of the present invention is also illustrated in FIGS. 11A-11O. As shown in FIGS. 10A and 11A, the process begins at step 1002 with various initial steps such as cleaning, deposition, doping, etching, etc. on the substrate 1002 '. In one example, the substrate 1002 'comprises (N +) silicon heavily doped with phosphorus. The semiconductor substrate 1002 'will substantially constitute the source region of the TMOSFET upon completion of this manufacturing process.

  In step 1004, a first semiconductor layer 1004 'is epitaxially grown on the substrate 1002'. In one embodiment, the first semiconductor layer 1004 'is comprised of heavily p-doped (P +) silicon. Epitaxially grown silicon can be doped by introducing desired impurities such as boron into the epitaxial reaction chamber. In another example, the doping of the first semiconductor layer 1004 'may be realized by high energy implantation (ion implantation) using a p-type dopant such as boron.

  In step 1006, a second semiconductor layer 1006 'is epitaxially grown on the first semiconductor layer 1004'. In one embodiment, the second semiconductor layer comprises lightly n-type doped (N-type) silicon. Epitaxially grown silicon can be doped by introducing desired impurities such as phosphorus or arsenic into the reaction chamber. In another example, the doping of the second semiconductor layer 1006 'may be realized by high energy implantation using an n-type dopant such as phosphorus or arsenic.

  Step 1008 forms a first sacrificial oxide layer 1008 'on the second semiconductor layer 1006'. In one embodiment, the sacrificial oxide layer 1008 'is formed by oxidizing the surface of the second semiconductor layer 1006'. In step 1010, a photoresist is deposited and patterned by any known lithography process to form a gate trench resist layer 1010 '.

  In step 1012, exposed portions of the first sacrificial oxide layer 1008 ′, the second semiconductor layer 1006 ′, the first semiconductor layer 1004 ′, and a portion of the substrate 1002 ′ are subjected to some known anisotropic etching method. Etching is performed by (for example, dry etching). In one embodiment, an ionic etchant interacts with the sacrificial oxide layer 1008 ′, the second semiconductor layer 1006 ′, the first semiconductor layer 1004 ′, and the substrate 1002 ′ exposed by the gate trench resist layer 1010 ′. . A plurality of trenches 1012 'are formed having a first portion with a substantially parallel structure and a second portion with a parallel structure substantially perpendicular thereto.

  In step 1014, the gate trench resist layer 1010 'is removed using a suitable resist stripping or resist ashing process. In step 1016, a first dielectric layer 1016 'is formed along the plurality of trenches 1012'. In one embodiment, dielectric layer 1016 'is formed by oxidizing the exposed surface of silicon to form a silicon dioxide layer. The resulting dielectric layer 1016 'along the trench wall forms the first portion of the gate insulator region.

At step 1018, a first polysilicon layer is deposited in the plurality of trenches. In one embodiment, the polysilicon is deposited in the trench by a method such as decomposition of silane (SiH ₄ ). The polysilicon may be doped with n-type impurities such as phosphorus or arsenic. This polysilicon can be doped by introducing impurities during the deposition process. At step 1020, an etch back process is performed to remove excess polysilicon material to form gate region 1020 ′. This polysilicon layer is etched back to obtain the desired spacing / overlap between the gate region formed from the polysilicon layer in the trench and the body, drift and drain regions to be formed later. . In one embodiment, excess polysilicon is removed by a combination of a chemical mechanical polishing (CMP) process and an anisotropic etching method.

  With continued reference to FIGS. 10B and 11E, a second dielectric layer 1022 'is formed over the gate region 1020' in step 1022 as required. In one embodiment, the polysilicon of gate 1020 'is oxidized to form a silicon dioxide layer. A second polysilicon layer is deposited on the dielectric layer 1022 'formed on the gate 1020' at step 1024, if desired. An etch back process is used once again to form a super source region 1026 'from the second polysilicon layer at step 1026, as needed.

  At step 1028, a third dielectric is deposited in the plurality of trenches 1012 '. In one embodiment, the dielectric is deposited using a quasi-atmospheric chemical vapor deposition (SACVD) process. At step 1030, excess dielectric material is removed to complete the gate insulator region 1030 '. In one embodiment, excess dielectric material is removed by a chemical mechanical polishing (CMP) process.

  In step 1032, the lower portion of the second semiconductor layer 1006 'is doped with p-type impurities. In one embodiment, this doping process implants (implants) a p-type impurity 1032 ', such as boron, into the lower portion of the second semiconductor layer 1006'. In step 1034 as necessary, a thermal cycle is used to push the implanted impurities, thereby forming a body region 1035 '. As will be appreciated, this thermal cycling can occur in the first semiconductor layer 1004 ′ such that the body region 1035 ′ is formed substantially from the first semiconductor layer 1004 ′ and the lower portion of the second semiconductor layer 1006 ′. The impurity and the impurity implanted by the step 1032 in the lower part of the second semiconductor layer 1006 ′ are diffused.

  In step 1036, the upper portion of the second semiconductor layer 1006 'is n-type doped to adjust the doping concentration of the drift region 1036'. In one embodiment, the doping process implants an n-type impurity 1037 ', such as phosphorus or arsenic, on top of the second semiconductor layer 1006'. In step 1038, as required, a second thermal cycle is used to force (eg, diffuse) the implanted second impurity, thereby forming a drift region 1036 '.

  Step 1042 forms a second sacrificial oxide layer 1042 'on the wafer. In one embodiment, the sacrificial oxide layer is formed by oxidizing the wafer surface. As shown in FIGS. 10C and 11H, at step 1046, a photoresist is deposited and patterned by any known lithographic process to form a source-body contact opening resist layer 1046 '.

  At step 1048, the exposed portions of the second sacrificial oxide layer 1042 'and the drift region 1036' are etched by any known anisotropic etching method. In one embodiment, an ionic etchant interacts with the second sacrificial oxide layer 1042 'and the drift region 1036' exposed by the source-body contact opening resist layer 1046 '. This etching process forms a plurality of source-body contact openings 1048 '. Each source-body contact opening is disposed within a cell formed by a plurality of trenches 1012 '.

  In step 1050, the exposed body region is heavily p-doped to form source-body implant region 1050 '. In one embodiment, the doping process implants a p-type impurity 1049 ', such as boron, into the body region 1035'. Thermal cycling may be used to push the source-body implanted impurities into substantially the entire exposed portion of body region 1035 '. As will be appreciated, some of the source-body implanted impurities diffuse laterally into the unexposed portions of the body region 1035 ', the exposed portions of which are adjacent.

  In step 1052, the source-body contact opening resist layer 1046 'is removed using a suitable resist strip or resist ashing process. In step 1054, a fourth dielectric layer 1054 'is formed along the source-body contact opening 1048'. In one embodiment, dielectric layer 1054 'is formed by oxidizing the exposed surface of silicon to form a silicon dioxide layer.

  In step 1056, the portion of dielectric layer 1054 'formed at the bottom of source-body contact opening 1048' and the exposed portion of body region 1035 'are etched by any well-known anisotropic etching method. This etching process is performed until the source-body contact opening 1056 'extends partially into the substrate 1002'. This etching process exposes adjacent portions of body region 1035 'and source region 1002', while drift region 1036 'remains protected by dielectric layer 1054'. As will be appreciated, the portion of the source-body contact implant impurity that diffused laterally into the unexposed portion of the body region 1035 'remains substantially left after this etching process. The remaining portion of the source-body contact implantation impurity forms a first source-body contact 1050 '.

  In step 1058, a first metal layer 1060 'is deposited on the bottom of the source-body contact opening 1056', which is reacted with the exposed body region 1035 'and the substrate 1002'. In one example, titanium is sputtered into the opening and subjected to rapid thermal annealing (RTA) to form titanium silicide (TiSi). The titanium silicide forms a second source-body contact 1060 ′, which is combined with the first source-body contact 1050 ′ to form a body region 1035 ′ as a substrate region 1002. 'Electrically coupled to. At step 1060, unreacted portions of titanium along the walls of the source-body contact openings lined with dielectric are etched away. Step 1062 deposits a fifth dielectric layer in the source-body contact opening to form a source-body insulator region 1064 '. In one embodiment, the dielectric layer is deposited in the source-body contact opening 1056 'using a quasi-atmospheric chemical vapor deposition (SACVD) process.

  As shown in FIG. 10D, at step 1068, a photoresist is deposited and patterned by any known lithographic process to form a gate contact resist layer (not shown). The gate contact is formed in a peripheral region (not shown). At step 1070, the exposed portion of the fifth dielectric layer and gate insulator region 1030 'is etched (not shown) by any known anisotropic etching method. In one embodiment, an ionic etchant interacts with the gate oxide exposed by the gate contact resist layer. A gate contact opening extends to the underlying gate region 1020 '. In step 1072, the gate contact resist layer is removed using a suitable resist stripping or resist ashing process (not shown).

  In step 1074, a photoresist is deposited and patterned by any known lithography process to form a drain contact resist layer (not shown). At step 1076, the exposed portion of the fifth dielectric layer is etched by any known anisotropic etching method. In one embodiment, an ionic etchant interacts with the fifth dielectric layer to form a drain contact opening. The drain contact opening extends to the underlying drift region 1036 '. In step 1078, the upper portion of the drift region is heavily n-doped to form a drain region. In step 1080, if necessary, a third thermal cycle is used to push (eg, diffuse) the implanted impurities to achieve the desired depth of drain region 1080 '. In step 1082, the drain contact resist layer is removed using a suitable resist stripping or resist ashing process.

  At step 1084, a second metal layer is deposited on the wafer. In one embodiment, the second metal layer, for example aluminum, is deposited by any known method such as sputtering. This metal layer covers the top of the drain region, the gate oxide and the source-body contact oxide region and is in electrical contact with the drain region. The second metal layer also extends into the gate contact opening and makes electrical contact with the gate region. Thereafter, in step 1086, the metal layer is patterned using a photoresist mask and a selective etching method to form a gate contact layer (not shown) and a drain contact layer 1086 '.

  At step 1088, various backside fabrication processes are continued to form source contacts. These various processes generally include etching, deposition, doping, cleaning, annealing, passivation, cutting, and the like.

  The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration. These are not exhaustive and do not limit the invention to the precise forms disclosed. Obviously, many modifications and variations may be made in light of the above teachings. The foregoing embodiments best illustrate the principles of the invention and its practical application, thereby besting the invention and various embodiments with various modifications suitable for the specific application intended by those skilled in the art. It is selected and described so that it can be used. The scope of the present invention is defined by the appended claims and their equivalents.

It is a perspective view which shows the cross section of stripe type TMOSFET according to a prior art. It is a perspective view which shows the cross section of the closed cell type | mold TMOSFET according to a prior art. It is a perspective view which shows the cross section of the stripe cell type | mold TMOSFET according to one Embodiment of this invention. It is a perspective view which shows the cross section of the stripe cell type | mold TMOSFET according to other one Embodiment of this invention. It is a flowchart which shows the manufacturing method of stripe cell type TMOSFET according to one Embodiment of this invention. It is a flowchart which shows the manufacturing method of stripe cell type TMOSFET according to one Embodiment of this invention. It is a flowchart which shows the manufacturing method of stripe cell type TMOSFET according to one Embodiment of this invention. It is a flowchart which shows the manufacturing method of stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of the stripe cell type TMOSFET according to one Embodiment of this invention. It is a perspective view which shows the cross section of the closed cell type | mold TMOSFET according to one Embodiment of this invention. It is a flow figure showing a manufacturing method of closed cell type TMOSFET according to one embodiment of the present invention. It is a flow figure showing a manufacturing method of closed cell type TMOSFET according to one embodiment of the present invention. It is a flow figure showing a manufacturing method of closed cell type TMOSFET according to one embodiment of the present invention. It is a flowchart which shows the manufacturing method of closed cell type TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture step of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is sectional drawing which shows one manufacture stage of closed cell type | mold TMOSFET according to one Embodiment of this invention. It is a flowchart which shows the manufacturing method of the closed cell type TMOSFET according to other one Embodiment of this invention. It is a flowchart which shows the manufacturing method of the closed cell type TMOSFET according to other one Embodiment of this invention. It is a flowchart which shows the manufacturing method of the closed cell type TMOSFET according to other one Embodiment of this invention. It is a flowchart which shows the manufacturing method of the closed cell type TMOSFET according to other one Embodiment of this invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing one manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing stage of a closed cell TMOSFET according to another embodiment of the present invention.

Claims (39)

Source area;
A plurality of gate regions disposed above the source region and formed as substantially parallel elongated structures;
A plurality of gate insulator regions, each of which is disposed around a respective one of said gate regions;
A plurality of body regions disposed above the source region and between the plurality of gate insulator regions;
A plurality of drift regions disposed above the plurality of body regions and between the plurality of gate insulator regions; and a plurality of drift regions disposed above the plurality of drift regions and between the plurality of gate insulator regions. Drain region;
A stripe cell type trench MOSFET having   The plurality of drain regions and the plurality of gate regions are disposed on a first surface side, and the source region is disposed on a second surface side opposite to the first surface. 2. A stripe cell type trench MOSFET according to 1. The source region comprises a heavily n-doped semiconductor;
The plurality of body regions comprise a p-type doped semiconductor;
The plurality of drift regions comprise a lightly doped n-type semiconductor;
The plurality of drain regions comprise a heavily n-doped semiconductor;
The plurality of gate insulator regions are made of oxide; and the plurality of gate regions are made of heavily n-doped semiconductor;
The stripe cell type trench MOSFET according to claim 1.   The stripe cell type trench MOSFET according to claim 1, wherein the plurality of body regions are electrically coupled to the source region. A plurality of first source-body contacts electrically coupled to the plurality of body regions;
A plurality of second source-body contacts electrically coupled to the plurality of first source-body contacts and the source region; and the first source-body contact and the second source-body contact. A source-body contact insulator region that is electrically isolated from one or more of the plurality of drift regions and the plurality of drain regions;
The stripe cell type trench MOSFET according to claim 1, further comprising: The plurality of first source-body contacts are made of heavily p-doped semiconductor; and the plurality of second source-body contacts are made of silicide;
6. A stripe cell type trench MOSFET according to claim 5.   2. The stripe-cell trench MOSFET according to claim 1, wherein the plurality of gate regions substantially overlap with the plurality of body regions.   2. The stripe cell type trench MOSFET according to claim 1, wherein the plurality of gate regions substantially overlap the plurality of body regions and the plurality of drift regions.   2. The stripe-cell trench MOSFET according to claim 1, wherein the plurality of gate regions do not substantially overlap the plurality of drain regions.   A plurality of super source regions disposed above the plurality of gate regions, further comprising a plurality of super source regions formed as substantially parallel elongated structures and electrically coupled to the source regions. Item 2. A stripe cell type trench MOSFET according to Item 1. A method of manufacturing a stripe cell type trench MOSFET comprising:
Depositing a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being doped with a first type impurity, and the semiconductor substrate being doped with a second type impurity;
Depositing a second semiconductor layer on the first semiconductor layer;
Etching a plurality of first trenches in a portion of the first semiconductor layer, the second semiconductor layer, and the semiconductor substrate, wherein the plurality of first trenches are substantially parallel to each other; Process;
Forming a first dielectric layer in the plurality of first trenches;
Depositing a first polysilicon layer in the plurality of first trenches;
Depositing a second dielectric layer on the first polysilicon layer in the plurality of first trenches;
Doping the first semiconductor layer with a first type impurity; and a portion of the second semiconductor layer opposite to the first semiconductor layer to a first concentration with a second type impurity. Doping step;
Having a method.   The method of claim 11, wherein depositing the first semiconductor layer comprises epitaxially growing silicon heavily doped with boron.   The method of claim 11, wherein depositing the second semiconductor layer comprises epitaxially growing silicon lightly doped with boron.   14. The method of claim 13, wherein the step of doping the first semiconductor layer with a first type impurity comprises the step of ion implanting boron.   The method of claim 11, wherein depositing the second semiconductor layer comprises epitaxially growing silicon lightly doped with phosphorus or arsenic.   12. The method according to claim 11, wherein the step of doping a part of the second semiconductor layer opposite to the first semiconductor layer with a second type impurity comprises ion implantation of phosphorus or arsenic. .   Prior to the step of doping the part of the second semiconductor layer, the step of doping the second semiconductor layer with a second type impurity to a second concentration, wherein the first concentration is the first concentration. The method of claim 11, further comprising a step having a concentration higher than 2. Etching a plurality of second trenches in a portion of the first semiconductor layer, the second semiconductor layer, and the semiconductor substrate, wherein the plurality of second trenches are substantially parallel to each other; And arranging between the plurality of first trenches;
Doping a portion of the first semiconductor layer adjacent to the plurality of second trenches;
Forming silicide in the plurality of second trenches along the semiconductor substrate and the first semiconductor layer; and depositing a third dielectric layer in the plurality of second trenches;
The method of claim 11, further comprising: The steps of forming the silicide include:
Sputtering a metal film along the semiconductor substrate and the first semiconductor layer in the plurality of second trenches; and subjecting the metal film, the semiconductor substrate, and the first semiconductor layer to a thermal cycle ;
The method of claim 18, comprising: Depositing a second polysilicon layer between the first polysilicon layer and the second dielectric layer in the plurality of first trenches; and the first polysilicon layer and the Forming a fourth dielectric layer between the second polysilicon layer;
The method of claim 11, further comprising: Source area;
A gate region disposed above the source region, wherein the first portion of the gate region is formed as a substantially parallel elongated structure, and the second portion of the gate region is substantially vertical, parallel A gate region formed as an elongated structure;
A gate insulator region disposed around the gate region;
A plurality of body regions disposed above the source region and between the gate insulator regions;
A plurality of drift regions disposed above the plurality of body regions and between the gate insulator regions; and a plurality of drain regions disposed above the plurality of drift regions and between the gate insulator regions;
A closed cell type trench MOSFET.   The plurality of drain regions and the gate region are disposed on a first surface side, and the source region is disposed on a second surface side opposite to the first surface. The closed cell type trench MOSFET as described. The source region comprises a heavily n-doped semiconductor;
The plurality of body regions comprise a p-type doped semiconductor;
The plurality of drift regions comprise a lightly doped n-type semiconductor;
The plurality of drain regions comprise a heavily n-doped semiconductor;
The gate insulator region comprises an oxide; and the gate region comprises a heavily n-doped semiconductor;
The closed-cell trench MOSFET according to claim 21.   The closed-cell trench MOSFET according to claim 21, wherein the plurality of body regions are electrically coupled to the source region. A plurality of first source-body contacts electrically coupled to the plurality of body regions;
A plurality of second source-body contacts electrically coupled to the plurality of first source-body contacts and the source region; and the plurality of first source-body contacts and the plurality of second A plurality of source-body contact insulator regions that electrically isolate a source-body contact from one or more of the plurality of drift regions and the plurality of drain regions;
The closed-cell trench MOSFET according to claim 21, further comprising: The plurality of first source-body contacts are made of heavily p-doped semiconductor; and the plurality of second source-body contacts are made of silicide;
26. A closed cell trench MOSFET according to claim 25.   The closed-cell trench MOSFET according to claim 21, wherein the gate region substantially overlaps the plurality of body regions.   The closed-cell trench MOSFET according to claim 21, wherein the gate region substantially overlaps the plurality of body regions and the plurality of drift regions.   24. The closed cell trench MOSFET according to claim 21, wherein the gate region does not substantially overlap the plurality of drain regions.   23. The closed source of claim 21, further comprising a super source region disposed above the gate region, the super source region being formed as a substantially parallel elongated structure and electrically coupled to the source region. Cell type trench MOSFET. A method of manufacturing a closed cell trench MOSFET comprising:
Depositing a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being doped with a first type impurity, and the semiconductor substrate being doped with a second type impurity;
Depositing a second semiconductor layer on the first semiconductor layer;
Etching a plurality of trenches in a portion of the first semiconductor layer, the second semiconductor layer, and the semiconductor substrate, the first set of the plurality of trenches being substantially parallel to each other; The second set of trenches is substantially parallel to each other and substantially perpendicular to the first set of trenches;
Forming a first dielectric layer on the first semiconductor layer, the second semiconductor layer, and the semiconductor substrate adjacent to the plurality of trenches;
Depositing a first polysilicon layer in the plurality of trenches;
Depositing a second dielectric layer on the first polysilicon layer in the plurality of first trenches;
Doping the first semiconductor layer with a first type impurity;
Doping the second semiconductor layer to a first concentration with a second type impurity; and a portion of the second semiconductor layer opposite to the first semiconductor layer with a second type impurity. Doping to a second concentration;
Having a method.   32. The method of claim 31, wherein depositing the first semiconductor layer comprises epitaxially growing silicon heavily doped with boron.   32. The method of claim 31, wherein depositing the second semiconductor layer comprises epitaxially growing silicon lightly doped with phosphorus or arsenic.   32. The method of claim 31, wherein the step of doping the second semiconductor layer with a second type impurity comprises the step of ion implanting phosphorus or arsenic.   32. The method of claim 31, wherein the step of doping the first semiconductor layer with a first type impurity comprises the step of ion implanting boron.   32. The method according to claim 31, wherein the step of doping a part of the second semiconductor layer opposite to the first semiconductor layer with a second type impurity comprises ion implantation of phosphorus. Etching a plurality of openings in a part of the first semiconductor layer, the second semiconductor layer, and the semiconductor substrate, the openings being in each of a plurality of cells formed between the plurality of trenches; Arranged in a process;
Doping a portion of the first semiconductor layer adjacent to the plurality of openings;
Forming silicide in the plurality of openings along the semiconductor substrate and the first semiconductor layer; and depositing a third dielectric layer in the plurality of openings;
32. The method of claim 31, further comprising: The steps of forming the silicide include:
Sputtering a metal film along the semiconductor substrate and the first semiconductor layer in the plurality of openings; and subjecting the metal film, the semiconductor substrate and the first semiconductor layer to a thermal cycle;
38. The method of claim 37, comprising: Depositing a second polysilicon layer between the first polysilicon layer and the second dielectric layer in the plurality of trenches; and the first polysilicon layer and the second Forming a fourth dielectric layer between the polysilicon layer;
32. The method of claim 31, further comprising:

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