KR20080025041A - Trench metal oxide semiconductor field effect transistor - Google Patents

Abstract

Embodiments here described provide a striped or closed cell trench metal-oxide semiconductor field effect transistor (TMOSFET). The striped or closed cell TMOSFET comprises a source region, a body region disposed above the source region, a drift region disposed above the body region, a drain region disposed above the drift region. A gate region is disposed above the source region and adjacent the body region. A gate insulator region electrically isolates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region. ® KIPO & WIPO 2008

Description

Trench metal oxide semiconductor field effect transistor {TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal oxide semiconductor field effect transistors (MOSFETs), and more particularly to vertical MOSFET devices having trench gate geometry.

Referring to FIG. 1, a cross-sectional perspective view of a striped trench metal oxide semiconductor field effect transistor (TMOSFET) 100 according to the prior art is shown. The striped TMOSFET 100 includes a plurality of source contacts 110, a plurality of source regions 115, a plurality of gate regions 120, a plurality of gate insulator regions 125, and a plurality of body regions ( body region 130, drain regions 135 and 140, and drain contacts 145. The drain regions 135 and 140 may optionally include a first drain portion 140 and a second drain portion 135.

The body region 130 is disposed above the drain regions 135 and 140. The source region 115, the gate region 120, and the gate insulator region 125 are disposed in the body region 130. The gate region 120 and the gate insulator region 125 are formed in a parallel-elongated structure. Gate insulator region 125 surrounds gate region 12. Thus, gate region 120 is electrically isolated from the surrounding region by gate insulator region 125. Gate regions 120 are combined to form a common gate of device 100. The source region 115 is formed in a structure elongated in parallel along the circumference of the gate insulator region 125. Source region 115 is joined by source contact 110 to form a common source of device 100. Although shown as a plurality of respective source contacts 110, the source contacts 110 may be implemented as a single conductive layer that joins all of the source regions 115. Source contact 110 also couples source region 115 with body region 130.

The source region 115 and the drain region 110 are heavily n-doped (N +) semiconductors, such as silicon doped with phosphorus or arsenic. Body region 130 is a p-doped (P) semiconductor, such as boron doped silicon. Gate region 120 is a large n-doped (N +) semiconductor, such as polysilicon doped with phosphorus. Gate insulator region 125 may be an insulator, such as silicon dioxide.

If the potential of the gate region 120 relative to the source region 115 increases above the threshold voltage of the device, a conductive channel is induced in the body region 130 along the perimeter of the gate insulator region 125. Striped TMOSFET 100 will then conduct current between drain region 140 and source region 115. Thus, the device is turned on.

If the potential of the gate region 120 decreases below the threshold voltage, the channel is no longer induced. As a result, the voltage potential applied between the drain region 140 and the source region 115 will not induce a current therebetween. Thus, device 100 is off and the junction formed by body region 130 and drain region 140 maintains the applied voltage across the source and drain.

If the drain regions 135 and 140 include a second drain portion 135 disposed over the first drain portion 140, the second portion 135 of the drain region may be formed of phosphorus or arsenic doped silicon. Lightly n-doped (N−) semiconductors, and the first portion 140 of the drain region is a bulk n-doped (N +) semiconductor, such as silicon doped with phosphorus or arsenic. The second portion 135 of the n-doped (N-) drain region in small amounts results in a depletion region that extends into both the body region 130 and the second portion 135 of the drain region. Thus reducing the punch through effect. Thus, the second portion 135 of the small n-doped (N-) drain region acts to increase the breakdown voltage of the striped TMOSFET 100.

The channel width of the striped TMOSFET 100 is a function of the length of the plurality of source regions 115. Thus, the striped TMOSFET 100 provides a large channel width at a ratio of lengths. Thus, striped TMOSFETs can be useful for power MOSFET applications, such as switching devices, in pulse width modulation (PWM) voltage regulators.

Referring to FIG. 2, there is shown a cross-sectional perspective view of a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) 200 according to the prior art. The closed cell TMOSFET 200 includes a plurality of source contacts 210, a plurality of source regions 215, a gate region 220, a gate insulator region 225, a plurality of body regions 230, and drain regions 235 and 240. ) And a drain contact 245. The drain regions 235 and 240 may optionally include a first drain portion 240 and a second drain portion 235.

The body region 230, the source region 215, the gate region 220, and the gate insulator region 225 are disposed on the drain regions 235 and 240. The first portion of the gate region 220 and the gate insulator region 225 are formed of a structure 221 extending substantially parallel. The second portion of the gate region 220 and the gate insulator region 225 are formed of a structure 222 that extends substantially vertically-parallel. The first and second portions of the gate region 220 are both interconnected to form a plurality of cells. The body region 230 is disposed in the plurality of cells formed by the gate region 220.

Gate insulator region 225 surrounds gate region 220. Thus, the gate region 220 is electrically isolated from the surrounding region by the gate insulator region 225. Source region 215 is formed in the plurality of cells along the periphery of gate insulator region 225.

Source region 215 is joined by source contact 210 to form a common source of device 200. Although a plurality of individual source contacts 210 are shown, the source contacts 210 may be implemented as a plurality of conductive strips coupling each of the plurality of source regions 215, a single conductive layer coupling all the source regions 215, and the like. It could be. Source contact 210 also couples source region 215 to body region 230.

The source region 215 and the drain region 240 are largely n-doped (+ N) semiconductors, such as silicon doped with phosphorus or arsenic. Body region 230 is a p-doped (P) semiconductor, such as silicon doped with boron. Gate region 220 is a large n-doped (N +) semiconductor, such as polysilicon doped with phosphorus. Gate insulator region 225 may be an insulator such as silicon dioxide.

When the potential of the gate region 220 relative to the source region 215 increases above the threshold voltage of the device 200, a conductive channel is induced in the body region 230 along the periphery of the gate insulator region 25. Device 200 will conduct current between drain region 240 and source region 215. Thus, the device 200 is turned on.

If the potential of gate region 220 decreases below the threshold voltage, the channel is no longer induced. As a result, the voltage potential applied between the drain region 240 and the source region 215 does not cause a current flowing therebetween. Thus, the device is turned off and the junction between body region 230 and drain region 240 maintains the applied voltage across the source and drain.

If the drain regions 235 and 240 include a second portion 235 disposed above the first portion 240, the second portion 235 of the drain region may be a small amount, such as silicon doped with phosphorous or arsenic. N-doped (N−) semiconductor, and the first portion 240 of the drain region is a semiconductor n-doped (N +) in bulk, such as phosphorus-doped silicon. The second portion 235 of the n-doped (N-) drain region in small amounts results in a depletion region extending into both the body region 230 and the second portion 235 of the drain region, thus punch-through Reduce the effect. Thus, the second portion 235 of the small n-doped (N-) drain region acts to increase the breakdown voltage of the closed cell TMOSFET 200.

The channel width of the closed cell TMOSFET 200 is a function of the sum of the widths of the source regions 215. As an EK, the closed cell TMOSFET 200 structure advantageously increases the width of the channel region when compared to the striped TMOSFET 100. Thus, the closed cell TMOSFET 200 has a relatively low channel resistance (ie, on resistance) as compared to the striped TMOSFET 100. The low channel resistance reduces the power dissipated in the closed cell TMOSFET 200 compared to the striped TMOSFET 100.

Similarly, the gate-to-drain capacitance of the closed cell TMOSFET 220 is a function of the overlap between the bottom of the gate region 220 and the drain region 240. Thus, the closed cell TMOSFET 200 structure produces a high gate-to-drain capacitance when compared to the striped TMOSFET 100. The relatively high gate-to-drain capacitance limits the switching speed of the closed cell TMOSFET 200 as compared to the striped TMOSFET 100.

Thus, the embodiment described herein provides a trench metal-oxide-semiconductor field effect transistor (TMOSFET) in which the gate and drain regions are on the same side, while the source region is disposed opposite. Embodiments of the present invention provide a striped or closed cell TMOSFET having an on resistance substantially the same as a striped or closed cell TMOSFET. In addition, embodiments of the present invention provide a striped or closed cell TMOSFET with low gate-to-drain capacitance.

Embodiments of the present invention also provide a striped or closed cell TMOSFET comprising a source region, a body region disposed over the source region, a drift region disposed over the body region, a drain region disposed over the drift region. The gate region is disposed near the body region above the source region. The gate insulator region electrically isolates the gate region from the source region, the body region, the drift region and the drain region. The body young bran is electrically coupled with the source region.

The present invention also provides a method of fabricating a striped or closed cell TMOSFET. The fabrication method includes growing P-doped epitaxial silicon onto an N-doped silicon substrate and growing N-doped epitaxial silicon into a P-doped silicon layer. The epitaxially deposited silicon layer and a portion of the substrate are selectively etched to form a trench set. Silicon near the trench is oxidized to form a gate oxide region. The first portion of the trench is filled with polysilicon and the remainder is filled with a dielectric. n-type impurities are implanted to form the drift region and the gate region. P-type impurities are implanted to form the body region of the N-channel MOSFET.

The present invention shows an example in the accompanying drawings, but is not limited thereto, and like reference numerals refer to like elements.

1 is a cross-sectional perspective view of a striped trench metal oxide semiconductor field effect transistor (TMOSFET) according to the prior art.

2 is a cross-sectional perspective view of a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) according to the prior art.

3 is a cross-sectional perspective view of a striped cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention.

4 is a cross-sectional perspective view of yet another striped cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention.

5A-5D are flow diagrams of a method of fabricating a striped cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention.

6A-6O are cross-sectional perspective views of various stages of fabrication of a striped cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention.

7 is a cross-sectional perspective view of a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention.

8A-8D are flow diagrams of a method of fabricating a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention.

9A-9O are cross-sectional plan views of various fabrication steps of a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention.

10A-10D are flow diagrams of a method of fabricating a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with another embodiment of the present invention.

11A-11N are cross-sectional plan views of various fabrication steps of a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with another embodiment of the present invention.

An embodiment of the present invention will be described in detail with reference to the accompanying drawings. Although the present invention will be described in conjunction with these examples, the present invention is not limited to these examples. On the contrary, the invention is intended to cover modifications, variations, and equivalents that may be included within the scope of the invention as defined by the appended claims. In addition, in the following detailed description of the invention, numerous details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be practiced without these details. In other instances, well-known methods, procedures, components and circuits will not be described in detail in order not to unnecessarily obscure the present invention.

Referring now to FIG. 3, a cross-sectional perspective view of a striped cell trench metal oxide semiconductor field effect transistor (TMOSFET) 300 is shown in accordance with an embodiment of the present invention. The striped cell TMOSFET 300 includes a source contact 310, a source region 315, a plurality of gate regions 320, a plurality of gate insulator regions 325, a plurality of body regions 330, and a plurality of drifts ( a drift region 335, a plurality of drain regions 340, and a drain contact portion 345. Striped cell TMOSFET 300 may also comprise a first source-body contact region 350, a second source-body contact region 355, and a source-body contact insulator region 360.

The plurality of gate regions 320, the plurality of gate insulator regions 325, the plurality of body regions 330, the plurality of drift regions 335, and the plurality of drain regions 340 are disposed on the source region 315. . The gate region 320 and the gate insulator region 325 are formed to have a substantially parallel structure. The body region 330 is disposed between the parallel elongated structure formed by the gate region 320 and the gate insulator region 325 on top of the source region 315. The drain region 340 is disposed between the parallel elongated structure formed by the gate region 320 and the gate insulator region 325 on top of the drift region 335.

Gate region 320 is surrounded by corresponding gate insulator region 325. Accordingly, the gate region 320 is surrounded by the gate insulator region 325 (ie, the source region 315, the body region 330, the drift region 335, the drain region 340, and the drain contact 345). Is electrically isolated from Although not shown, the gate regions 320 intersect each other (ie, in the peripheral region of the device by the gate contacts). The plurality of drain regions 340 form the common drain of the device by the drain contacts 345. From the above description, the striped TMOSFET 300 of the present invention has a gate region 320 and a drain region 340 on substantially the same side.

In one embodiment, the source region 315 and the drain region 340 may be largely n-doped (N +) semiconductors, such as silicon doped with phosphorous or arsenic. The body region 330 may be a p-doped (P) semiconductor, such as silicon doped with boron. The drift region may be a small n-doped (N-) semiconductor, such as silicon doped with phosphorus or arsenic. Gate region 320 may be a large amount of n-doped (N +) or p-doped (P +) semiconductors, such as polysilicon doped with phosphorus or arsenic or polysilicon doped with boron. Gate insulator region 325 may be an oxide, such as silicon dioxide.

In another embodiment, source region 315 and drain region 340 may be a large amount of p-doped (P +) semiconductors, such as silicon doped with boron. The body region 330 may be a small n-doped (N-) semiconductor, such as silicon doped with phosphorous or arsenic. The drift region may be a small p-doped (P-) semiconductor, such as boron doped silicon. The gate region 320 may be a large amount of n-doped (N +) or p-doped (P) semiconductors, such as polysilicon doped with phosphorus or arsenic, or polysilicon doped with boron. Gate insulator region 325 may be an oxide, such as silicon dioxide.

Body region 330 is electrically coupled to source region 315. In one embodiment, body region 330 is coupled to source region 315 by first and second source-body contact regions 350 and 355. The second source-body bond region 355 is a silicide, such as tungsten silicide. The first source-body contact region 350 is a largely p-doped (P +) semiconductor, such as boron doped silicon. Source-body contact regions 350 and 355 are electrically isolated from the region surrounded by source-body insulator region 360 (ie, drift region 335). In one embodiment, the source-body contact insulator region 360 may be an oxide, such as silicon dioxide. In yet another embodiment, the source-body contact insulator region 360 may be p-doped polysilicon, silicon nitride, or the like.

When the potential of the gate region 320 relative to the source region 315 increases above the threshold voltage of the device 300, a conductive channel is induced in the body region 330 along the perimeter of the gate insulator region 325. The device 300 will then conduct a current between the plurality of drain regions 340 and the source region 315. Thus, device 300 is in an on state. If the potential of the plurality of gate regions 302 decreases below the threshold voltage, the channel is no longer induced. As a result, the voltage potential applied between the plurality of drain regions 340 and the source region 315 does not generate a current induced therebetween. Thus, device 300 is turned off and the junction of body region 330 and drift region 335 maintains the voltage applied across source region 315 and drain region 340.

The width of the channel is a function of the sum of the lengths of the drain regions 340. Thus, the width of the channel region is substantially the same as the conventional striped cell TMOSFET 100. Thus, the on resistance Rds-on of the device 300 is substantially the same as the conventional striped cell TMOSFET 100.

In the same striped cell TMOSFET 100, a lead wire is used to connect a source at the die to an external device. Source wire leads increase the effective inductance of the source in conventional striped cell TMOSFET 100. The source of the striped cell TMOSFET 300 of the present invention may be directly connected to a PCB or a conventional striped cell TMOSFET (ie, the source contact may extend to the bottom of the die or may be a wave junction connected to a PCB or the like). The wire leads of the source may be removed, so the effective inductance is reduced.

The striped cell TMOSFET 300 of the present invention may be manufactured so that the gate region 320 does not overlap the drain region 340. Therefore, the separation between the gate region 320 and the drain region 340 is increased. Thus, the gate-to-drain capacitance Cgd can be substantially reduced compared to the conventional striped cell TMOSFET 100. For example, in one embodiment the gate region substantially overlaps the body region and the drift region or drain region does not substantially overlap.

In addition, the striped cell TMOSFET 300 of the present invention has a relatively large gate-to-source capacitance Cgs as a result of the overlap of the source region 315 and the gate region 320. Thus, the gate-to-source capacitance Cgs of the striped cell TMOSFET 300 of the present invention is generally greater than the gate-to-source capacitance Cgs of the conventional striped cell TMOSFET 100. Thus, the ratio of gate-to-drain capacitance Cgd to source-to-drain capacitance Cgs, which is the figure of merit of the striped cell TMOSFET 300 of the present invention, is the conventional striped cell TMOSFET 100. Less than) (i.e. have a good figure of merit). Furthermore, the ratio of gate to drain capacitance Cgd to gate to source capacitance Cgs adjusts the thickness of gate oxide region 325 near source region 315 and / or gate near drain region 340. It can be adjusted by adjusting the thickness of a portion of the insulator region 325.

Overlap between the gate region 320 and the drift region 335 increases the accumulation of conductive channels while the device 300 is on. Accordingly, the gate region 320 extends to overlap the body region 330 and the drift region 335 so that the on resistance Rds-on of the striped cell TMOSFET 300 of the present invention can be further reduced. .

Referring to FIG. 4, there is shown a cross-sectional perspective view of yet another striped cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention. Striped cell TMOSFET 400 is the same as described with reference to FIG. 3 with the addition of a plurality of super source regions 365. The super source region 365 is formed as a substantially parallel elongated structure disposed on the gate region 320. The gate insulator region also surrounds the super source region 365, from the surrounding region (ie, gate region 320, body region 330, drift region 335, drain region 340, and drain contact 345). Super source region 365 is electrically isolated.

Although not shown, the super source region 365 is electrically coupled with the source region 315 (ie, by contacts in the peripheral region). The super source region 365 reduces the on state resistance Rds-on and increases the breakdown voltage in the off state.

The drain contact 345 is shown by cutting away a portion of the exterior substantially to show the striped cell structure in more detail. However, it will be understood that drain contact 345 lies to cover the surface of the core region of the striped cell TMOSFET 400 of the present invention.

Referring now to FIGS. 5A-5D, a flow diagram of a method of manufacturing a striped cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention is shown. A method of manufacturing a striped cell TMOSFET according to one embodiment of the present invention is shown in FIGS. 6A-6O. As shown in FIGS. 5A and 6A, at 502, the process begins with various initial processes such as cleaning, depositing, doping, etching, etc. on the substrate 502 ′. In one embodiment, the substrate 502 'includes silicon that is heavily doped with phosphorus (N +). The semiconductor substrate 502 'will substantially include the source region of the TMOSFET when the fabrication process is complete.

At 504, a first semiconductor layer 504 ′ is epitaxially deposited on the substrate 502 ′. In one embodiment, the first semiconductor layer 504 'comprises p-doped (P) silicon. Epitaxially deposited silicon may be doped by introducing desired impurities such as boron into the epitaxial reaction chamber. Alternatively, the doping of the first semiconductor layer 504 ′ may be performed by high energy injection with a p-type dopant such as boron.

At 506, a second semiconductor layer 506 ′ is epitaxially deposited over the first semiconductor layer 504 ′. In one embodiment, the second semiconductor layer 506 'comprises a small amount of p-doped (P-) silicon. Epitaxially deposited silicon can be doped by introducing desired impurities, such as boron, into the reaction chamber. Alternatively, the doping of the second semiconductor layer 506 ′ may be performed by high energy injection with a p-type dopant such as boron.

In an optional process 508, a sacrificial oxide layer 508 ′ is formed on the second semiconductor layer 506 ′. In one embodiment, the sacrificial oxide layer 508 'is formed by oxidizing the surface of the second semiconductor layer 506'. At 510, photo-resist is deposited and patterned by known lithography processes to form a gate trench resistive layer 510 '.

At 512, the exposed portions of the sacrificial oxide layer 508 ′, the second semiconductor layer 506 ′, the first semiconductor layer 504 ′, and a portion of the substrate 502 ′ are known anisotropic etching methods (ie, And dry etching). In one embodiment, the ionic etchant comprises a sacrificial oxide layer 508 ', a second semiconductor layer 506', a first semiconductor layer 504 'exposed by the gate trench resistive layer 510' and Interact with the substrate 502 '. The etching process forms a plurality of first trenches 512 'formed in a substantially parallel structure.

At 514, gate trench resistive layer 510 'is removed using a suitable resist stripper or resist stripping process. At 516, dielectric layer 516 ′ is formed on the walls of the plurality of first trenches 512 ′. In one embodiment, dielectric layer 516 'is formed by oxidizing exposed surfaces of silicon to form a silicon dioxide layer. The dielectric layer 516 'formed along the wall of the resulting trench forms the first portion of the gate insulator region.

At 518, a polysilicon layer is deposited in the plurality of first trenches 512 ′. In one embodiment, polysilicon is deposited in trench 512 'by a method such as decomposition of silane (SiH ₄ ). Polysilicon is doped with n-type impurities such as phosphorous or arsenic. Polysilicon may be doped by introducing impurities during the deposition process. At 520, an etch-back process is performed to remove excess polysilicon material to form gate region 520 ′. The polysilicon layer is etched back such that a desired separation / overlap is formed between the gate region formed from the polysilicon layer of the trench and the subsequently formed body, drift and drain regions. In one embodiment, excess polysilicon is removed by a combination of chemical mechanical polishing (CMP) and anisotropic etching methods.

In an alternative embodiment, a dielectric layer is formed over the gate region 520 '. In one implementation, polysilicon in the gate region 512 'is oxidized to form a silicon dioxide layer. A second polysilicon layer is deposited over the dielectric layer formed over the gate region 520 '. Another etch back process is used to form the super source region from the second polysilicon layer.

As shown in FIGS. 5B and 6E, a dielectric layer is deposited in the plurality of first trenches 512 ′ at 522. In one implementation, the dielectric is deposited in the trench by a method such as decomposition of tetraethly orthosilicate (TEOS) or high density plasma fill (HDP) At 524, extra dielectric material is deposited. Removed to complete the gate insulator region 524 '. In one implementation, the excess dielectric is removed by a chemical mechanical polishing (CMP) process.

At 526, the first semiconductor layer 504 ′ is p-doped to adjust the doping concentration to form a body region 526 ′ between the plurality of first trenches 512 ′. In one implementation, a p-type impurity 527 ', such as boron, is implanted into the first semiconductor layer 504' in a doping process. At 528, a thermal cycle is used to drive (ie, diffuse) the implanted impurities substantially at the depth of the first semiconductor layer 504 ', thereby forming a body region 526'. At 530, the second semiconductor layer 506 ′ is n-doped. In one implementation, the doping process implants an n-type impurity 531 ', such as phosphorous or arsenic, into the second semiconductor layer 506'. At 532, a second thermocycle is used to drive (ie, diffuse) the impurity implanted at substantially the depth of the second semiconductor layer 506 ′. At 543, the top of the second semiconductor layer 506 ′ is n-doped in large quantities, so that a drain 534 ′ is provided on top of the second semiconductor layer 506 ′ between the plurality of first trenches 512 ′. A drift region 530 'is formed at the lower portion. In one implementation, an n-type impurity 533 ', such as phosphorous or arsenic, is implanted on top of the second semiconductor layer 506' in the doping process. At 536, a third thermal cycle can be used to drive the third injection to obtain drain region 534 'to the desired depth.

In an optional process 528, a second sacrificial oxide layer 538 ′ is formed over the wafer. In one implementation, the sacrificial oxide layer 538 'is formed by oxidizing the surface of the wafer. At 542, photo-resist is deposited and patterned by known lithography processes to form source-body contact trench resistive layer 542 ′.

5C and 6J, at 544, exposed portions of the second sacrificial oxide layer 538 ', drain region 534' and drift region 530 'are etched by known anisotropic etching methods. In one implementation, an ion etchant interacts with the sacrificial oxide layer 538 ', the drain region 534' and the drift region 530 'exposed by the source-body contact trench resistive layer 542'. Each of the plurality of second trenches 544 'is disposed between each of the plurality of first trenches 512'.

At 546, the exposed portion of body region 526 ′ is heavily p-doped to form first source-body contact 546 ′. In one implementation, a p-type impurity 545 'such as boron is implanted into the body region 526' in a doping process. Thermocycling may be used to substantially drive the source-body implant at the exposed portion of the body region 526 ′. The implant portion will laterally diffuse into the adjacent unexposed portion of the body region 526 ′.

At 548, source-body contact trench resistive layer 542 ′ is removed using a suitable resist remover or resist remove process. At 550, dielectric layer 550 ′ is formed on the walls of the plurality of second trenches 544 ′. In one implementation, dielectric layer 550 'may be formed by oxidizing the exposed silicon surface to form a silicon dioxide layer.

At 552, the dielectric formed at the bottom of the plurality of second trenches 544 ′ and the exposed portions of the body region 526 ′ is etched by known anisotropic etching methods. The etching process is performed until the plurality of second trenches 552 'partially extends into the source region 502' (ie, the substrate). The etching process leaves adjacent portions of the body region 526 'and the source region 502' while leaving the drift region 530 'and the drain region protected by the dielectric layer 550' along the sides. Source-body contact implants that laterally diffuse into the unexposed portions of body region 526 'remain substantially even after the etching process of the present invention. The remaining portion of the source-body contact injection forms the first source-body contact.

At 554, a first metal layer 554 ′ is deposited on the bottom of the plurality of second trenches 552 ′ and reacts with the source region 502 ′ and the body region 526 ′. In one implementation, titanium is sputtered and quickly annealed to form titanium silicide (TiSi) along exposed portions of the source region 502 'and the body region 526'. Titanium silicide forms a second source-body contact 556 ', which is coupled to the first source-body contact 546' to electrically couple the body region 526 'and the source region 502' ( couple). At 556, the unreacted metal portion is etched along the wall where the dielectric of the source-body trench has stuck.

At 558, a second dielectric is deposited in the plurality of second trenches 552 ′ to form the source-body insulator region 560 ′. In one implementation, the dielectric is deposited by a method such as decomposition of tetraethylorthosilicate (TEOS) or high density plasma fill (HDP).

At 564, photo-resist is deposited and patterned by known lithography processes to form a gate contact resistive layer (not shown). Gate contacts are formed around (not shown). At 566, the exposed portion of gate insulator 524 'is etched by a known anisotropic etching method (not shown). In one implementation, the ion etchant interacts with the gate oxide exposed by the gate contact resistive layer. The gate contact opening extends down to the gate 520 '. At 568, the gate contact resistive layer is removed using a suitable resist remover or resist remove process (not shown).

At 570, photo-resist is deposited and patterned by a known lithography process (not shown). At 572, the exposed portion of the second sacrificial oxide is etched by a known anisotropic etching method (not shown). In one implementation, the ion etchant interacts with the third sacrificial oxide and the extra second dielectric material to form a drain contact opening. The drain contact opening extends down to the drain region. At 574, the drain contact resistive layer is removed using a suitable resist remover or resist remove process.

At 576, a second metal layer is deposited on the wafer. In one implementation, a second metal layer, such as aluminum, is deposited by known methods such as sputtering. The second metal layer covers the top of the drain 534 ', the gate insulator 524' and the source-body contact insulator 560 '. The second metal layer extends down to the gate contact opening to make an electrical contact to the gate 520 ', and extends down to the drain contact opening to make an electrical contact to the drain. Then at 578, the second metal layer is patterned using a photo-resist mask and an optional etching method to form a gate contact layer (not shown) and a drain contact layer 578 '.

At 584, fabrication proceeds through various back-end processes to form source contacts. Various processes typically include etching, deposition, doping, cleaning, annealing, passivation, cleaving, and the like.

Referring now to FIG. 7, a cross-sectional perspective view of a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) 700 in accordance with one embodiment of the present invention is shown. The closed cell TMOSFET 700 includes a source contact 710, a source region 715, a gate region 720, a gate insulator region 725, a plurality of body regions 730, a plurality of drift regions 735, a plurality of And a drain region 740 and a drain contact 745. The closed cell TMOSFET 700 may further include a plurality of first source-body contact regions 750, a plurality of second source-body contact regions 755, and a plurality of source-body contact insulator regions 760. .

The gate region 720, the gate insulator region 725, the plurality of body regions 730, the plurality of drift regions 735, and the plurality of drain regions 740 are deposited on the source region 715. The first portion of the gate region 720 and the gate insulator region 725 are formed to extend substantially in parallel. The second portion of the gate region 620 and the gate insulator region 625 are formed in a substantially vertically-parallel elongated structure (ie, in the surface plane of the wafer, the second portion of the gate region and the gate insulator region are gated). A plurality of substantially parallel elongated structures formed at right angles to the first portion of the region and the gate insulator region). The first and second portions of the gate region 720 are both interconnected to form a plurality of cells. The body region 730 is disposed inside the plurality of cells and over the source region 715. The drift region 735 is disposed inside the plurality of cells and over the body region 730. The drain region 740 is disposed inside the plurality of cells and over the drift region 735. The drain contact 745 is shown in a substantially cutout to reveal the closed cell structure in more detail. However, it should be understood that drain contact 745 covers the entire surface of the core region.

Gate region 720 is surrounded by gate dielectric region 725. Thus, gate region 720 is surrounded by gate insulator region 725 (ie, source region 715, body region 730, drift region 735, drain region 740, and drain contact 745). Is electrically isolated). A plurality of drain regions 740 are joined by drain contacts 745 to form a common drain of the device. From the above description, it can be seen that the closed cell TMOSFET 700 of the present invention has a gate and a drain terminal on the same side.

In one implementation, source region 715 and drain region 740 may be a large n-doped (N +) semiconductor, such as phosphorus or arsenic doped silicon. The body region 730 may be a p-doped (P) semiconductor, such as silicon doped with boron. The drift region 735 may be a small amount of n-doped (N-) semiconductor, such as silicon doped with phosphorus or arsenic. The gate region 720 may be a large amount of n-doped (N +) semiconductors or a large amount of p-doped (P +) semiconductors, such as polysilicon doped with phosphorus or arsenic or polysilicon doped with boron. . Gate insulator region 725 may be an oxide, such as silicon dioxide.

In other implementations, source region 715 and drain region 740 may be a large amount of p-doped (P +) semiconductors, such as silicon doped with boron. Body region 730 may be a small n-doped (N-) semiconductor, such as silicon doped with phosphorous or arsenic. The drift region 735 may be a semiconductor p-doped (P-) in small amounts, such as silicon doped with boron. The gate region 720 may be a large amount of p-doped (P +) or largely n-doped (N +) semiconductors, such as boron doped polysilicon or phosphorus or arsenic doped polysilicon. Gate insulator region 725 may be an oxide, such as silicon dioxide.

Body region 730 is electrically coupled with source region 715. In one implementation, body region 730 is coupled with source region 715 by first and second source-body contact regions 750 and 755. The second source-body contact region 750 may be a silicide, such as tungsten silicide. The first source-body contact region 755 may be a largely p-doped (P +) semiconductor, such as silicon doped with boron. Source-body contact regions 750 and 755 are electrically isolated from surrounding drift region 735 by source-body contact insulator region 760. In one implementation, source-body contact insulator region 760 may be an oxide, such as silicon dioxide. In other implementations, the source-body contact insulator region 760 may be p-doped polysilicon, such as silicon nitride. Source-body contact regions 750 and 755 and source-body insulator region 760 are formed substantially in the center of each cell. The front corner of the cross section is cut away to show the structure of the source-body contact regions 750 and 755 and the source-body insulator region 760 in detail.

When the potential of the gate region 720 relative to the source region 715 increases above the threshold voltage of the device 700, a conductive channel is induced in the body region 730 along the perimeter of the gate insulator region 725. The device 700 will conduct current between the plurality of drain regions 740 and the source region 715. Thus, the device 700 is turned on. If the potential of the plurality of gate regions 720 decreases below the threshold voltage, the channel is no longer induced. As a result, the voltage potential applied between the plurality of drain regions 740 and the source region 715 will not cause current to be induced therebetween. Thus, device 700 is turned off and the junction of body region 730 and drift region 735 maintains the voltage applied across source region 715 and drain region 740.

The channel width is a function of the sum of the lengths of the periphery of the drain region 740, around the gate insulator region 725. Thus, the width of the channel region is substantially the same as the conventional closed cell TMOSFET 200. Thus, the on resistance Rds-on of the device 700 is substantially the same as the conventional closed cell TMOSFET 200.

In a conventional closed cell TMOSFET 200, lead wires are used to connect a source at a die to an external device. The source wire lead increases the effective inductance of the source in a conventional closed cell TMOSFET 200. The source of the closed cell TMOSFET 700 of the present invention may be directly connected to a PCB or a conventional closed cell TMOSFET 200 (ie, the source contacts may extend to the bottom of the die or may be wave bonded to a PCB or the like). The wire lead of the source can be eliminated, thus the effective inductance of the closed cell TMOSFET 700 of the present invention is reduced.

The closed cell TMOSFET 700 of the present invention may be fabricated so that the gate region 720 does not overlap the drain region 740. Thus, the separation between the gate region 720 and the drain region 740 is increased. Increased isolation reduces the gate-to-drain capacitance Cgd. Thus, the gate-to-drain capacitance Cgd of the closed cell TMOSFET 700 of the present invention is reduced as compared to the conventional closed cell TMOSFET 200.

Additionally, the closed cell TMOSFET 700 of the present invention has a relatively large gate-to-source capacitance Cgs as a result of the overlap of the gate region 720 and the source region 715. Thus, the gate-to-source capacitance Cgs of the closed cell TMOSFET 700 of the present invention is generally larger than the gate-to-source capacitance Cgs of the conventional closed cell TMOSFET 200. The ratio of gate-to-source capacitance Cgd to source-to-drain capacitance Cgs, which is the figure of merit of the closed cell TMOSFET 700 of the present invention, is smaller than that of a conventional closed cell TMOSFET 200 (ie, Is a good figure of merit). Further, the ratio of gate-to-drain capacitance Cgd to gate-to-source capacitance Cgs adjusts the thickness of a portion of the gate insulator region 725 near the source region 715 and / or the drain region. The thickness of a portion of the gate insulator region 725 near 740 can be adjusted.

Overlap between the gate region 725 and the drift region 735 results in an increase in the accumulation of conductive channels while the device 700 is on. Thus, if the gate region 720 extends to overlap the body region 730 and the drift region 735, the on-resistance (Rdg-on) of the closed cell TMOSFET 700 of the present invention may be further reduced. .

Although not shown, the closed cell TMOSFET 700 may further include a super source region. The super source region is formed as a structure extending substantially parallel to the gate region 720. The gate insulator region 725 also surrounds the super source region so that the super source region is surrounded by the surrounding region (ie, the gate region 720, the body region 730, the drift region 735, the drain region 740, and the drain contact portion (). 745). The super source region is electrically coupled with the source region 715 (by contact in the peripheral region). The super source region reduces the on state resistance Rds-on of the closed cell TMOSFET 700 and increases the breakdown voltage in the off state.

Referring now to FIGS. 8A-8D, a flow diagram of a method of fabricating a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) in accordance with one embodiment of the present invention is shown. A method of fabricating a closed cell TMOSFET, in accordance with one embodiment of the present invention, is shown in FIGS. 9A-9N. As shown in FIGS. 8A and 9A, at 802, various initial processes, such as cleaning, deposition, doping, etching, etc., on the substrate 802 ′ are initiated. In one implementation, the substrate 802 'comprises silicon that is heavily doped with phosphorus (N +). The semiconductor substrate 802 'will comprise the source region of the TMOSFET at substantially the end of the fabrication process.

At 804, a first semiconductor layer 804 ′ is epitaxially deposited on the substrate 802 ′. In one implementation, the first semiconductor layer 804 ′ includes large amounts of p-doped (P +) silicon. Epitaxially deposited silicon may be doped by placing desired impurities such as boron into the epitaxial reaction chamber. Alternatively, doping of the first semiconductor layer may be obtained by high energy implantation with a p-type dopant such as boron.

At 806, a second semiconductor layer 806 ′ is epitaxially deposited on the first semiconductor layer 804 ′. In one implementation, the second semiconductor layer 806 'comprises n-doped (N) silicon. Epitaxially deposited silicon may be doped by placing desired impurities such as phosphorous or arsenic into the reaction chamber. Alternatively, the doping of the second semiconductor layer may be obtained by high energy implantation of n-type dopants such as phosphorous or arsenic.

At 808, an optional process, a first sacrificial oxide layer 808 ′ is formed on the second semiconductor layer 806 ′. In one implementation, the sacrificial oxide layer 808 'is formed by oxidizing the surface of the second semiconductor layer 806'. At 810, photo-resist is deposited and patterned by a known lithography process to form a gate trench resistive layer 810 '.

At 812, the exposed portions of sacrificial oxide layer 808 ′, second semiconductor layer 806 ′, first semiconductor layer 804 ′, and portions of substrate 802 ′ are known anisotropic etching methods (ie, dry etching). Is etched). In one implementation, the ion etchant is provided with a sacrificial oxide layer 808 ', a second semiconductor layer 806', a first semiconductor layer 804 'and a substrate 802' exposed by the gate trench resistive layer 810 '. Interact The etching process produces a plurality of trenches 812 'having a plurality of cells therein. The plurality of trenches 812 'are formed to have a first portion of the substantially parallel structure and a second portion of the substantially vertical-parallel structure.

At 814, gate trench resistive layer 810 ′ is removed using a suitable resist remover or resist remove process. At 816, a first dielectric 816 ′ is formed on the walls of the plurality of trenches 812 ′. In one implementation, the first dielectric 816 'is produced by oxidizing an exposed surface of silicon to form a silicon dioxide layer. The resulting dielectric 816 ′ along the trench walls forms a first portion of the gate insulator region.

At 818, polysilicon layer 820 ′ is deposited in the plurality of first trenches 812 ′. In one implementation, polysilicon 820 'is deposited in trench 812' by a method such as decomposition of silane (SiH ₄ ). Polysilicon may be doped with n-type impurities such as phosphorous or arsenic. Polysilicon may be doped by introducing impurities during the deposition process. At 820, an etch back process is performed to remove excess polysilicon material and form a gate region. The polysilicon layer is etched back to achieve the desired separation / overlap between the gate region formed from the polysilicon layer in the trench and the subsequently formed body, drift and drain regions. In one implementation, excess polysilicon is removed by combining a chemical mechanical polishing (CMP) process and an anisotropic etching method.

In an alternative embodiment, a dielectric layer is formed over the gate. In one implementation, the polysilicon of the gate is oxidized to form silicon dioxide. A second polysilicon layer is deposited over the dielectric layer formed over the gate. Another etch back process is used to form the super source from the second polysilicon layer.

As shown in FIGS. 8B and 9E, at 822 a second dielectric 824 ′ is deposited in the plurality of second trenches 812 ′. In one implementation, a dielectric is deposited in the trench by methods such as decomposition of tetraethylorthosilicate (TEOS) or high density plasma fill (HDP). At 824, excess dielectric material is removed to complete the gate insulator region. In one implementation, the excess dielectric is removed by a chemical mechanical polishing (CMP) process.

At 826, the first semiconductor layer 804 ′ is p-doped to adjust the doping concentration of the body region 826 ′ between the plurality of trenches 812 ′. In one implementation, the doping process injects p-type impurities 827 ', such as boron, into the first semiconductor layer 804'. At 828, thermal cycling is used to drive (ie, diffuse) the implanted impurities substantially to the depth of the first semiconductor layer 804 ', forming the body region 826'. At 830, second semiconductor layer 806 ′ is n-doped. In one implementation, the doping process injects n-type impurities 831 ', such as phosphorous or arsenic, into the second semiconductor layer 806'. At 832, a second thermocycle is used to drive (ie, diffuse) the implanted impurities substantially to the depth of the second semiconductor layer 806 ′. At 834, the upper portion of the second semiconductor layer 806 ′ is n-doped in bulk to form a drain region 834 ′ above the second semiconductor layer 806 ′ between the plurality of trenches 812 ′ and the lower portion. An drift region 830 'is formed. In one implementation, the doping process implants n-type impurities 833 ', such as phosphorous or arsenic, on top of the second semiconductor layer 806'. At 836, a third thermal cycle is used to drive drain region implantation to obtain the desired depth of drain region 834 '.

At 838, a second sacrificial oxide layer 838 ′ is formed over the wafer. In one implementation, a second sacrificial oxide layer 838 'is formed by oxidizing the wafer surface. At 840, photo-resist is deposited and patterned by known lithography processes to form source-body contact opening resistive layer 840 '.

As shown in FIGS. 8C and 9J, the exposed portions of the second sacrificial oxide layer 838 ′, source region 834 ′ and drift region 830 ′ are etched at 842 by a known anisotropic etching method. In one implementation, the ion etchant interacts with the second sacrificial oxide layer 836 ', the source region 834' and the drift region 830 'exposed by the source-body contact opening resistive layer 840'. The etching process forms a plurality of source-body contact openings 842 '. Each source-body contact opening 842 'is disposed within a cell formed by a plurality of trenches 812'.

At 844, the exposed portion of body region 826 ′ is heavily doped to form first source-body contact region 844 ′. In one implementation, the doping process injects p-type impurities 843 ', such as boron, into the body region 826'. Thermocycling may be used to drive the source-body implant substantially to the exposed portion of the body region 826 ′. The portion to be implanted will laterally diffuse up to an adjacent unexposed portion of the body region 826 ′.

At 846, source-body contact opening resistive layer 840 'is removed using a suitable resist remover or resist remove process. At 848, dielectric 848 ′ is formed in the wall of the source-body contact opening 842 ′. In one implementation, dielectric 848 'is formed by oxidizing exposed surfaces of silicon to create a silicon dioxide layer.

At 850, a portion of dielectric 848 ′ formed at the bottom of source-body contact opening 842 ′ and an exposed portion of body region 826 ′ are etched by known anisotropic etching methods. The etching process is performed until the source-body contact opening 850 'partially extends into the source region 802' (ie, the substrate). The etching process leaves adjacent portions of the body region 826 'and source region 802' exposed, while leaving drift region 830 'and drain region 834' protected by dielectric layer 848 '. Source-body contact implants 844 'diffused laterally into the unexposed portions of body region 826' remain substantially after the etching process of the present invention. The remaining portion of the source-body contact injection forms a source-body contact 844 '.

At 852, a first metal 852 ′ is deposited below the source-body contact opening 850 ′ and reacts with the body region 826 ′ and the exposed portion of the source region 802 ′. In one implementation, titanium is sputtered in the openings and quickly thermally annealed to form titanium silicide (TiSi). Titanium silicide forms a second source-body contact 854 ', which couples with the first source-body contact to electrically couple the body region 826' to the source 802 '. At 854, the unreacted portion of titanium is etched along the dielectric-padded wall of the source-body contact opening 850 '.

At 856, a second dielectric layer is deposited in source-body contact opening 850 ′ to form source-body insulator region 856 ′. In one implementation, dielectric 856 'is deposited in opening 850' by a method such as decomposition of tetraethylorthosilicate (TEOS) or high density plasma fill (HDP).

At 862, photo-resist is deposited and patterned through known lithography processes to form a gate contact resistive layer (not shown). Gate contacts are formed in the peripheral region. As shown in FIG. 8D, at 864, the exposed portion of the gate insulator region 822 ′ is etched by known anisotropic etching methods to form gate contacts in the peripheral region (not shown). In one implementation, the ion etchant interacts with the gate oxide exposed by the gate contact resistive layer. The gate contact opening extends down to the gate region 820 ′. At 866, the gate contact resistive layer is removed using a suitable resist remover or resist remove process.

At 868, photo-resist is deposited and patterned by known lithography processes to form a drain contact resistive layer (not shown). At 870, the excess dielectric material and the third sacrificial oxide at the core are etched by known anisotropic etching methods to form drain contact openings (not shown). In one implementation, the ion etchant interacts with the extra dielectric material and the third sacrificial oxide to form a drain contact opening. The drain contact opening extends down to the drain region 834 '. At 872, the drain contact resistive layer is removed using a suitable resist remover or resist remove process (not shown).

At 874, a second metal layer is deposited on the wafer. In one implementation, a second metal layer, such as aluminum, is deposited by known methods such as sputtering. The metal layer covers the top of the drain region 834 ', the gate insulator region 856', and the source-body contact insulator region 856 '. The second metal layer extends down to the gate contact opening and is in electrical contact with the gate region, and extends down to the drain contact opening and is in electrical contact with the drain region 834 '. At 876, the second metal layer is patterned using a photo-resist mask and an optional etching method to form a gate contact layer (not shown) and drain contact layer 876 '.

At 882, fabrication proceeds to various back-end processes to form source contacts. Various processes typically include etching, deposition, doping, cleaning, annealing, passivation, cleaving, and the like.

10A-10D, a flow diagram of a method of fabricating a closed cell trench metal oxide semiconductor field effect transistor (TMOSFET) in accordance with another embodiment of the present invention is shown. A method of fabricating a closed cell TMOSFET according to another embodiment of the present invention is illustrated in FIGS. 11A-11O. As shown in FIGS. 10A and 11A, at 1002, the process begins with various initial processes such as cleaning, depositing, doping, etching, etc. on the substrate 1002 ′. In one implementation, the substrate 1002 'comprises silicon that is heavily doped with phosphorus (N +). The semiconductor substrate 1002 'will comprise the source region of the TMOSFET substantially at the end of the fabrication process.

At 1004, a first semiconductor layer 1004 ′ is epitaxially deposited over the substrate 1002 ′. In one implementation, the first semiconductor layer 1004 'includes large amounts of p-doped silicon (P +). Epitaxially deposited silicon may be doped by placing desired impurities such as boron into the epitaxial reaction chamber. Alternatively, the doping of the first semiconductor layer 1004 'may be obtained by high energy implantation with a p-type dopant such as boron.

At 1006, a second semiconductor layer 1006 ′ is epitaxially deposited on the first semiconductor layer 1004 ′. In one implementation, the second semiconductor layer comprises a small amount of n-doped (N-) silicon. Epitaxially deposited silicon can be doped by introducing desired impurities such as phosphorous or arsenic into the reaction chamber. Alternatively, the doping of the second semiconductor layer 1006 'may be obtained by high energy implantation of an n-type dopant, such as phosphorous or arsenic.

At 1008, a first sacrificial oxide layer 1008 ′ is formed on the second semiconductor layer 1006 ′. In one implementation, the sacrificial oxide layer 1008 'is formed by oxidizing the surface of the second semiconductor layer 1006'. At 1010, photo-resist is deposited and patterned by known lithography processes to form a gate trench resistive layer 1010 '.

At 1012, the exposed portions of the first sacrificial oxide layer 1008 ', the second semiconductor layer 1006', the first semiconductor layer 1004 'and the portion of the substrate 802' are known anisotropic etching methods (i.e., Dry etching). In one implementation, the ion etchant is formed with the sacrificial oxide layer 1008 ', the second semiconductor layer 1006', the first semiconductor layer 1004 'and the substrate 1002' exposed by the gate trench resistive layer 1010 '. Interact The etching process produces a plurality of trenches 812 'having a plurality of cells therein. The plurality of trenches 1012 'are formed to have a first portion of the substantially parallel structure and a second portion of the substantially vertical-parallel structure.

At 1014, gate trench resistive layer 1010 'is removed using a suitable resist remover or resist remove process. At 1016, a first dielectric layer 1016 ′ is formed on the walls of the plurality of trenches 1012 ′. In one implementation, dielectric layer 1016 'is produced by oxidizing exposed surfaces of silicon to form a silicon dioxide layer. The resulting dielectric layer 1016 'along the trench wall will form a first portion of the gate insulator region.

At 1018, a first polysilicon layer is deposited in the plurality of trenches. In one implementation, polysilicon is deposited in the trench by a method such as decomposition of silane (SiH ₄ ). Polysilicon may be doped with n-type impurities such as phosphorous or arsenic. Polysilicon may be doped by introducing impurities during the deposition process. At 1020, an etch back process is performed to remove excess polysilicon material and form gate region 1020 '. The polysilicon layer is etched back to achieve the desired separation / overlap between the gate region formed from the polysilicon layer in the trench and the subsequently formed body, drift and drain regions. In one implementation, excess polysilicon is removed by combining a chemical mechanical polishing (CMP) process and an anisotropic etching method.

Referring now to FIGS. 10B and 11E, in an optional process 1022, a second dielectric layer 1022 ′ is formed over the gate region 1020 ′. In one implementation, polysilicon of gate 1020 'is oxidized to form silicon dioxide. In an optional process 1024, a second polysilicon layer is deposited over dielectric layer 1022 ′ formed over gate 1020 ′. In an optional process 1026, another etch back process is used to form the super source region 1026 'from the second polysilicon layer.

At 1028, a third dielectric layer is deposited in the plurality of second trenches 812 ′. In one implementation, a dielectric is deposited in the trench by methods such as decomposition of tetraethylorthosilicate (TEOS) or high density plasma fill (HDP). At 824, excess dielectric material is removed to complete the gate insulator region. In one implementation, the excess dielectric is removed by a chemical mechanical polishing (CMP) process.

At 1032, the lower portion of the second semiconductor layer 1004 'is doped with p-type impurities. In one implementation, the doping process injects p-type impurities 1032 ', such as boron, to the bottom of the second semiconductor layer 1006'. In optional process 1034, thermal cycling is used to drive (ie, diffuse) the implanted impurities, forming body region 1035 '. Thermal circulation diffuses impurities in the first semiconductor layer 1004 'and implanted impurities in the lower portion of the second semiconductor layer 1006' from the process 1034 so that the body region 1035 'is formed of the first semiconductor layer 1004'. And from the bottom of the second semiconductor layer 1006 '.

At 1036, the top of second semiconductor layer 1006 'is n-doped to adjust the doping concentration of drift region 1036'. In one implementation, the doping process implants n-type impurities 1037 ', such as phosphorous or arsenic, on top of the second semiconductor layer 1006'. In an optional process 1038, a second thermal cycle is used to drive (ie, diffuse) the second implanted impurity, thereby forming a drift region 1036 ′.

At 1042, a second sacrificial oxide layer 1042 'is formed over the wafer. In one implementation, the sacrificial oxide layer is formed by oxidizing the wafer surface. As shown in FIGS. 10C and 11H, at 1046, photo-resist is deposited and patterned by known lithography processes to form a source-body contact opening resistive layer 1046 ′.

At 1048, exposed portions of second sacrificial oxide layer 1042 'and drift region 1036' are etched by known anisotropic etching methods. In one implementation, the ion etchant interacts with the second sacrificial oxide layer 1042 'and the drift region 1046' exposed by the source-body contact opening resistive layer 1046 '. The etching process forms a plurality of source-body contact openings 1048 '. Each source-body contact opening is disposed within a cell formed by a plurality of trenches 1012 ′.

At 1050, the exposed portion of the body region is p-doped in bulk to form source-body implant region 1050 '. In one implementation, the doping process injects p-type impurities 1049 ', such as boron, into the body region 1035'. Thermocycling may be used to drive the source-body implant 1050 'substantially to the exposed portion of the body region 1035'. A portion of the source-body implant 1050 'will laterally diffuse up to an adjacent unexposed portion of the body region 1035'.

At 1052, the source-body contact opening resistive layer 1046 'is removed using a suitable resist remover or resist remove process. At 1054, a fourth dielectric layer 1054 'is formed on the wall of the source-body contact opening 1048'. In one implementation, dielectric layer 1054 'is formed by oxidizing exposed surfaces of silicon to produce a silicon dioxide layer.

At 1056, a portion of the dielectric layer 1054 'formed at the bottom of the source-body contact opening 1048' and the exposed portion of the body region 1035 'are etched by known anisotropic etching methods. The etching process is performed until the source-body contact opening 1056 'partially extends to the substrate 1002'. The etching process leaves adjacent portions of the body region 1035 'and the source region 1002' exposed, while leaving the drift region 1036 'protected by the dielectric layer 1054'. A portion of the source-body contact implant 844 'diffused laterally into the unexposed portion of the body region 1035' remains substantially after the etching process of the present invention. The remaining portion of the source-body contact injection forms the first source-body contact 1050 '.

At 1058, a first metal layer 1060 ′ is deposited at the bottom of the source-body contact opening 1056 ′ and reacts with the body region 1035 ′ and the exposed portion of the substrate 1002 ′. In one implementation, titanium is sputtered in the openings and quickly thermally annealed to form titanium silicide (TiSi). Titanium silicide forms a second source-body contact 1060 ', which couples with the first source-body contact 1050' to electrically couple the body region 1035 'to the substrate 1002'. At 1060, the unreacted portion of titanium is etched along the dielectric-padded wall of the source-body contact opening. At 1062, a fifth dielectric layer is deposited in the source-body contact openings to form source-body insulator region 1064 '. In one implementation, a dielectric layer is deposited in source-body contact opening 1056 'using sub-atmosphere chemical vapor deposition (SACVD).

As shown in FIG. 10D, at 1068, photo-resist is deposited and patterned through known lithography processes to form a gate contact resistive layer (not shown). Gate contacts are formed in the peripheral region. At 1070, the exposed portion of the fifth dielectric layer and gate insulator region 1030 'is etched by a known anisotropic etching method (not shown). In one implementation, the ion etchant interacts with the gate oxide exposed by the gate contact resistive layer. The gate contact opening extends down to the gate region 1020 '. At 1072, the gate contact resistive layer is removed using a suitable resist remover or resist remove process (not shown).

At 1074, photo-resist is deposited and patterned by known lithography processes to form a drain contact resistive layer (not shown). At 1076, the exposed portion of the fifth dielectric layer is etched by known anisotropic etching methods. In one implementation, the ion etchant interacts with the fifth dielectric layer to form a drain contact opening. The drain contact opening extends down to the drift region 1036 '. At 1078, the top of the drift region is n-doped in bulk to form the drain region. In an optional process 1080, a third thermal cycle is used to drive (ie, diffuse) the implanted impurities to obtain the desired depth of the drain region 1080 '. At 1082, the drain contact resistive layer is removed using a suitable resist remover or resist remove process.

At 1084, a second metal layer is deposited on the wafer. In one implementation, a second metal layer, such as aluminum, is deposited by known methods such as sputtering. The metal layer covers the top of the drain, gate oxide, and source-body contact oxide regions and is in electrical contact with the drain regions. The second metal layer also extends down to the gate contact opening and is in electrical contact with the gate region. Then at 1086, the metal layer is patterned using a photo-resist mask and an optional etching method to form a gate contact layer (not shown) and drain contact layer 1086 '.

At 1088, fabrication proceeds in various back-end processes to form source contacts. Various processes typically include etching, deposition, doping, cleaning, annealing, passivation, cleaving, and the like.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to limit the invention to the precise form disclosed, and obviously, numerous modifications and variations will be possible by the above disclosure. The embodiments are selected and disclosed in order to best explain the principles of the invention and its practical application, whereby various embodiments vary in variety, suited to the particular use envisioned by others skilled in the art. To use. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims (39)

Source region; A plurality of gate regions disposed over the source region, the plurality of gate regions having a structure that is substantially elongated in parallel; A plurality of gate insulator regions, each of the plurality of gate insulator regions disposed around the corresponding one of the plurality of gate regions; A plurality of body regions disposed over the source region and between the plurality of gate insulator regions; A plurality of drift regions disposed over the plurality of body regions and between the plurality of gate insulator regions; And A striped cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising a plurality of drain regions disposed over the plurality of drift regions and between the plurality of gate insulator regions. The striped TMOSFET of claim 1, wherein the plurality of drain regions and the plurality of gate regions are disposed along a first side and the source region is disposed along a second side opposite to the first side. The method of claim 1, The source region comprises a semiconductor n-doped in bulk; The plurality of body regions comprises a p-doped semiconductor; The plurality of drift regions comprises a small n-doped semiconductor; The plurality of drain regions comprises a bulk n-doped semiconductor; The plurality of gate insulator regions comprises an oxide; Wherein said plurality of gate regions is a striped cell TMOSFET comprising a large quantity of n-doped semiconductors. The cell TMOSFET of claim 1, wherein the plurality of body regions are striped to be electrically coupled with the source region. The method of claim 1, A plurality of first source-body contacts electrically coupled with the plurality of body regions; A plurality of second source-body contacts electrically coupled between the plurality of first source-body contacts and over the source; And The striped cell TMOSFET further comprising a source-body contact insulator region that electrically isolates the first source-body contact and the second source-body contact from one or more of the plurality of drift regions and the plurality of drain regions. The method of claim 5, The plurality of first source-body contacts comprises a large amount of p-doped semiconductor; And wherein said plurality of second source-body contacts comprises silicide. The cell TMOSFET of claim 1, wherein the plurality of gate regions are striped to substantially overlap the plurality of body regions. The cell TMOSFET of claim 1, wherein the plurality of gate regions are striped with substantially overlapping the plurality of body regions and the plurality of drift regions. The cell TMOSFET of claim 1, wherein the plurality of gate regions are stripes that do not substantially overlap the plurality of drain regions. The semiconductor device of claim 1, further comprising a plurality of super source regions disposed on the plurality of gate regions, wherein the plurality of super source regions are formed to have a substantially parallel structure and are electrically coupled to the source regions. Striped cell TMOSFET. A method of manufacturing a striped cell trench metal-oxide-semiconductor field effect transistor (TMOSFET), Depositing a first semiconductor layer on a semiconductor substrate, wherein the first semiconductor layer is doped with a first type of impurity and the semiconductor substrate is doped with a second type of impurity; Depositing a second semiconductor layer on the first semiconductor layer; Etching a plurality of first trenches in the first semiconductor layer, the second semiconductor layer and a portion of the semiconductor substrate, the plurality of first trenches being substantially parallel to each other; Forming a first dielectric layer in the plurality of first trenches; Depositing a first polysilicon layer in the plurality of first trenches; Depositing a second dielectric layer in the plurality of first trenches on the first polysilicon layer; Doping the first semiconductor layer with the impurity of the first type; And Doping a portion of the second semiconductor layer, opposite the first semiconductor layer, to a first concentration with impurities of the second type. The method of claim 11, wherein depositing the first semiconductor layer comprises epitaxially depositing silicon heavily doped with boron. The method of claim 11, wherein depositing the second semiconductor layer comprises depositing silicon doped with a small amount of boron. 14. The method of claim 13, wherein the step of doping the first semiconductor layer with the impurity of the second type comprises implanting boron. The method of claim 11, wherein depositing the second semiconductor layer comprises epitaxially depositing silicon doped with a small amount of phosphorus or arsenic. 12. The method of claim 11, wherein the step of doping a portion of the second semiconductor layer opposite the first semiconductor layer with the impurity of the second type comprises implantation of phosphorus or arsenic. 12. The method of claim 11, further comprising doping the second semiconductor layer to a second concentration with impurities of the second type prior to doping the portion of the second semiconductor layer, wherein the first concentration is Greater than said second concentration. The method of claim 11, Etching a plurality of second trenches in the first semiconductor layer, the second semiconductor layer and a portion of the semiconductor substrate, wherein the plurality of second trenches are substantially parallel to each other and between the plurality of first trenches. Disposed in; Doping a portion of the first semiconductor layer near the plurality of second trenches; Forming silicide along the semiconductor substrate and the first semiconductor layer in the plurality of second trenches; And And depositing a third dielectric layer in the plurality of second trenches. The method of claim 18, wherein forming the silicide, Sputtering a metal film along the semiconductor substrate and the first semiconductor layer in the plurality of second trenches; And And thermal cycling the metal film, the semiconductor substrate, and the first semiconductor layer. The method of claim 11, Depositing a second polysilicon layer in the plurality of first trenches between the first polysilicon layer and the second dielectric layer; And And forming a fourth dielectric layer between the first polysilicon layer and the second polysilicon layer. Source region; A gate region disposed over the source region, wherein a first portion of the plurality of gate regions is formed as a substantially elongated structure, and a second portion of the plurality of gate regions is formed as a vertically-parallel elongated structure, Gate region; A gate insulator region, wherein the gate insulator region is disposed surrounding the gate region; A plurality of body regions disposed over the source region, between the gate insulator regions; A plurality of drift regions disposed between the gate insulator regions on the plurality of body regions; And A closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET), comprising a plurality of drain regions disposed over the plurality of drift regions, between the gate insulator regions. 22. The striped TMOSFET of claim 21, wherein the plurality of drain regions and the gate region are disposed along a first side and the source region is disposed along a second side opposite to the first side. The method of claim 21, The source region comprises a bulk n-doped semiconductor; The plurality of body regions comprises a p-doped semiconductor; The plurality of drift regions comprises a small n-doped semiconductor; The plurality of drain regions comprises a bulk n-doped semiconductor; The gate insulator region comprises an oxide; Wherein the gate region comprises a bulk n-doped semiconductor. The closed cell TMOSFET of claim 21, wherein the plurality of body regions are electrically coupled to the source region. The method of claim 21, A plurality of first source-body contacts electrically coupled to the plurality of body regions; A plurality of second source-body contacts electrically coupled between the plurality of source-body contacts and the source; And And a plurality of source-body contact insulator regions that electrically isolate the plurality of first source-body contacts and the plurality of second source-body contacts from one or more of the plurality of drift regions and the plurality of drain regions. Closed Cell TMOSFET. The method of claim 25, The plurality of first source-body contacts comprises a large amount of p-doped semiconductor, And the plurality of second source-body contacts comprises silicide. The closed cell TMOSFET of claim 21, wherein the gate region substantially overlaps the plurality of body regions. 22. The closed cell TMOSFET of claim 21, wherein the gate region substantially overlaps the plurality of body regions and the plurality of drift regions. 22. The closed cell TMOSFET of claim 21 wherein the gate region does not substantially overlap the plurality of drain regions. 22. The closed cell TMOSFET of claim 21, further comprising a super source region disposed over the gate region, wherein the plurality of super source regions are formed in a substantially parallel elongated structure and electrically coupled with the source region. A method of fabricating a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET), Depositing a first semiconductor layer on a semiconductor substrate, wherein the first semiconductor layer is doped with a first type of impurity and the semiconductor substrate is doped with a second type of impurity; Depositing a second semiconductor layer on the first semiconductor layer; Etching the first semiconductor layer, the second semiconductor layer, and a portion of the semiconductor substrate, wherein the first set of trenches is substantially parallel to each other and the second set of trenches is Substantially perpendicular-parallel to the first set of trenches of; Depositing a first polysilicon layer in the plurality of first trenches; Depositing a second dielectric layer in the plurality of first trenches on the first polysilicon layer; Doping the first semiconductor layer with the impurity of the first type; Doping the second semiconductor layer to a first concentration with the second type of impurities; And Doping a portion of the second semiconductor layer opposite the first semiconductor layer to a second concentration with impurities of the second type. 32. The method of claim 31, wherein the doping the first semiconductor layer comprises epitaxially depositing silicon doped with boron in bulk. 32. The method of claim 31, wherein depositing the second semiconductor layer comprises epitaxially depositing silicon doped with a small amount of phosphorus or arsenic. 32. The method of claim 31 wherein the step of doping the second semiconductor layer with the second type of impurity comprises implanting phosphorus or arsenic. 32. The method of claim 31 wherein the step of doping the first semiconductor layer with the impurity of the first type comprises implanting boron. 32. The method of claim 31, wherein the step of doping the portion of the semiconductor layer that is opposite the first semiconductor layer with the impurity of the second type comprises implanting phosphorus. The method of claim 31, wherein Etching a plurality of openings in the first semiconductor layer, the second semiconductor layer and a portion of the semiconductor substrate, the openings being disposed in each of a plurality of cells formed between the plurality of trenches; Doping a portion of the first semiconductor layer near the plurality of openings; Forming silicide along the semiconductor substrate and the first semiconductor layer in the plurality of openings; And And depositing a third dielectric layer in the plurality of openings. The method of claim 37, wherein forming the silicide, Sputtering a metal film along the semiconductor substrate and the first semiconductor layer in the plurality of openings; And Thermal cycling said metal film, said semiconductor substrate and said first semiconductor layer. The method of claim 31, wherein Depositing a second polysilicon layer in the plurality of first trenches between the first polysilicon layer and the second dielectric layer; And And forming a third dielectric layer between the first polysilicon layer and the second polysilicon layer.

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