JP2008529181A5 - - Google Patents

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Publication number
JP2008529181A5
JP2008529181A5 JP2007553585A JP2007553585A JP2008529181A5 JP 2008529181 A5 JP2008529181 A5 JP 2008529181A5 JP 2007553585 A JP2007553585 A JP 2007553585A JP 2007553585 A JP2007553585 A JP 2007553585A JP 2008529181 A5 JP2008529181 A5 JP 2008529181A5
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JP
Japan
Prior art keywords
request
read
dma
memory access
load
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Application number
JP2007553585A
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English (en)
Japanese (ja)
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JP2008529181A (ja
JP4931828B2 (ja
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Priority claimed from US11/050,040 external-priority patent/US7617338B2/en
Application filed filed Critical
Publication of JP2008529181A publication Critical patent/JP2008529181A/ja
Publication of JP2008529181A5 publication Critical patent/JP2008529181A5/ja
Application granted granted Critical
Publication of JP4931828B2 publication Critical patent/JP4931828B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007553585A 2005-02-03 2006-01-25 ライン・アクセスおよびワード・アクセスの結合を用いてメモリをアクセスするためのシステムおよび方法 Expired - Fee Related JP4931828B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/050,040 2005-02-03
US11/050,040 US7617338B2 (en) 2005-02-03 2005-02-03 Memory with combined line and word access
PCT/EP2006/050433 WO2006082154A2 (en) 2005-02-03 2006-01-25 System and method for a memory with combined line and word access

Publications (3)

Publication Number Publication Date
JP2008529181A JP2008529181A (ja) 2008-07-31
JP2008529181A5 true JP2008529181A5 (https=) 2008-11-27
JP4931828B2 JP4931828B2 (ja) 2012-05-16

Family

ID=36097154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007553585A Expired - Fee Related JP4931828B2 (ja) 2005-02-03 2006-01-25 ライン・アクセスおよびワード・アクセスの結合を用いてメモリをアクセスするためのシステムおよび方法

Country Status (8)

Country Link
US (1) US7617338B2 (https=)
EP (1) EP1849083B1 (https=)
JP (1) JP4931828B2 (https=)
CN (1) CN101111828B (https=)
AT (1) ATE415664T1 (https=)
DE (1) DE602006003869D1 (https=)
TW (1) TWI362591B (https=)
WO (1) WO2006082154A2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7681014B2 (en) * 2005-02-04 2010-03-16 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US8015323B2 (en) * 2006-02-28 2011-09-06 Infineon Technologies Ag Acquisition of data and autonomous transfer of data through communication interface in automotive system
US20080201312A1 (en) * 2007-01-17 2008-08-21 Encirq Corporation Systems and methods for a devicesql parallel query
JP4356030B2 (ja) * 2007-05-17 2009-11-04 ソニー株式会社 情報処理装置および方法
US7941574B2 (en) * 2008-08-11 2011-05-10 International Business Machines Corporation CKD partial record handling
US7870309B2 (en) * 2008-12-23 2011-01-11 International Business Machines Corporation Multithreaded programmable direct memory access engine
US7870308B2 (en) * 2008-12-23 2011-01-11 International Business Machines Corporation Programmable direct memory access engine
JP6146128B2 (ja) * 2013-05-20 2017-06-14 ヤマハ株式会社 データ処理装置
US9842630B2 (en) * 2013-10-16 2017-12-12 Rambus Inc. Memory component with adjustable core-to-interface data rate ratio
CN115794376A (zh) * 2022-10-31 2023-03-14 东风汽车集团股份有限公司 数据传输处理装置、方法、控制装置以及可读存储介质

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0288649B1 (en) * 1987-04-22 1992-10-21 International Business Machines Corporation Memory control subsystem
US4918587A (en) * 1987-12-11 1990-04-17 Ncr Corporation Prefetch circuit for a computer memory subject to consecutive addressing
US4929246A (en) * 1988-10-27 1990-05-29 C. R. Bard, Inc. Method for closing and sealing an artery after removing a catheter
US5446845A (en) * 1993-09-20 1995-08-29 International Business Machines Corporation Steering logic to directly connect devices having different data word widths
US5669013A (en) * 1993-10-05 1997-09-16 Fujitsu Limited System for transferring M elements X times and transferring N elements one time for an array that is X*M+N long responsive to vector type instructions
US5784700A (en) * 1994-12-12 1998-07-21 Texas Instruments Incorporated Memory interface with address shift for different memory types
US7272703B2 (en) * 1997-08-01 2007-09-18 Micron Technology, Inc. Program controlled embedded-DRAM-DSP architecture and methods
US6351784B1 (en) 1998-12-28 2002-02-26 International Business Machines Corp. System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction
US6341318B1 (en) * 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US7386671B2 (en) * 2000-06-09 2008-06-10 Texas Instruments Incorporated Smart cache
EP1182564A3 (en) * 2000-08-21 2004-07-28 Texas Instruments France Local memory with indicator bits to support concurrent DMA and CPU access
US6775727B2 (en) * 2001-06-23 2004-08-10 Freescale Semiconductor, Inc. System and method for controlling bus arbitration during cache memory burst cycles
JP2003044354A (ja) * 2001-07-26 2003-02-14 Matsushita Electric Ind Co Ltd メモリ制御装置
US6920510B2 (en) * 2002-06-05 2005-07-19 Lsi Logic Corporation Time sharing a single port memory among a plurality of ports

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