JP2008506247A - Semiconductor device module having flip chip device on common lead frame - Google Patents

Abstract

In a semiconductor device module, circuit board space is secured and thermal management is improved.
The semiconductor portion of the circuit includes a plurality of flip chip devices arranged in a planar manner within a common housing. The plurality of flip chip devices are connected to each other without using wire bonding, and the common housing has a package structure that includes a connection portion and at least one web portion, whereby Helps to manage the heat generated by the plurality of flip chip devices and connects the flip chip devices to each other. Passive devices in the circuit can also be arranged in a plane within the common housing.
[Selection] Figure 3

Description

  The present invention relates to a module comprising a flip chip device forming at least a semiconductor part of a circuit.

  Many types of electrical circuits such as DC-DC converters, synchronous converters, etc. require a large number of semiconductor components such as MOSFETs and ICs. Such circuit components are provided within the portable electronic device, which are typically housed separately and mounted separately on a support board. These separately housed components take up board space and each component generates heat. If the component is near other components, such as a microprocessor, this component may interfere with the operation of the microprocessor.

  Conventionally, at least two different methods have been implemented in order to solve the two problems of generating such heat and occupying the substrate space.

  One method is to arrange various semiconductor components in a planar manner in a single housing. FIG. 1 shows an example of a circuit diagram including semiconductor components arranged in a plane on a single substrate. This FIG. 1 was originally shown as FIG. 2 in US Pat. No. 6,388,319.

  FIG. 1 shows a synchronous buck converter circuit having an N-channel MOSFET 4 as a switching device, an N-channel synchronous MOSFET 5 in parallel for synchronous rectification, and a Schottky diode 6.

  These N-channel MOSFET 4, N-channel MOSFET 5, and Schottky diode 6 are arranged in a plane in the common housing 7. However, the control circuit 8 connected to the gates of the MOSFETs 4 and 5 is not accommodated in the common housing 7 described above. Since the source (top) of the die 4 is connected to the drain (bottom) of the die 5, it was necessary to insulate the die 5 from the substrate and wire bonds. Since the control circuit 8 must also be insulated from the substrate, the control circuit 8 was separate.

  Other patents that implement a method for placing semiconductor components in a planar manner in a common housing include U.S. Pat.Nos. Mention No. 6,696,321. Importantly, however, in any of the reference examples cited above, wire bonding is widely used to make the necessary connections between semiconductor components, but such wire bonding reduces resistance and inductance. growing. Further, mounting these components in a common housing reduces the thermal effects of the components compared to housing the components separately, but it is desirable to further improve thermal management.

  A second way to solve the problem of occupying board space and improving thermal management is to stack the dies or place them up and down and store them in a common housing. Such methods are exemplified in US Pat. Nos. 5,770,480, 6,798,044 and 6,858,922. Such a method requires a larger substrate space than the planar arrangement method. Furthermore, wire bonding between the dies can be omitted. However, in such a method, the operation of one die may cause the thermal effect imparted to other dies placed thereon to be greater than in the planar placement method.

  In view of the above-mentioned problems and matters discovered by examining the related technology, the present invention has several objects.

  A first object of the present invention is to arrange semiconductor components in a flat shape in a common housing in order to secure a circuit board space.

  A second object of the present invention is to eliminate the need for wire bonding and to provide such a planar arrangement for connection between the various dies in the common housing.

  The third object of the present invention is to arrange the dies in a planar manner in a common housing, which has better thermal management than the conventional planar arrangement of the dies than the stacked dies.

  The present invention includes a plurality of flip chip devices disposed on a common lead frame or other circuit board in a substantially planar manner without superimposing one flip chip device on another flip chip device. Yes. Connection between flip chip devices is performed without using wire bonding. Connections between at least some of the flip chip devices can be obtained by placing the dies in a planar manner, or by stacking the dies in a common housing, or placing them separately above and below, as is conventional. Rather than improve thermal management.

  Thus, for the buck converter circuit, the control FET can be a top drain MOSFET of the type disclosed in US Provisional Patent Application No. 60 / 539,549, filed Jan. 26, 2004. In this case, a drain and a gate are provided at the top of the die, and the drain and gate contact the lead frame and source at the top when the die is repeated.

  The synchronous FET can be the DirectFET ™ type disclosed in US Pat. No. 6,624,522. Here, the drain is provided at the top of the die and the source and gate are provided at the bottom of the die. Therefore, the FET can be connected to the source of the top drain FET by a T-PAC type mounting structure as disclosed in US Patent Publication No. 2004 / 0061221A1.

  Other conventional vertical conductive device packages can also be used to connect the synchronous FET and the top drain FET. The IC is also a flip chip where the bottom can be connected to the gates of the control FET and the sync FET by traces patterned in the lead frame. Therefore, there is no need for wire bonding.

  Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings.

  FIG. 2 shows a MOSFET with a top drain structure 15, a synchronous MOSFET 25 of DirectFET ™ type, a flip chip type IC 94 that controls MOSFETs 15 and 25 in PWM mode to obtain a constant output DC voltage, and an inductor. 1 is a circuit diagram of a buck converter circuit including a capacitor 10 and a capacitor 11. FIG.

  This buck converter circuit, sometimes known as a step-down converter, is commonly used to reduce the voltage. Therefore, the input voltage VIN is higher than the output voltage VOUT. MOSFET die 15, MOSFET die 25, and IC die 94 are arranged in a common housing 21. The dies 15, 25, and 94 are arranged in a planar shape on the lead frame 20 or other substrate that is thermally conductive or conductive.

  The thermal conductivity of the lead frame or other substrate ensures effective conduction of heat from the dies 15, 25, 94 towards one or more heat sinks (not shown) below the lead frame or other substrate. It is necessary to do.

  As will be described in more detail later, the electrical connection between the IC 94 and the MOSFETs 15 and 25 is enabled, and the conduction of the input voltage VIN and the output voltage V1 (see FIG. 2) to and from the common housing 21 is performed. In order to be possible, the conductivity of the lead frame or substrate is required. Examples of the substrate other than the thermally conductive and conductive lead frame include direct bond copper (DBC), printed circuit board (PCB), printed wiring board (PWB), and flexible circuit.

  Reference is now made to FIG. The IC 94 is directly bonded to the lead frame 20 or other substrate by solder or conductive epoxy (not shown). (The term flip chip as used herein refers to a chip whose surface is directly attached to a lead frame or other substrate without the use of wire bonding, and this flip chip refers to an appropriately manufactured bond chip. Have)

  The lead frame 20 has contact regions 30 and 31 that support the gate electrode 32 and the drain electrode 33 of the MOSFET 15, respectively. The lead frame 20 also has drain contacts 40 and 41 for contacting the source electrodes 43 and 44 of the MOSFET 25. Further, the lead frame 20 has a gate contact region 42 for receiving the gate electrode 45 of the MOSFET 25.

  The lead frame 20 or other substrate also has a trace 52, shown schematically, patterned in the lead frame or other substrate, connecting the IC 94 to the gate contact regions 30,42.

  The gate contact regions 32, 42 are then connected to the gate electrodes 32, 45 by solder or conductive epoxy 58 and solder or conductive epoxy 54, respectively. Similarly, referring to FIG. 5, source contact regions 40 and 41 are connected to source electrodes 43 and 44 by solder or conductive epoxy 62 and solder or conductive epoxy 60, respectively. The drain contact region 31 is connected to the drain electrode 33 via solder or conductive epoxy 66.

  The MOSFET 25 has a DirectFET (trademark) structure manufactured by International Rectifier. Thus, as shown in FIG. 5, MOSFET 25 is passivated on the surface 70 of the die, and the die is provided with source and gate electrodes 43, 44, 45, and source Short circuit between the electrode and the gate electrode is prevented and the electrodes are protected from moisture and other contaminants.

  The drain contact 74 of the MOSFET 25 is connected to the source electrode 78 of the MOSFET 15 through the conductive T-PACK type package structure 50, which schematically shows the output voltage V1 shown in FIG. 2 in FIG. It also provides a path for communicating to the leadframe 20 or other substrate that will be used.

  Furthermore, improved thermal management is performed by using a T-PACK type package 50. The T-PACK type package structure 50 includes a connectable portion 80 and a web portion 82. Web portion 82 is connected to lead frame 20 or other substrate by solder or conductive epoxy 84. The connectable portion 80 is connected to the drain contact 74 of the MOSFET 25 by conductive epoxy or solder 86, 88 (see FIG. 4), and is also connected to the source contact 78 by solder or conductive epoxy (not shown). It is connected. The connectable portion 80 and the web portion 82 are integrally formed so as to be an integral body.

  To configure the circuit of FIG. 2, both source contacts 40 and 41 are grounded as schematically shown in FIG. 5 and VIN is supplied to drain electricity 33 via lead frame 20 or other substrate. Has been. A T-PACK mounting structure 50 in which a housing 90 manufactured by molding a resin or other conventional non-conductive material is above the lead frame 20 or other substrate, and all other components of the circuit package Is housed.

  The connectable portion 80 of the T-PACK package structure covers the entire area of the lead frame 20 or other substrate, while the web portion 82 contacts a portion of the top surface of the lead frame 20 or other substrate. It should be noted that it has only sufficient dimensions. The contact portion is shown as a hatched area 92 in FIG. (The plan view of FIG. 3 is shown without the T-PACK type package structure 50 for the sake of simplicity.)

  Further, the lower surface of the connector portion 80 is above the upper surface of the flip chip IC 94, and the resin or other non-conductive material 90 electrically isolates the flip chip IC 94 from the T-PACK package structure 50. You should understand that. The extension of the connector portion 80 of the T-PACK package structure 50 over the entire area of the lead frame 20 or other substrate may be another planar structure, stack structure or spaced apart of the die within the common housing. The thermal management of the heat generated by the die can be improved compared to a structure that is vertically arranged in the state.

  Further, as disclosed in FIG. 8A of US Patent Publication No. 2004 / 0061221A1 and shown in FIG. 6 of the present specification, it protrudes into the top surface of the connector portion 80 of the T-PACK packaging structure 50. By providing the shape 96, thermal management can be further improved. Such ridges not only help dissipate more heat, but also help the connector 80 adhere better to the non-conductive material 90.

  It has been described above that only the MOSFET die 15, the MOSFET die 25, and the IC die 95 are arranged in a planar shape on the lead frame 20 or other substrate. However, the back converter of FIG. It can easily be envisaged to also provide an inductor 10 for the circuit. In such a case, the inductor 10 is connected to the drain contact 74 of the MOSFET 25 by a trace formed in the lead frame 20 or another substrate, and further by a T-PACK type package structure or other package structure, and wire bonding is performed. Further portions of the circuit shown in FIG.

  Finally, the capacitor 11 can also be mounted on the lead frame 20, and this capacitor 11 is connected to the inductor 10 and the source contacts 40 and 41, and contacts the source electrodes 43 and 44 of the MOSFET 25 without performing wire bonding again. As such, appropriate traces can be patterned in the lead frame 20. The addition of the inductor 10 and the capacitor 11 to the lead frame 20 completes the formation of the entire buck converter circuit shown in FIG. 2 on one lead frame or another substrate.

  Although the above disclosure focuses on mounting the semiconductor portion of a conventional buck converter circuit in a common housing in a planar shape, the present invention is not limited to such a specific structure. Absent. On the contrary, the present invention can be applied to planarly arrange flip chip devices, which are semiconductor parts of various circuits, in a common housing without requiring wire bonding. Furthermore, the use of a T-PACK package structure for the package can improve the thermal management of the package.

  Of course, the leadframe 20 or other substrate to prevent shorting between the contacts of the semiconductor components of the circuit, the T-PACK, or other package structure, and passive devices on the leadframe 20 or other substrate. It should be understood that there are insulating barriers or layers within as needed.

  Although the present invention has been described with reference to specific embodiments of the present invention, other variations and modifications and other uses will become apparent to those skilled in the art. Accordingly, the invention is not limited by the specific disclosures but only by the claims.

This application claims the rights based on US Provisional Patent Application No. 60 / 576,703 filed on June 3, 2004, the entire contents of which are hereby incorporated by reference. Incorporated as.

It is a circuit diagram which shows the conventional structure of the semiconductor part of the circuit provided in the common housing. FIG. 3 is a circuit diagram of the present invention showing a semiconductor portion of a circuit disposed within a common housing. FIG. 3 is a plan view of an embodiment of the present invention corresponding to the components of the circuit shown in FIG. 2 as contained within a common housing. FIG. 4 is a sectional view of FIG. 3 taken along section line 4-4 in FIG. 3. FIG. 5 is a sectional view of FIG. 3 taken along section line 5-5 in FIG. 3, and also schematically shows the flow of current inside the circuit, corresponding to the circuit shown in FIG. 2. It is a partial side view of T-PACK package structure which shows the protrusion in a top direction.

Explanation of symbols

8 Control Circuit 10 Inductor 11 Capacitor 15 Drain Structure 20 Lead Frame 21 Common Housing 25 Synchronous MOSFET
30, 31 Contact region 32 Gate electrode 33 Drain electrode 40, 41 Drain contact 43, 44 Source electrode 45 Gate electrode 52 Trace 54, 60, 62 Conductive epoxy

Claims (20)

  At least a semiconductor portion of a circuit disposed in a common housing including a plurality of flip chip dies, wherein the plurality of flip chip dies are connected to each other without using wire bonding, and the common housing includes a package structure At least the semiconductor part of the circuit.   2. At least a semiconductor portion of a circuit disposed in a common housing according to claim 1, comprising a lead frame or other thermally conductive and conductive substrate on which the plurality of flip chip dies are mounted.   The at least semiconductor portion of a circuit disposed within the common housing of claim 1, wherein the common housing includes a resin or other non-conductive material that encapsulates the package structure.   The at least semiconductor portion of the circuit disposed within the common housing of claim 1, wherein the plurality of flip chip dies include at least one IC.   The at least semiconductor portion of the circuit disposed within the common housing of claim 1, wherein the plurality of flip chip dies includes at least one MOSFET.   The at least semiconductor portion of the circuit disposed within the common housing of claim 1, wherein the circuit is a buck converter circuit.   The package structure includes a connectable portion and at least one web portion, the connectable portion disposed within a common housing that connects the plurality of flip chip dies together. At least the semiconductor part of the circuit.   The common portion of claim 1, wherein the connectable portion has a top surface that covers the entire surface of a lead frame or other thermally conductive and conductive substrate with the plurality of flip chip dies mounted thereon. At least a semiconductor portion of a circuit disposed within the housing.   9. At least a semiconductor portion of a circuit disposed within a common housing according to claim 8, wherein the top surface has a ridge.   The at least semiconductor portion of the circuit disposed within the common housing of claim 1, wherein the plurality of flip chip dies are disposed in a planar shape.   The at least semiconductor portion of the circuit disposed within the common housing of claim 1, wherein the circuit further comprises at least one passive device disposed within the common housing.   The at least one passive device is selected from the group consisting of at least one resistor, at least one capacitor, and at least one inductor. 12. At least a semiconductor portion of a circuit disposed within the common housing of claim 11. In a semiconductor device comprising first and second MOSFET dies and a control IC die for controlling the first and second MOSFETs all contained in a common package,
The common package has a conductive mounting surface, the first MOSFET die has a source electrode and a gate electrode on one surface, and a drain electrode on the opposite surface, and the second MOSFET die has 1 Having a drain electrode and a gate electrode on one surface and a source electrode on the opposite surface, wherein the first die and the second die are electrically conductive to the conductive mounting surface at their source and gate and drain electrodes. Semiconductor devices that are fixedly fixed and further spaced laterally from one another.   The device of claim 13, wherein the IC die is a flip chip IC having one surface that is conductively secured to the conductive mounting surface.   The common package further includes a package structure, the package structure including a connectable portion and a web portion, the connectable portion connecting the first MOSFET and the second MOSFET die to each other. The device of claim 13.   The device according to claim 15, wherein a ridge is provided on a top surface of the connectable portion.   The device of claim 15, wherein the common package further includes a resin or other non-conductive material that encapsulates the package structure.   The device of claim 13, wherein the first and second MOSFET dies and the control IC die are arranged in a planar shape.   The device of claim 13, further comprising at least one passive device included in the common package.   The at least one passive device is selected from the group consisting of at least one resistor, at least one capacitor, and at least one inductor. The device of claim 19.

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