JP2008300718A - Semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for which the covering property of an insulating layer at a through-hole bottom part is improved and the decline of electric insulation and connection defects are improved in the through wiring part of a semiconductor substrate. <P>SOLUTION: On the surface of the semiconductor substrate 2 having a through-hole 3, a first insulating layer 4 having the opening 4a of the same diameter as the through-hole 3 is put, and a first wiring layer 5 is formed on it covering the opening 4a. Also, a second insulating layer 6 is put inside the through-hole 3 and on the back surface of the semiconductor substrate 2. The second insulating layer 6 is formed so as to be inscribed in the first wiring layer 5 and has the opening 6a of a diameter smaller than the opening 4a of the first insulating layer 4 in the inscribed part. Further, a second wiring layer 7 is filled and formed inside the through-hole 3, and the second wiring layer 7 is inscribed in the first wiring layer 5 through the opening 6a of the second insulating layer 6. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a through connection portion for electrically connecting wirings on the front and back surfaces of a semiconductor substrate and a method for manufacturing the semiconductor device.

  In memory devices using semiconductor integrated circuits, it has been proposed to stack memory chips (semiconductor chips) in multiple stages in order to increase the memory capacity. A through-hole penetrating the front and back surfaces is formed in the semiconductor chip, a conductor layer is formed in the through-hole, and metal bumps electrically connected to the conductor layer are provided on the back surface of the chip. Metal bumps of the upper semiconductor chip are bonded to metal pads formed on the surface of the lower semiconductor chip, and thus the integrated circuit portion of the upper memory chip and the integrated circuit portion of the lower memory chip are electrically connected. Yes.

  As a semiconductor device having such a through-connection portion, conventionally, a through hole is formed by etching from the back surface of the semiconductor substrate, and a conductive portion formed in the through hole electrically connects the wiring layer between the front surface and the back surface of the semiconductor substrate. Devices having a structure in which they are connected are proposed (see, for example, Patent Document 1 and Patent Document 2).

  A conventional semiconductor device will be described below. In the conventional semiconductor device 100 shown in FIG. 10, a semiconductor substrate 101 made of silicon has a through hole 102 penetrating the front and back surfaces, and an insulating film 103 extends from the inner wall surface of the through hole 102 to the back surface of the semiconductor substrate 101. Is formed. A through wiring portion 104 is formed in the through hole 102. The through wiring portion 104 electrically connects a wiring layer 105 formed on the front surface side of the semiconductor substrate 101 and an external terminal (solder ball) 106 formed on the back surface side. An insulating layer 107 is formed on the surface of the semiconductor substrate 101, and a wiring layer 105 is formed on the insulating layer 107. A semiconductor device such as an image sensor is formed on the surface side of the semiconductor substrate 101 by an integrated circuit. Furthermore, on the back surface of the semiconductor substrate 101, an external terminal 106 connected to the through wiring portion 104, an insulating film (back surface side insulating film) 103, and a back surface side protective film 108 are provided. The external terminal 106 is formed so as to protrude outward.

In this semiconductor device 100, the through hole 102, the opening 107a of the insulating layer 107, and the opening of the insulating film 103 have the same shape and the same diameter, and are formed as follows. That is, the through-hole 102 is formed by etching the semiconductor substrate 101 from the back side thereof using a predetermined mask pattern (not shown) until the insulating layer 107 is exposed, and then the through-hole thus formed is formed. The opening 107a of the insulating layer 107 is formed by etching the insulating layer 107 with an etching method having a larger selection ratio than the semiconductor substrate 101 using the mask 102 as a mask. Furthermore, after forming the insulating film 103 on the inner wall surface of the through hole 102 and the back surface of the semiconductor substrate 101 so that the film thickness on the back surface side of the semiconductor substrate 101 is larger than the bottom surface of the through hole 102, The insulating film 103 formed on the back side is etched back using anisotropic etching. Thus, the insulating film 103 on the bottom surface of the through hole 102 is removed, and the wiring layer 105 is exposed.
US Pat. No. 5,229,647 Patent 3,186,941

  However, in the conventional semiconductor device 100 manufactured by such a method, an opening is formed in the insulating film 103 on the bottom surface of the through hole 102 in order to etch back using the opening 103a on the back surface side of the insulating film 103 as an etching mask. In this case, the etching tends to spread in the lateral direction. As a result, when the through hole 102 of the semiconductor substrate 101 is viewed from the back surface side, it is easy to exhibit a so-called notch shape in which the opening end on the wiring layer 105 side (front surface side) of the insulating film 103 is hidden. For this reason, the insulating film 103 is unlikely to remain in the notch-shaped portion, and not only does it easily cause an insulation failure, but also the through wiring portion 104 is difficult to be formed. Therefore, there is a problem in that a connection failure occurs between the wiring layers, yield decreases, and electrical and mechanical reliability decreases.

  The present invention has been made to solve these problems. In the through wiring portion of the semiconductor substrate, the covering property of the insulating layer at the bottom of the through hole is improved, and the deterioration of electrical insulation and poor connection are improved. It is an object of the present invention to provide a manufactured semiconductor device and a method for manufacturing such a semiconductor device.

  A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate, a through-hole provided through the first surface and the second surface of the semiconductor substrate, and a first surface of the semiconductor substrate. A first insulating layer having an opening on the opening on the first surface side of the through hole, and a first conductor provided on the first insulating layer so as to cover the opening And an opening on the first surface side of the through hole that is inscribed in the first conductor layer and provided on the second surface of the semiconductor substrate from the inner wall surface of the through hole. A second insulating layer having an opening smaller in diameter than the opening of the first insulating layer; and the second insulating layer in the through hole and on the second surface of the semiconductor substrate. And a second conductor layer inscribed in the first conductor layer through the opening of the second insulating layer.

  A semiconductor device according to a second aspect of the present invention includes a semiconductor substrate, a first surface of the semiconductor substrate, a through hole provided through the second surface, and a first surface of the semiconductor substrate. A first insulating layer having an opening on the opening on the first surface side of the through hole, and a first conductor provided on the first insulating layer so as to cover the opening And an opening on the first surface side of the through hole that is inscribed in the first conductor layer and provided on the second surface of the semiconductor substrate from the inner wall surface of the through hole. A second insulating layer having an opening smaller in diameter than the opening of the first insulating layer; and the second insulating layer in the through hole and on the second surface of the semiconductor substrate. A third insulating layer having an opening having the same diameter coaxially as the opening of the second insulating layer, the inside of the through hole, and the first of the semiconductor substrate; A second conductor layer inscribed in the first conductor layer through the openings of the second and third insulation layers, connected to the third insulation layer on the surface of the second insulation layer; It is characterized by providing.

  A semiconductor device according to a third aspect of the present invention includes a semiconductor substrate, a through-hole provided through the first surface and the second surface of the semiconductor substrate, and a first surface of the semiconductor substrate. A first insulating layer having an opening on the opening on the first surface side of the through hole, and a first conductor provided on the first insulating layer so as to cover the opening And an opening on the first surface side of the through hole that is inscribed in the first conductor layer and provided on the second surface of the semiconductor substrate from the inner wall surface of the through hole. A second insulating layer having an opening smaller in diameter than the opening of the first insulating layer; and the second insulating layer in the through hole and on the second surface of the semiconductor substrate. A third insulating layer coaxially having an opening having a smaller diameter than the opening of the second insulating layer, the inside of the through hole, and the semiconductor substrate; And a second conductor layer inscribed in the first conductor layer through the opening of the third insulator layer, which is provided on the third insulator layer on the second surface. It is characterized by that.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating layer on a first surface of a semiconductor substrate; and forming a first conductor layer on the first insulating layer. Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, exposing the first insulating layer on the first surface side of the through hole, and Forming an opening in the first insulating layer exposed on the first surface side of the through hole to expose the first conductor layer; and on the exposed first conductor layer and the Forming a second insulating layer on the second surface of the semiconductor substrate from the inner wall surface of the through hole, and the second insulating layer formed on the exposed first conductor layer; Forming an opening having a smaller diameter than the opening of the first insulating layer and exposing the first conductor layer again; and the second insulating layer in the through hole. The first conductive layer is inscribed through the opening of the second insulating layer over the second insulating layer on the second surface of the semiconductor substrate from above the layer. And a step of forming two conductor layers.

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating layer on a first surface of a semiconductor substrate; and forming a first conductor layer on the first insulating layer. Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, exposing the first insulating layer on the first surface side of the through hole, and Forming an opening in the first insulating layer exposed on the first surface side of the through hole to expose the first conductor layer; and on the exposed first conductor layer and the Forming a second insulating layer on the second surface of the semiconductor substrate from the inner wall surface of the through hole; forming a third insulating layer on the second insulating layer in the through hole; Forming the third insulating layer on the second insulating layer on the second surface of the semiconductor substrate, and forming the third insulating layer in the through hole. A hole having a smaller diameter than the through hole is formed in the insulating layer, and at the same time, an opening having the same diameter as the hole is connected to the second insulating layer formed on the first surface side of the through hole, A step of exposing the first conductor layer; and the third insulation from the third insulating layer in the through hole to the third insulating layer on the second surface of the semiconductor substrate. Forming a second conductor layer so as to be inscribed in the exposed first conductor layer through a hole in the layer and an opening in the second insulating layer.

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating layer on a first surface of a semiconductor substrate; and forming a first conductor layer on the first insulating layer. Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, exposing the first insulating layer on the first surface side of the through hole, and Forming an opening in the first insulating layer exposed on the first surface side of the through hole to expose the first conductor layer; and on the exposed first conductor layer and the Forming a second insulating layer on the second surface of the semiconductor substrate from the inner wall surface of the through hole, and the second insulating layer formed on the exposed first conductor layer; Forming an opening having a smaller diameter than the opening of the first insulating layer and exposing the first conductor layer again; and the second insulating layer in the through hole. Inscribed in the exposed first conductor layer through the opening of the second insulating layer over the second insulating layer on the second surface of the semiconductor substrate from above the layer, and third And forming a hole having a diameter smaller than the opening of the second insulating layer in the third insulating layer in the through hole coaxially with the opening of the second insulating layer. And exposing the first conductor layer and over the third insulating layer on the second surface of the semiconductor substrate from the third insulating layer in the through hole. And a step of forming a second conductor layer so as to be inscribed in the exposed first conductor layer through the opening of the third insulating layer.

  According to the semiconductor device according to the first aspect of the present invention and the method for manufacturing the semiconductor device according to the fourth aspect, the opening of the second insulating layer is hidden when viewed from the second surface of the semiconductor substrate. The so-called notch shape is not exhibited, the insulation of the second insulating layer is improved, and the formation of the second conductor layer constituting the through wiring portion is facilitated. Therefore, a semiconductor device with improved yield and good electrical and mechanical reliability can be obtained.

  According to the semiconductor device according to the second aspect of the present invention and the method of manufacturing the semiconductor device according to the fifth aspect, the insulating property of the second insulating layer is the same as in the first aspect and the fourth aspect. The improved and easy formation of the second conductor layer constituting the through wiring portion is facilitated, and the yield is improved, and a semiconductor device having good electrical and mechanical reliability can be obtained. In addition, since both the inner wall surface of the through hole and the second surface of the semiconductor substrate are covered with the insulating layer in which the second insulating layer and the third insulating layer are laminated, the electrical reliability is further improved. .

  According to the semiconductor device according to the third aspect of the present invention and the method for manufacturing the semiconductor device according to the sixth aspect, the insulating property of the second insulating layer is the same as in the second and fifth aspects. The improved and easy formation of the second conductor layer constituting the through wiring portion is facilitated, the yield is improved, and a semiconductor device excellent in electrical and mechanical reliability can be obtained. Further, the material constituting the second insulating layer is selected from materials having excellent adhesion in consideration only of the adhesion to the semiconductor substrate, and the material constituting the third insulating layer is the second material in the through hole. A material having excellent adhesion can be selected considering only the adhesion with the conductor layer. Therefore, the degree of freedom in material selection is greatly expanded and the mechanical reliability is further improved.

  Hereinafter, modes for carrying out the present invention will be described. In addition, although embodiment is described based on drawing in the following description, those drawings are provided for illustration and this invention is not limited to those drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention, and FIGS. 2A to 2H are cross-sectional views showing respective steps in the method for manufacturing the semiconductor device of the first embodiment. FIG.

  As shown in FIG. 1, a semiconductor device 1 according to the first embodiment includes a semiconductor substrate 2 made of silicon or the like, and the semiconductor substrate 2 has a surface (element region forming surface) which is a first surface thereof. And a through-hole 3 penetrating through the second surface is formed. The surface of the semiconductor substrate 2 is covered with a first insulating layer 4 having an opening 4 a having the same diameter as the through hole 3 on the top of the through hole 3. A first wiring layer 5 is formed. The first wiring layer 5 is formed so as to cover and close the opening of the through hole 3 and the opening 4 a of the first insulating layer 4. The inner wall surface of the through hole 3 and the back surface of the semiconductor substrate 2 are covered with a second insulating layer 6. The second insulating layer 6 is formed so as to be inscribed in the first wiring layer 5, and has an opening 6 a having a smaller diameter than the opening 4 a of the first insulating layer 4 in the inscribed portion.

  Further, the second wiring layer 7 is filled and formed in the through hole 3. The second wiring layer 7 is inscribed in the first wiring layer 5 through the opening 6 a of the second insulating layer 6 and on the second insulating layer 6 on the back surface of the semiconductor substrate 2 from the inside of the through hole 3. It is formed over. Furthermore, external terminals 8 are provided on the second wiring layer 7 on the back surface of the semiconductor substrate 2. On the back surface of the semiconductor substrate 2, on the second wiring layer 7 excluding the portion where the external terminals 8 are disposed and on the second wiring layer 7. A protective layer 9 is coated on the second insulating layer 6.

The semiconductor device 1 according to the first embodiment configured as described above is manufactured as follows. That is, first, in the first step shown in FIG. 2A, the first insulating layer 4 is formed on the surface (first surface) of the semiconductor substrate 2 by a CVD (Chemical Vapor Deposition) method, a spin coat method, a spray coat method, or the like. Form. The first insulating layer 4 is made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), SiOF (Fluorine-doped SiO ₂ ), porous SiOC (Carbon-doped SiO ₂ ), or the like.

  Next, in the second step shown in FIG. 2B, a first wiring layer 5 is formed on the first insulating layer 4 by sputtering, CVD, vapor deposition, plating, or the like. The first wiring layer 5 includes, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, etc.) or a structure in which a plurality of layers made of the above materials are laminated.

Next, in a third step shown in FIG. 2C, a through-hole 3 is formed by plasma etching using a mask (not shown) having a predetermined pattern from the back surface side of the semiconductor substrate 2. The first insulating layer 4 is exposed at the bottom portion. The through-hole 3 preferably has a cross section that tapers toward the first insulating layer 4. In the formation of the through-hole 3, plasma etching is performed by introducing an etching gas into the plasma so that the semiconductor substrate 2 is etched relatively larger than the first insulating layer 4. As the etching gas, for example, when the semiconductor substrate 2 is silicon (Si) and the first insulating layer 4 is a SiO ₂ film, a mixed gas of SF ₆ , O _2, and Ar is used.

Next, in a fourth step shown in FIG. 2D, the exposed portion of the first insulating layer 4 is removed by plasma etching, an opening 4a is formed in the first insulating layer 4, and the first wiring layer 5 is exposed. Let At this time, an etching gas (for example, the first insulating layer 4 is formed in the plasma) so that the first insulating layer 4 is etched relatively larger than the semiconductor substrate 2 and the first wiring layer 5. When the semiconductor substrate 2 is made of silicon and the first wiring layer 5 is made of TiN or Al with a SiO ₂ film, plasma etching is performed by introducing a mixed gas of C ₅ F ₈ , O ₂ and Ar).

Note that the third and fourth steps described above can be performed all at once without using a mask by laser etching. As the laser light source, for example, a YAG (yttrium, aluminum, garnet) laser, a UV (solid ultraviolet) laser, an excimer laser, a carbon dioxide gas (CO ₂ ) laser, or the like is used. The frequency band of YAG laser is 355 nm, the frequency band of UV laser is 213 nm and 266 nm (CLBO: cesium lithium triborate crystal), 355 nm (CBO: cesium triborate crystal, LBO: lithium triborate crystal), and the frequency band of excimer laser is 193 nm (ArF), 248 nm (KrF), 308 nm (XeCl), and 351 nm (XeF). When the semiconductor substrate 2 is silicon and the first insulating layer 4 is a SiO ₂ film, it is preferable to use a YAG laser having a frequency of 355 nm as a laser light source.

  Next, in the fifth step shown in FIG. 2E, the second insulating layer 6 is formed by CVD so as to cover the back surface of the semiconductor substrate 2 from the bottom surface (exposed portion of the first wiring layer 5) and the inner wall surface of the through hole 3. It is formed by a method, a spray coating method, a spin coating method, a film laminating method or the like. The second insulating layer 6 is made of, for example, silicon oxide, silicon nitride, polyimide resin, BCB (benzocyclobutene) resin, epoxy resin, or the like.

Next, in a sixth step shown in FIG. 2F, a mask (not shown) having a predetermined pattern is formed on the second insulating layer 6 formed so as to cover the first wiring layer 5 on the bottom surface portion of the through hole 3. The opening 6a having a smaller diameter than the opening 4a of the first insulating layer 4 is formed coaxially by plasma etching using the plasma etching, and the first wiring layer 5 is exposed again. In the formation of the opening 6a, an etching gas (for example, the second insulating layer 6 is formed in the plasma) so that the second insulating layer 6 is etched relatively larger than the first wiring layer 5. In the case where the first wiring layer 5 is composed of TiN and Al with a SiO ₂ film, plasma etching is performed by introducing a mixed gas of C ₅ F ₈ , O ₂ and Ar).

Further, the removal of the second insulating layer 6 and the formation of the opening 6a can be performed using a laser etching method without using a mask. As the laser light source, for example, a YAG laser, a UV laser, an excimer laser, a carbon dioxide (CO ₂ ) laser, or the like is used. In the case where the second insulating layer 6 is a resin film and an opening having a fine diameter is formed, it is preferable to use a UV laser having a frequency of 266 nm. Further, when the second insulating layer 6 is a resin film or glass film having photosensitivity, the opening 6a can be easily formed by lithography using a mask having a predetermined pattern.

  Next, in the seventh step shown in FIG. 2G, the second insulating layer 6 is formed over the second insulating layer 6 on the back surface of the semiconductor substrate 2 from the second insulating layer 6 in the through hole 3. A second wiring layer 7 is formed so as to be inscribed in the first wiring layer 5 through the opening 6a. The second wiring layer 7 is made of, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu). , Au, Ag, solder material, etc.), or a single layer made of conductive resin, or a structure in which a plurality of layers made of the above materials are laminated. The second wiring layer 7 is formed using a mask (not shown) having a predetermined pattern and filling the through holes 3 by sputtering, CVD, vapor deposition, plating, printing, or the like. To do.

  Thereafter, in an eighth step shown in FIG. 2H, external terminals 8 are formed on the second wiring layer 7, and on the second wiring layer 7 and the second insulating layer excluding the portion where the external terminals 8 are disposed. A protective layer 9 is formed on 6. The external terminal 8 is formed of, for example, a solder material, and the protective layer 9 is formed of a polyimide resin, an epoxy resin, or a solder resist material. Next, the semiconductor substrate 2 is cut with a cutting blade of a dicer. In this way, individual pieces of the semiconductor device 1 shown in FIG. 1 are obtained.

  In the semiconductor device 1 according to the first embodiment manufactured as described above, the second insulating layer 6 covered on the inner wall surface and the back surface of the through hole 3 is formed so as to be inscribed in the first wiring layer 5. The inscribed portion has an opening 6a having a smaller diameter than the opening 4a of the first insulating layer 4, and the second wiring layer 7 filled in the through hole 3 has the opening 6a having a small diameter. So that the portion of the opening 6a of the second insulating layer 6 is hidden when the semiconductor substrate 2 is viewed from the back side. Does not occur. For this reason, the insulation failure of the second insulating layer 6 is improved, and the second wiring layer 7 can be easily formed, the filling property is improved, and the electrical connectivity is improved. Therefore, a semiconductor device with improved yield and good electrical and mechanical reliability can be obtained.

  Next, another embodiment of the present invention will be described.

  FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention, and FIGS. 4A to 4I are cross-sectional views showing a method for manufacturing the semiconductor device of the second embodiment. . In these drawings, the same parts as those in FIGS. 1 and 2A to 2H are denoted by the same reference numerals.

  As shown in FIG. 3, the semiconductor device 21 of the second embodiment has a semiconductor substrate 2 made of silicon or the like, and the semiconductor substrate 2 is formed with a through hole 3 penetrating the front surface and the back surface. . The surface of the semiconductor substrate 2 is covered with a first insulating layer 4 having an opening 4a having the same diameter as that of the through hole 3 on the top of the through hole 3, on which the first wiring layer 5 is formed. Is formed so as to close the opening of the through hole 3 and the opening 4 a of the first insulating layer 4. A second insulating layer 6 is covered on the inner wall surface of the through hole 3 and the back surface of the semiconductor substrate 2. The second insulating layer 6 is formed so as to be inscribed in the first wiring layer 5, and has an opening 6 a having a smaller diameter than the opening 4 a of the first insulating layer 4 in the inscribed portion.

  A third insulating layer 22 is formed on the second insulating layer 6, and the second insulating layer 6 is covered with the third insulating layer 22 except for the opening 6 a portion. That is, the third insulating layer 22 has an opening having the same diameter as the opening 6 a of the second insulating layer 6 on the first wiring layer 5 side, and is not inscribed in contact with the first wiring layer 5. ing. Further, the second wiring layer 7 is filled in the through hole 3. The second wiring layer 7 is inscribed in the first wiring layer 5 through the opening 6 a of the second insulating layer 6, and extends from the inside of the through hole 3 to the back surface of the semiconductor substrate 2. Formed on top. Furthermore, external terminals 8 are provided on the second wiring layer 7 on the back surface of the semiconductor substrate 2, and the second wiring layer 7 and the third insulating layer 22 except for the portion where the external terminals 8 are disposed. Is covered with a protective layer 9.

The semiconductor device 21 of the second embodiment configured as described above is manufactured as follows. That is, first in the first step shown in FIG. 4A, a first insulating layer made of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), SiOF, porous SiOC, or the like is formed on the surface of the semiconductor substrate 2. 4 is formed by CVD, spin coating, spray coating, or the like.

  Next, in the second step shown in FIG. 4B, the first wiring layer 5 is formed on the first insulating layer 4 by sputtering, CVD, vapor deposition, plating, or the like. The first wiring layer 5 includes, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, etc.) or a structure in which a plurality of layers made of the above materials are laminated.

Next, in a third step shown in FIG. 4C, a through-hole 3 is formed by plasma etching using a mask (not shown) having a predetermined pattern from the back surface side of the semiconductor substrate 2 to form a first insulation. Layer 4 is exposed. The through-hole 3 preferably has a cross section that tapers toward the first insulating layer 4. In the formation of the through hole 3, an etching gas (for example, the semiconductor substrate 2 is made of silicon and the first insulating layer 4 is used in the plasma so that the semiconductor substrate 2 is etched larger than the first insulating layer 4. Is a SiO ₂ film, plasma etching is performed by introducing a mixed gas of SF ₆ , O _2, and Ar).

Next, in the fourth step shown in FIG. 4D, the exposed portion of the first insulating layer 4 is removed by plasma etching, an opening 4a is formed in the first insulating layer 4, and the first wiring layer 5 is exposed. Let At this time, an etching gas (for example, the first insulating layer 4 is a SiO ₂ film) in the plasma so that the first insulating layer 4 is largely etched compared to the semiconductor substrate 2 and the first wiring layer 5. When the semiconductor substrate 2 is made of silicon and the first wiring layer 5 is made of TiN or Al, plasma etching is performed by introducing a mixed gas of C ₅ F ₈ , O ₂ and Ar).

Note that the third and fourth steps described above can be performed all at once without using a mask by laser etching. As the laser light source, for example, a YAG laser, a UV laser, an excimer laser, a carbon dioxide (CO ₂ ) laser, or the like is used. When the semiconductor substrate 2 is silicon and the first insulating layer 4 is a SiO ₂ film, it is preferable to use a YAG laser having a frequency of 355 nm as a laser light source.

  Next, in the fifth step shown in FIG. 4E, a second method such as a CVD method, a spray coating method, a spin coating method, a film laminating method or the like is performed so as to cover the back surface of the semiconductor substrate 2 from the bottom surface and inner wall surface of the through hole 3. An insulating layer 6 is formed. The second insulating layer 6 is made of, for example, silicon oxide, silicon nitride, polyimide resin, BCB resin, epoxy resin, or the like.

  Next, in the sixth step shown in FIG. 4F, the third insulating layer 22 is formed by CVD, spray coating, spin coating so as to cover the second insulating layer 6 in the through hole 3 and on the back surface of the semiconductor substrate 2. It is formed by a coating method, a film laminating method or the like. The third insulating layer 22 is made of, for example, silicon oxide, silicon nitride, polyimide resin, BCB resin, epoxy resin, or the like, and may be formed by filling the through hole 3 completely, It is not necessary to fill completely.

Next, in a seventh step shown in FIG. 4G, the second insulating layer 6 formed on the first wiring layer 5 on the bottom surface of the through hole 3 and the inside of the through hole 3 are filled thereon. An opening 23 having a smaller diameter than the opening 4a of the first insulating layer 4 is formed coaxially on the formed third insulating layer 22 by plasma etching using a mask (not shown) having a predetermined pattern. Then, the first wiring layer 5 is exposed. In the formation of the opening 23, an etching gas (for example, in the plasma) is formed so that the third insulating layer 22 and the second insulating layer 6 are etched relatively larger than the first wiring layer 5. When the second insulating layer 6 is a SiO ₂ film and the third insulating layer 22 is a SiN _x film, and the first wiring layer 5 is composed of TiN and Al, C ₅ F ₈ and O ₂ Plasma etching is performed by introducing a mixed gas of Ar).

When the third insulating layer 22 is made of an organic resin such as polyimide resin, BCB resin, or epoxy resin, the second insulating layer 6 and the third insulating layer 22 are simultaneously formed using a laser etching method. It is desirable to remove and form the opening 23. When the laser etching method is used, the opening 23 can be formed without using a mask. As the laser light source, for example, a YAG laser, a UV laser, an excimer laser, a carbon dioxide (CO ₂ ) laser, or the like is used. When the second insulating layer 6 is a SiO ₂ film and the third insulating layer 6 is a resin film and the fine-diameter opening 23 is formed, it is preferable to use a UV laser having a frequency of 266 nm. Further, in the case where both the third insulating layer 22 and the second insulating layer 6 are resin films or glass films having photosensitivity, these films are simultaneously removed by lithography using a mask having a predetermined pattern, The opening 23 can be easily formed.

  Next, in the eighth step shown in FIG. 4H, the second insulating layer 6 is formed over the third insulating layer 22 on the back surface of the semiconductor substrate 2 from the third insulating layer 22 in the through hole 3. A second wiring layer 7 is formed so as to be inscribed in the first wiring layer 5 through the opening 6a. The second wiring layer 7 includes, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, solder material, etc.), or a single layer made of a conductive resin, or a structure in which a plurality of layers made of the above materials are laminated. The second wiring layer 7 is filled in the through hole 3 by a sputtering method, a CVD method, a vapor deposition method, a plating method, a printing method or the like using a mask (not shown) having a predetermined pattern. It is formed.

  Thereafter, in a ninth step shown in FIG. 4I, external terminals 8 are formed on the second wiring layer 7, and on the second wiring layer 7 and the third insulating layer excluding the portion where the external terminals 8 are disposed. A protective layer 9 is formed on 22. The external terminal 8 is formed of, for example, a solder material, and the protective layer 9 is formed of a polyimide resin, an epoxy resin, or a solder resist material. Next, the semiconductor substrate 2 is cut with a cutting blade of a dicer. Thus, individual pieces of the semiconductor device 21 shown in FIG. 3 are obtained.

  In the semiconductor device 21 of the second embodiment manufactured as described above, the second insulating layer 6 covered on the inner wall surface and the back surface of the through hole 3 is formed so as to be inscribed in the first wiring layer 5. The inscribed portion has an opening 6a having a smaller diameter than the opening 4a of the first insulating layer 4, and the second wiring layer 7 filled in the through-hole 3 has the opening 6a having a small diameter. So that the opening 6a portion of the second insulating layer 6 is hidden when the semiconductor substrate 2 is viewed from the back side. Does not occur. For this reason, the insulation failure of the second insulating layer 6 is improved, and the second wiring layer 7 can be easily formed, the filling property is improved, and the electrical connectivity is improved.

  The second insulating layer 6 is covered with the third insulating layer 22 except for the opening 6a, and the inner wall surface and the back surface of the through hole 3 of the semiconductor substrate 2 are both the second insulating layer 6. And the third insulating layer 22, the electrical reliability is further improved as compared with the first embodiment described above.

  FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention, and FIGS. 6A to 6J are cross-sectional views showing a method for manufacturing the semiconductor device of the third embodiment. . In these drawings, the same parts as those in FIGS. 3 and 4A to 4I are denoted by the same reference numerals.

  As shown in FIG. 5, the semiconductor device 31 of the third embodiment has a semiconductor substrate 2 made of silicon or the like, and a through hole 3 penetrating the front surface and the back surface is formed in the semiconductor substrate 2. . The surface of the semiconductor substrate 2 is covered with a first insulating layer 4 having an opening 4a having the same diameter as that of the through hole 3 on the top of the through hole 3, on which the first wiring layer 5 is formed. Is formed so as to close the opening of the through hole 3 and the opening 4 a of the first insulating layer 4. A second insulating layer 6 is covered on the inner wall surface of the through hole 3 and the back surface of the semiconductor substrate 2. The second insulating layer 6 is formed so as to be inscribed in the first wiring layer 5, and has an opening 6 a having a smaller diameter than the opening 4 a of the first insulating layer 4 in the inscribed portion.

  A third insulating layer 22 is formed on the second insulating layer 6. The third insulating layer 22 is inscribed with the first wiring layer 5, and has an opening 22 a having a smaller diameter than the opening 6 a of the second insulating layer 6 at the inscribed portion. Further, the second wiring layer 7 is filled in the through hole 3. The second wiring layer 7 is inscribed in the first wiring layer 5 through the opening 22 a of the third insulating layer 22, and extends from the through hole 3 to the back surface of the semiconductor substrate 2. Formed on top. Furthermore, external terminals 8 are provided on the second wiring layer 7 on the back surface of the semiconductor substrate 2, and the second wiring layer 7 and the third insulating layer 22 except for the portion where the external terminals 8 are disposed. Is covered with a protective layer 9.

  The semiconductor device 31 of the third embodiment configured as described above is manufactured as follows. That is, first, in the first step shown in FIG. 6A, a first insulating layer 4 made of silicon oxide, silicon nitride, SiOF, porous SiOC or the like is formed on the surface of the semiconductor substrate 2 by CVD or spin coating. It is formed by a method such as a spray coating method.

  Next, in a second step shown in FIG. 6B, the first wiring layer 5 is formed on the first insulating layer 4 by sputtering, CVD, vapor deposition, plating, or the like. The first wiring layer 5 includes, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, etc.) or a structure in which a plurality of layers made of the above materials are laminated.

Next, in a third step shown in FIG. 6C, a through-hole 3 is formed by plasma etching using a mask (not shown) having a predetermined pattern from the back surface side of the semiconductor substrate 2 to form a first insulation. Layer 4 is exposed. The through-hole 3 preferably has a cross section that tapers toward the first insulating layer 4. In the formation of the through hole 3, an etching gas (for example, the semiconductor substrate 2 is made of silicon and the first insulating layer 4 is used in the plasma so that the semiconductor substrate 2 is etched larger than the first insulating layer 4. Is a SiO ₂ film, plasma etching is performed by introducing a mixed gas of SF ₆ , O _2, and Ar).

Next, in the fourth step shown in FIG. 6D, the exposed portion of the first insulating layer 4 is removed by plasma etching, an opening 4a is formed in the first insulating layer 4, and the first wiring layer 5 is exposed. Let At this time, an etching gas (for example, the first insulating layer 4 is formed in the plasma) so that the first insulating layer 4 is etched relatively larger than the semiconductor substrate 2 and the first wiring layer 5. When the semiconductor substrate 2 is made of silicon and the first wiring layer 5 is made of TiN or Al with a SiO ₂ film, plasma etching is performed by introducing a mixed gas of C ₅ F ₈ , O ₂ and Ar).

Note that the third and fourth steps described above can be performed all at once without using a mask by laser etching. As the laser light source, for example, a YAG laser, a UV laser, an excimer laser, a carbon dioxide (CO ₂ ) laser, or the like is used. When the semiconductor substrate 2 is silicon and the first insulating layer 4 is a SiO ₂ film, it is preferable to use a YAG laser having a frequency of 355 nm as a laser light source.

  Next, in a fifth step shown in FIG. 6E, a second process is performed by a CVD method, a spray coating method, a spin coating method, a film laminating method or the like so as to cover the back surface of the semiconductor substrate 2 from the bottom surface and inner wall surface of the through hole 3. An insulating layer 6 is formed. The second insulating layer 6 is made of, for example, silicon oxide, silicon nitride, polyimide resin, BCB resin, epoxy resin, or the like.

Next, in a sixth step shown in FIG. 6F, a first pattern mask (not shown) is used for the second insulating layer 6 formed on the bottom surface of the through-hole 3 to perform first etching. An opening 6a having a smaller diameter than the opening 4a of the insulating layer 4 is formed coaxially, and the first wiring layer 5 is exposed again. In the formation of the opening 6a, an etching gas (for example, the second insulating layer 6 is formed of an SiO ₂ film) in the plasma so that the second insulating layer 6 is largely etched as compared with the first wiring layer 5. When the first wiring layer 5 is made of TiN or Al, plasma etching is performed by introducing a mixed gas of C ₅ F ₈ , O _2, and Ar).

Further, the opening 6a can be formed by removing the second insulating layer 6 by a laser etching method without using a mask. As the laser light source, for example, a YAG laser, a UV laser, an excimer laser, a carbon dioxide (CO ₂ ) laser, or the like is used. In the case where the second insulating layer 6 is a resin film and an opening having a fine diameter is formed, it is preferable to use a UV laser having a frequency of 266 nm. Further, when the second insulating layer 6 is a resin film or glass film having photosensitivity, the opening 6a can be easily formed by lithography using a mask having a predetermined pattern.

  Next, in the seventh step shown in FIG. 6G, the third insulating layer is inscribed in the first wiring layer 5 and covers the second insulating layer 6 in the through hole 3 and on the back surface of the semiconductor substrate 2. 22 is formed by CVD, spray coating, spin coating, film laminating, or the like. The third insulating layer 22 is made of, for example, silicon oxide, silicon nitride, polyimide resin, BCB resin, epoxy resin, or the like. The third insulating layer 22 may be formed by being filled so as to completely fill the inside of the through hole 3 or may not be completely filled.

Next, in an eighth step shown in FIG. 6H, the third insulating layer 22 is provided with an opening 23 having a smaller diameter than the opening 6a of the second insulating layer 6, and a mask having a predetermined pattern (not shown). Used and formed coaxially by plasma etching. Thus, the opening 22a is formed in the inscribed portion of the third insulating layer 22 with the first wiring layer 5, and the first wiring layer 5 is exposed from the opening 22a. In the formation of the opening 23 in the third insulating layer 22, an etching gas (for example, the third insulating layer 22) is included in the plasma so that the third insulating layer 22 is etched larger than the first wiring layer 5. When the insulating layer 6 is a SiO ₂ film and the first wiring layer 5 is made of TiN or Al, plasma etching is performed by introducing a mixed gas of C ₅ F ₈ , O _2, and Ar).

When the third insulating layer 22 is made of an organic resin such as a polyimide resin, a BCB resin, or an epoxy resin, it is desirable to form the opening 23 using a laser etching method. In the case of using a laser etching method, the third insulating layer 22 can be removed and the opening 23 can be formed without using a mask. As the laser light source, for example, a YAG laser, a UV laser, an excimer laser, a carbon dioxide (CO ₂ ) laser, or the like is used. When the third insulating layer 6 is a resin film and the fine-diameter opening 23 is formed, it is preferable to use a UV laser having a frequency of 266 nm. Furthermore, when the third insulating layer 22 is a resin film or glass film having photosensitivity, the opening 23 can be easily formed by removing it by lithography using a mask having a predetermined pattern.

  Next, in the ninth step shown in FIG. 6I, the opening of the third insulating layer 22 extends from the third insulating layer 22 in the through hole 3 to the third insulating layer 22 on the back surface of the semiconductor substrate 2. The second wiring layer 7 is formed so as to be inscribed in the first wiring layer 5 through 22a. The second wiring layer 7 includes, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, solder material, etc.), or a single layer made of a conductive resin, or a structure in which a plurality of layers made of the above materials are laminated. The second wiring layer 7 is filled in the through hole 3 by a sputtering method, a CVD method, a vapor deposition method, a plating method, a printing method or the like using a mask (not shown) having a predetermined pattern. It is formed.

  Thereafter, in a tenth step shown in FIG. 6J, external terminals 8 are formed on the second wiring layer 7, and the second wiring layer 7 and the third insulating layer excluding the portion where the external terminals 8 are disposed. A protective layer 9 is formed on 22. The external terminal 8 is formed of, for example, a solder material, and the protective layer 9 is formed of a polyimide resin, an epoxy resin, or a solder resist material. Next, the semiconductor substrate 2 is cut with a cutting blade of a dicer. Thus, individual pieces of the semiconductor device 31 shown in FIG. 5 are obtained.

  In the semiconductor device 31 of the third embodiment manufactured as described above, the second insulating layer 6 covered on the inner wall surface and the back surface of the through hole 3 is formed so as to be inscribed in the first wiring layer 5. The inscribed portion has an opening 6a having a smaller diameter than the opening 4a of the first insulating layer 4, and the second wiring layer 7 filled in the through-hole 3 has the opening 6a having a small diameter. So that the opening 6a portion of the second insulating layer 6 is hidden when the semiconductor substrate 2 is viewed from the back side. Does not occur. For this reason, the insulation failure of the second insulating layer 6 is improved, and the second wiring layer 7 can be easily formed, the filling property is improved, and the electrical connectivity is improved.

  The second insulating layer 6 is covered with the third insulating layer 22 except for the opening 6a, and the inner wall surface and the back surface of the through hole 3 of the semiconductor substrate 2 are both the second insulating layer 6. And the third insulating layer 22, the electrical reliability is further improved as compared with the first embodiment described above.

  Furthermore, the second wiring layer 7 is in contact only with the third insulating layer 22, is not in direct contact with the second insulating layer 6, and the third insulating layer 22 is in direct contact with the semiconductor substrate 2. Therefore, the degree of freedom in selecting the materials constituting the second and third insulating layers is higher than in the second embodiment. That is, the material constituting the second insulating layer 6 can be selected with the best material having excellent adhesion, considering only the adhesion with the semiconductor substrate 2. Moreover, considering the adhesiveness with the second wiring layer 7 as the material constituting the third insulating layer 22, a material having excellent adhesiveness can be selected. Accordingly, the degree of freedom of material selection can be greatly expanded, and a semiconductor device with further improved mechanical reliability compared to the second embodiment can be obtained.

  Next, still another embodiment of the present invention will be described.

  FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to the fourth embodiment of the present invention. In this figure, the same parts as those in FIG.

  As shown in FIG. 7, the semiconductor device 41 of the fourth embodiment has a semiconductor substrate 2 made of silicon or the like, and the semiconductor substrate 2 has a through hole 3 penetrating the front surface and the back surface. . The surface of the semiconductor substrate 2 is covered with a first insulating layer 4 having an opening 4 a having a diameter smaller than that of the through hole 3. The opening 4a of the first insulating layer 4 is coaxially formed in the upper part of the through hole 3, and the first wiring layer 5 is formed thereon so as to close the opening 4a. The inner wall surface of the through hole 3 including the inner wall surface of the opening 4 a of the first insulating layer 4 and the back surface of the semiconductor substrate 2 are covered with the second insulating layer 6. The second insulating layer 6 is formed so as to be inscribed in the first wiring layer 5, and has an opening 6 a having a smaller diameter than the opening 4 a of the first insulating layer 4 in the inscribed portion.

  Further, the second wiring layer 7 is filled in the through hole 3. The second wiring layer 7 is inscribed in the first wiring layer 5 through the opening 6 a of the second insulating layer 6 and on the second insulating layer 6 on the back surface of the semiconductor substrate 2 from the inside of the through hole 3. It is formed over. Furthermore, an external terminal 8 is provided on the second wiring layer 7 on the back surface of the semiconductor substrate 2. On the second wiring layer 7 and the second insulating layer 6 except for the portion where the external terminal 8 is disposed. Is covered with a protective layer 9.

  In the semiconductor device 41 of the fourth embodiment configured as described above, the diameter of the opening 4a of the first insulating layer 4 is set to be smaller than the opening diameter on the surface side of the through hole 3, so that the first The wiring layer 5 is structured to be covered with both the first insulating layer 4 and the second insulating layer 6 in the opening on the surface side of the through-hole 3, and is more electrically reliable than the first embodiment. The nature is further improved.

  FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to the fifth embodiment of the present invention. In this figure, the same parts as those in FIG.

  As shown in FIG. 8, the semiconductor device 51 of the fifth embodiment has a semiconductor substrate 2 made of silicon or the like, and the semiconductor substrate 2 is formed with a through hole 3 penetrating the front surface and the back surface. . The surface of the semiconductor substrate 2 is covered with a first insulating layer 4 having an opening 4 a having a diameter smaller than the diameter of the through hole 3. The opening 4a of the first insulating layer 4 is coaxially formed on the through hole 3, and the first wiring layer 5 is formed thereon so as to close the opening 4a. The inner wall surface of the through hole 3 including the inner wall surface of the opening 4 a of the first insulating layer 4 and the back surface of the semiconductor substrate 2 are covered with the second insulating layer 6. The second insulating layer 6 is formed so as to be inscribed in the first wiring layer 5, and has an opening 6 a having a smaller diameter than the opening 4 a of the first insulating layer 4 in the inscribed portion. A third insulating layer 22 is formed on the second insulating layer 6, and the second insulating layer 6 is covered with the third insulating layer 22 except for the opening 6 a portion.

  Further, the second wiring layer 7 is filled in the through hole 3. The second wiring layer 7 is inscribed in the first wiring layer 5 through the opening 6 a of the second insulating layer 6 and on the third insulating layer 22 extending from the inside of the through hole 3 to the back surface of the semiconductor substrate 2. Is formed. Furthermore, an external terminal 8 is provided on the second wiring layer 7 on the back surface of the semiconductor substrate 2. On the second wiring layer 7 and the third insulating layer 22 excluding the portion where the external terminal 8 is disposed. Is covered with a protective layer 9.

  In the semiconductor device 51 of the fifth embodiment configured as described above, the diameter of the opening 4a of the first insulating layer 4 is set to be smaller than the opening diameter on the surface side of the through hole 3, so that the first The wiring layer 5 is structured to be covered with both the first insulating layer 4 and the second insulating layer 6 in the opening on the surface side of the through-hole 3, and is electrically reliable as compared with the second embodiment. The nature is further improved.

  FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device according to the sixth embodiment of the present invention. In this figure, the same parts as those in FIG.

  As shown in FIG. 9, the semiconductor device 61 of the sixth embodiment has a semiconductor substrate 2 made of silicon or the like, and a through hole 3 penetrating the front surface and the back surface is formed in the semiconductor substrate 2. . The surface of the semiconductor substrate 2 is covered with a first insulating layer 4 having an opening 4 a having a diameter smaller than that of the through hole 3. The opening 4a of the first insulating layer 4 is coaxially formed on the through hole 3, and the first wiring layer 5 is formed thereon so as to close the opening 4a. The inner wall surface of the through hole 3 including the inner wall surface of the opening 4 a of the first insulating layer 4 and the back surface of the semiconductor substrate 2 are covered with the second insulating layer 6. The second insulating layer 6 is formed so as to be inscribed in the first wiring layer 5, and has an opening 6 a having a smaller diameter than the opening 4 a of the first insulating layer 4 in the inscribed portion.

  A third insulating layer 22 is formed on the second insulating layer 6. The third insulating layer 22 is inscribed with the first wiring layer 5, and has an opening 22 a having a smaller diameter than the opening 6 a of the second insulating layer 6 at the inscribed portion. Further, the second wiring layer 7 is filled in the through hole 3. The second wiring layer 7 is inscribed in the first wiring layer 5 through the opening 22 a of the third insulating layer 22, and extends from the through hole 3 to the back surface of the semiconductor substrate 2. Formed on top. Furthermore, an external terminal 8 is provided on the second wiring layer 7 on the back surface of the semiconductor substrate 2. On the second wiring layer 7 and the third insulating layer 22 excluding the portion where the external terminal 8 is disposed. Is covered with a protective layer 9.

  In the semiconductor device 61 of the sixth embodiment configured as described above, the diameter of the opening 4a of the first insulating layer 4 is set to be smaller than the opening diameter on the surface side of the through hole 3, so that the first The wiring layer 5 has a structure that is covered with both the first insulating layer 4 and the second insulating layer 6 in the opening on the surface side of the through-hole 3, and has an electrical reliability as compared with the third embodiment. Is further improved.

  The configuration, shape, size, and arrangement relationship described in the above embodiments are merely schematically shown, and the numerical values and the composition (material) of each configuration are merely examples. Therefore, the present invention is not limited to the above embodiment, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 6th Embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 21, 31, 41, 51, 61 ... Semiconductor device, 2 ... Semiconductor substrate, 3 ... Through-hole, 4 ... 1st insulating layer, 4a ... Opening of 1st insulating layer, 5 ... 1st wiring layer , 6 ... second insulating layer, 6a ... opening of the second insulating layer, 7 ... second wiring layer, 8 ... external terminal, 9 ... protective layer, 22 ... third insulating layer, 22a ... third Insulation layer opening.

Claims (7)

A semiconductor substrate;
A through hole provided through the first surface and the second surface of the semiconductor substrate;
A first insulating layer provided on the first surface of the semiconductor substrate and having an opening on the opening on the first surface side of the through hole;
A first conductor layer provided on the first insulating layer so as to cover the opening;
The inner surface of the through hole is connected to the second surface of the semiconductor substrate and is inscribed in the first conductor layer and on the opening on the first surface side of the through hole. A second insulating layer having an opening having a smaller diameter than the opening of the first insulating layer;
In the first conductor layer through the opening of the second insulating layer provided in the through hole and on the second insulating layer on the second surface of the semiconductor substrate. A semiconductor device comprising: a second conductor layer in contact therewith. A semiconductor substrate;
A through hole provided through the first surface and the second surface of the semiconductor substrate;
A first insulating layer provided on the first surface of the semiconductor substrate and having an opening on the opening on the first surface side of the through hole;
A first conductor layer provided on the first insulating layer so as to cover the opening;
The inner surface of the through hole is connected to the second surface of the semiconductor substrate and is inscribed in the first conductor layer and on the opening on the first surface side of the through hole. A second insulating layer having an opening having a smaller diameter than the opening of the first insulating layer;
A third opening having the same diameter as that of the opening of the second insulating layer is provided in the through hole and on the second insulating layer on the second surface of the semiconductor substrate. An insulating layer of
The first conductor is provided through the openings of the second and third insulating layers provided in connection with the third insulating layer in the through hole and on the second surface of the semiconductor substrate. A semiconductor device comprising: a second conductor layer inscribed in the layer. A semiconductor substrate;
A through hole provided through the first surface and the second surface of the semiconductor substrate;
A first insulating layer provided on the first surface of the semiconductor substrate and having an opening on the opening on the first surface side of the through hole;
A first conductor layer provided on the first insulating layer so as to cover the opening;
The inner surface of the through hole is connected to the second surface of the semiconductor substrate and is inscribed in the first conductor layer and on the opening on the first surface side of the through hole. A second insulating layer having an opening having a smaller diameter than the opening of the first insulating layer;
A third coaxially provided with an opening having a smaller diameter than the opening of the second insulating layer provided in the through hole and on the second insulating layer on the second surface of the semiconductor substrate. An insulating layer;
Inside the first conductor layer through the opening of the third insulating layer provided in the through hole and on the third insulating layer on the second surface of the semiconductor substrate. A semiconductor device comprising: a second conductor layer in contact therewith.   4. The semiconductor device according to claim 1, wherein the opening of the first insulating layer has a smaller diameter than the diameter of the opening on the first surface side of the through hole. Forming a first insulating layer on a first surface of a semiconductor substrate;
Forming a first conductor layer on the first insulating layer;
Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, exposing the first insulating layer on the first surface side of the through hole;
Forming an opening in the first insulating layer exposed on the first surface side of the through hole to expose the first conductor layer;
Forming a second insulating layer on the exposed first conductor layer and on the second surface of the semiconductor substrate from the inner wall surface of the through hole;
An opening having a smaller diameter than the opening of the first insulating layer is formed in the second insulating layer formed on the exposed first conductive layer, and the first conductive layer is exposed again. A process of
From the second insulating layer in the through hole to the second insulating layer on the second surface of the semiconductor substrate, the first exposed portion is exposed through the opening of the second insulating layer. And a step of forming a second conductor layer so as to be inscribed in the conductor layer. Forming a first insulating layer on a first surface of a semiconductor substrate;
Forming a first conductor layer on the first insulating layer;
Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, exposing the first insulating layer on the first surface side of the through hole;
Forming an opening in the first insulating layer exposed on the first surface side of the through hole to expose the first conductor layer;
Forming a second insulating layer on the exposed first conductor layer and on the second surface of the semiconductor substrate from the inner wall surface of the through hole;
A third insulating layer is formed on the second insulating layer in the through hole, and the third insulating layer is connected to the second insulating layer on the second surface of the semiconductor substrate. Forming the process,
A hole having a smaller diameter than the through hole is formed in the third insulating layer in the through hole, and at the same time, the second insulating layer formed on the first surface side of the through hole has the same diameter as the hole. Forming an opening contiguously and exposing the first conductor layer;
The hole of the third insulating layer and the opening of the second insulating layer extend from the third insulating layer in the through hole to the third insulating layer on the second surface of the semiconductor substrate. Forming a second conductor layer so as to be inscribed in the exposed first conductor layer through the semiconductor device. Forming a first insulating layer on a first surface of a semiconductor substrate;
Forming a first conductor layer on the first insulating layer;
Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, exposing the first insulating layer on the first surface side of the through hole;
Forming an opening in the first insulating layer exposed on the first surface side of the through hole to expose the first conductor layer;
Forming a second insulating layer on the exposed first conductor layer and on the second surface of the semiconductor substrate from the inner wall surface of the through hole;
An opening having a smaller diameter than the opening of the first insulating layer is formed in the second insulating layer formed on the exposed first conductive layer, and the first conductive layer is exposed again. A process of
From the second insulating layer in the through hole to the second insulating layer on the second surface of the semiconductor substrate, the first exposed portion is exposed through the opening of the second insulating layer. Forming a third insulator layer while inscribed in the conductor layer;
A hole having a smaller diameter than the opening of the second insulating layer is formed in the third insulating layer in the through hole coaxially with the opening of the second insulating layer, and the first conductor layer is formed. Exposing, and
From the third insulating layer in the through hole to the third insulating layer on the second surface of the semiconductor substrate, the exposed first through the opening of the third insulating layer. Forming a second conductor layer so as to be inscribed in the conductor layer. A method for manufacturing a semiconductor device, comprising:

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