JP2009049336A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which reduction of generating connection failures, or mechanical reliability in a feed-through connection part is improved by preventing wall-like adherent matters or residues of an organic mask in the bottom of a through hole when a feed-through wiring layer is formed on a semiconductor substrate. <P>SOLUTION: The semiconductor device is formed by coating the surface of the semiconductor substrate 2 having a through hole 3, with a first insulating layer 4 having an opening 4a whose diameter is smaller than that of the through hole 3 and by coating the surface with a first wiring layer 5 covering its opening 4a. The inside of the through hole 3 and the underside of the semiconductor substrate 2 are also coated with a second insulating layer 6, and therein with a metal mask layer 7 made of a high-resistance metal having the diffusion preventing function. The second insulating layer 6 and the metal mask layer 7 have openings 6a and 7a respectively whose diameter is identical with that of the opening 4a of the first insulating layer 4. A second wiring layer 8 is formed, and the through hole 3 is filled with it. The second wiring layer 8 is in contact with the inner side of the first wiring layer 5 through the openings 4a and 6a of the first insulating layer 4 and the second insulating layer 6. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a through connection portion for electrically connecting wirings on the front and back surfaces of a semiconductor substrate and a manufacturing method thereof.

  In memory devices using semiconductor integrated circuits, it has been proposed to stack memory chips (semiconductor chips) in multiple stages in order to increase the memory capacity. A through-hole penetrating the front and back surfaces is formed in the semiconductor chip, a conductor layer is formed in the through-hole, and metal bumps electrically connected to the conductor layer are provided on the back surface of the chip. Metal bumps of the upper semiconductor chip are bonded to metal pads formed on the surface of the lower semiconductor chip, and thus the integrated circuit portion of the upper memory chip and the integrated circuit portion of the lower memory chip are electrically connected. Yes.

  As a semiconductor device having such a through-connection portion, conventionally, a through hole is formed by etching from the back surface of the semiconductor substrate, and a conductive portion formed in the through hole electrically connects the wiring layer between the front surface and the back surface of the semiconductor substrate. An apparatus having a structure of being connected to each other has been proposed (for example, see Patent Document 1).

  A conventional semiconductor device will be described below. In the conventional semiconductor device 100 shown in FIG. 5, a semiconductor substrate 101 made of silicon has a through hole 102 penetrating the front and back surfaces, and an insulating film (from the inner wall surface of the through hole 102 to the back surface of the semiconductor substrate 101. A back side insulating film) 103 is formed. A through wiring layer 104 is formed in the through hole 102 via a barrier metal layer 105. The through wiring layer 104 electrically connects a wiring layer (front surface side wiring layer) 106 formed on the front surface side of the semiconductor substrate 101 and an external terminal (solder ball) 107 formed on the back surface side.

  An insulating layer (surface-side insulating layer) 108 having an opening 108 a having a smaller diameter than the through hole 102 is formed on the surface of the semiconductor substrate 101, and the surface-side wiring layer 106 is formed on the surface-side insulating layer 108. A semiconductor device such as an image sensor is formed on the surface side of the semiconductor substrate 101 by an integrated circuit. Furthermore, an external terminal 107 connected to the through wiring layer 104 and a protective film (back surface side protective film) 109 are provided on the back surface of the semiconductor substrate 101. The external terminal 107 is formed so as to protrude outward.

In the semiconductor device 100, the through hole 102 and the opening 108a of the surface side insulating layer 108 are formed as follows. That is, the through-hole 102 is formed by etching the semiconductor substrate 101 from the back side thereof using a predetermined mask pattern (not shown) until the front-side insulating layer 108 is exposed. Next, after forming a back surface side insulating film 103 from the inside of the through hole 102 to the back surface of the semiconductor substrate 101, an opening is formed at the bottom of the through hole 102 using an organic mask (not shown) such as a photoresist. After forming the mask pattern, the back-side insulating film 103 and the front-side insulating layer 108 exposed from the opening of the mask pattern are removed using anisotropic etching to form openings 103a and 108a, and the wiring layer 106 is exposed. . Thereafter, a through wiring layer 104 is formed in the through hole 102 and on the insulating film 103 on the back surface of the semiconductor substrate 101 through the barrier metal layer 105.
JP 2005-31215 A

  However, in the conventional semiconductor device 100 manufactured by such a method, it was exposed when the openings 103a and 108a were formed in the back-side insulating film 103 and the front-side insulating layer 108 at the bottom of the through hole 102. The wiring layer (surface-side wiring layer) 106 is etched and deposited on the organic mask. Then, when the organic mask is removed after etching, the deposit remains as the wall-like protrusions 110, which causes a problem that the mechanical reliability is lowered. In addition, the surface of the organic mask is altered during etching, making it difficult to remove, and the organic mask residue 111 remains at the bottom of the through-hole 102, resulting in poor connection of the wiring layer 106 and a decrease in yield. .

  The present invention was made to solve these problems, and prevents through-wall deposits and organic mask residues from being generated at the bottom of the through-hole when forming a through-wiring layer on a semiconductor substrate. An object of the present invention is to provide a semiconductor device with improved connection failures and mechanical reliability.

  A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate, a through-hole provided through the first surface and the second surface of the semiconductor substrate, and a first surface of the semiconductor substrate. A first insulating layer having an opening having a diameter smaller than the diameter of the opening on the opening on the first surface side of the through-hole, and covering the opening on the first insulating layer The first conductor layer provided on the first insulating layer and the same diameter as the first conductor layer provided on the second surface of the semiconductor substrate from the inner wall surface of the through hole. And a metal mask made of a high-resistance metal having a diffusion preventing function provided in the through hole and on the second insulating layer on the second surface of the semiconductor substrate. A layer connected to the metal mask layer in the through hole and on the second surface of the semiconductor substrate; Characterized in that it comprises a second conductor layer that is inscribed in the first conductive layer through the opening of the first opening of the insulating layer and the second insulating layer.

  A semiconductor device according to a second aspect of the present invention includes a semiconductor substrate, a first surface of the semiconductor substrate, a through hole provided through the second surface, and a first surface of the semiconductor substrate. A first insulating layer having an opening having a diameter smaller than the diameter of the opening on the opening on the first surface side of the through-hole, and covering the opening on the first insulating layer The first conductor layer provided on the first insulating layer and the same diameter as the first conductor layer provided on the second surface of the semiconductor substrate from the inner wall surface of the through hole. And a metal mask made of a high-resistance metal having a diffusion preventing function provided in the through hole and on the second insulating layer on the second surface of the semiconductor substrate. A layer connected to the metal mask layer in the through hole and on the second surface of the semiconductor substrate, and the first insulating layer; A base metal layer having a diffusion preventing function provided so as to be inscribed in the first conductor layer through the opening of the layer and the opening of the second insulating layer; And a second conductor layer connected to the base metal layer on the second surface.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating layer on a first surface of a semiconductor substrate; and forming a first conductor layer on the first insulating layer. Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, and exposing the first insulating layer on the first surface side of the through hole; and Forming a second insulating layer on the exposed first insulating layer and on the second surface of the semiconductor substrate from the inner wall surface of the through hole; and in the through hole and on the second surface of the semiconductor substrate. Forming a metal mask layer made of a high-resistance metal having a diffusion preventing function on the second insulating layer on the first surface, and the metal formed on an end of the through hole on the first surface side Forming a small-diameter opening in the mask layer from the through hole to expose the second insulating layer; and The second insulating layer and the first insulating layer exposed from the opening of the layer are removed by etching, and the second insulating layer and the first insulating layer have the same diameter as the opening of the metal mask layer. Forming an opening of each of the first wiring layer, exposing the first wiring layer, and over the metal mask layer on the second surface of the semiconductor substrate from the metal mask layer in the through hole. Forming a second conductor layer so as to be inscribed in the exposed first conductor layer through the opening of the second insulating layer and the first insulating layer; and the second conductor layer And a step of removing the metal mask layer other than the region covered with the film.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating layer on a first surface of a semiconductor substrate; and forming a first conductor layer on the first insulating layer. Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, exposing the first insulating layer on the first surface side of the through hole, and Forming a second insulating layer on the exposed first insulating layer and on the second surface of the semiconductor substrate from the inner wall surface of the through hole; and in the through hole and on the second surface of the semiconductor substrate. Forming a metal mask layer made of a high-resistance metal having a diffusion preventing function on the second insulating layer on the surface, and the metal mask formed on an end of the through hole on the first surface side Forming an opening having a smaller diameter than the through hole in the layer to expose the second insulating layer; and the metal mask layer The second insulating layer and the first insulating layer exposed from the opening are removed by etching, and an opening having the same diameter as the opening of the metal mask layer is formed in the second insulating layer and the first insulating layer. And exposing the first wiring layer, and extending from the metal mask layer in the through hole to the metal mask layer on the second surface of the semiconductor substrate. Forming a base metal layer having a diffusion preventing function so as to be inscribed in the exposed first conductor layer through the opening of the insulating layer and the first insulating layer, and the base in the through hole A step of connecting and forming a second conductor layer from the metal layer to the base metal layer on the second surface of the semiconductor substrate, and a region other than the region covered by the second conductor layer And a step of removing the base metal layer and the metal mask layer. And wherein the Rukoto.

  According to the semiconductor device according to the first aspect of the present invention and the method for manufacturing the semiconductor device according to the third aspect, the opening of the second insulating layer is formed at the bottom of the through hole (the end on the first surface side). And the opening of the first insulating layer is formed using a mask layer made of a high-resistance metal having a diffusion prevention function, and this metal mask layer remains as a diffusion prevention film (barrier layer) for the second conductor layer. As a result, no organic mask residue or re-attached metal wall is generated at the bottom of the through hole. Therefore, a semiconductor device with improved yield and excellent electrical and mechanical reliability can be obtained.

  According to the semiconductor device according to the second aspect of the present invention and the method for manufacturing the semiconductor device according to the fourth aspect, the residue of the organic mask at the bottom of the through-hole, as in the first and third aspects. There is no generation of wall-like objects due to objects and reattached metal, and electrical and mechanical reliability is improved. In addition, the metal mask layer is covered with a base metal layer having a diffusion preventing function, and the inner wall surface and the back surface of the through hole in the semiconductor substrate are double-coated with the metal mask layer and the base metal layer. The barrier property with respect to the second conductor layer is further improved. Therefore, a semiconductor device with better electrical reliability can be obtained.

  Hereinafter, modes for carrying out the present invention will be described. In addition, although embodiment is described based on drawing in the following description, those drawings are provided for illustration and this invention is not limited to those drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention, and FIGS. 2A to 2J are cross-sectional views showing respective steps of a method for manufacturing the semiconductor device of the first embodiment. FIG.

  As shown in FIG. 1, a semiconductor device 1 according to the first embodiment includes a semiconductor substrate 2 made of silicon or the like, and the semiconductor substrate 2 has a surface (element region forming surface) which is a first surface thereof. And a through-hole 3 penetrating through the second surface is formed. The surface of the semiconductor substrate 2 is covered with a first insulating layer 4 having an opening 4a having a smaller diameter than the through-hole 3 on the top of the through-hole 3. 1 wiring layer 5 is formed. The first wiring layer 5 is formed so as to cover and close the opening 4 a of the first insulating layer 4. The inner wall surface of the through hole 3 and the back surface of the semiconductor substrate 2 are covered with a second insulating layer 6. The second insulating layer 6 is formed so as to be inscribed with the first insulating layer 4 at the upper portion (surface side end portion) of the through hole 3, and the opening 4 a of the first insulating layer 4 is formed in the inscribed portion. An opening 6a having the same diameter is provided.

  Further, a metal mask layer 7 is formed from the inside of the through hole 3 to the second insulating layer 6 on the back surface of the semiconductor substrate 2. The metal mask layer 7 is made of a high resistance metal having a diffusion preventing function, and is formed so as to be inscribed in the second insulating layer 6 above the through hole 3. The inscribed portion has an opening 7 a having the same diameter as the opening 6 a of the second insulating layer 6 and the opening 4 a of the first insulating layer 4.

  Further, the second wiring layer 8 is filled in the through hole 3. The second wiring layer 8 is formed over the metal mask layer 7 on the back surface of the semiconductor substrate 2 from the inside of the through hole 3, and the opening 4 a of the first insulating layer 4 (and the opening of the second insulating layer 6). 6a and the opening 7a) of the metal mask layer 7 are formed so as to be inscribed in the first wiring layer 5. Furthermore, external terminals 9 are provided on the second wiring layer 8 on the back surface of the semiconductor substrate 2. Then, on the back surface of the semiconductor substrate 2, a protective layer (back surface side protective layer) 10 is covered on the second wiring layer 8 and the second insulating layer 6 except for the portion where the external terminals 9 are disposed. .

The semiconductor device 1 according to the first embodiment configured as described above is manufactured as follows. That is, first, in the first step shown in FIG. 2A, on the surface (first surface) of the semiconductor substrate 2, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), SiOF (Fluorine-doped SiO _2). ), Porous SiOC (Carbon-doped SiO ₂ ) or the like, is formed by a CVD (Chemical Vapor Deposition) method, a spin coat method, a spray coat method, or the like.

  Next, in the second step shown in FIG. 2B, the first wiring layer 5 is formed on the first insulating layer 4 by sputtering, CVD, vapor deposition, plating, or the like. The first wiring layer 5 includes, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, etc.) or a structure in which a plurality of layers made of the above materials are laminated.

Next, in a third step shown in FIG. 2C, a through hole 3 is formed by plasma etching from the second surface (back surface) side of the semiconductor substrate 2 using a mask (not shown) having a predetermined pattern. The first insulating layer 4 is exposed at the bottom (surface side end) of the through hole 3. The through-hole 3 preferably has a cross section that tapers toward the first insulating layer 4. In the formation of the through-hole 3, plasma etching is performed by introducing an etching gas into the plasma so that the semiconductor substrate 2 is etched relatively larger than the first insulating layer 4. As the etching gas, for example, when the semiconductor substrate 2 is silicon (Si) and the first insulating layer 4 is a SiO ₂ film, a mixed gas of SF ₆ , O _2, and Ar is used.

  Next, in the fourth step shown in FIG. 2D, the second insulating layer is formed so as to cover the back surface of the semiconductor substrate 2 from the exposed portion of the first insulating layer 4 at the bottom of the through hole 3 and the inner wall surface of the through hole 3. 6 is formed by a CVD method, a spray coating method, a spin coating method, a film laminating method, or the like. The second insulating layer 6 is made of, for example, silicon oxide, silicon nitride, polyimide resin, BCB (benzocyclobutene) resin, epoxy resin, or the like.

  Next, in a fifth step shown in FIG. 2E, a metal mask layer 7 is formed from the second insulating layer 6 in the through hole 3 to the second insulating layer 6 on the back surface of the semiconductor substrate 2. The metal mask layer 7 is, for example, a single layer made of a high resistance metal material (Ti, TiN, TiW, Ni, NiV, NiFe, Cr, TaN, CoWP, etc.) having a diffusion preventing function, or made of the above material. It has a structure in which a plurality of layers are stacked. The metal mask layer 7 is formed by sputtering, CVD, vapor deposition, plating, printing, or the like.

  Next, in a sixth step shown in FIG. 2F, a resist mask (not shown) having a predetermined pattern is formed on the metal mask layer 7 formed so as to cover the second insulating layer 6 at the bottom of the through hole 3. Then, an opening 7a is formed by etching, and the second insulating layer 6 is exposed again. In the formation of the opening 7a, for example, when the metal mask layer 7 is made of Ti, wet etching is performed using a mixed solution containing hydrofluoric acid as a main component as an etchant. After the opening 7a is formed in the metal mask layer 7, the resist mask is removed.

Next, in a seventh step shown in FIG. 2G, plasma etching is performed using the metal mask layer 7 as a mask to form openings 6 a and 4 a in the second insulating layer 6 and the first insulating layer 4. That is, after the exposed portion of the second insulating layer 6 exposed from the opening 7a of the metal mask layer 7 is removed by plasma etching to form the opening 6a, plasma etching is further performed, thereby performing the second insulating layer. The first insulating layer 4 exposed from the opening 6a is removed by plasma etching to form the opening 4a of the first insulating layer 4 at the same position as the opening 6a of the second insulating layer 6, and the first wiring Layer 5 is exposed. At this time, an etching gas (for example, the second insulating layer 6) is included in the plasma so that the second insulating layer 6 and the first insulating layer 4 are etched relatively larger than the metal mask layer 7. When the first insulating layer 4 and the first insulating layer 4 are both SiO ₂ films and the metal mask layer 7 is composed of Ti, plasma etching is performed by introducing a mixed gas of C ₅ F ₈ , O ₂ and Ar).

  Next, in an eighth step shown in FIG. 2H, the opening 6a of the second insulating layer 6 and the second insulating layer 6 extend from the metal mask layer 7 in the through hole 3 to the metal mask layer 7 on the back surface of the semiconductor substrate 2. The second wiring layer 8 is formed so as to be inscribed in the first wiring layer 5 through the opening 4 a of the first insulating layer 4. The second wiring layer 8 is, for example, a single layer made of a low-resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, solder material, etc.) or a conductive resin, Or it has the structure where the several layer which consists of said material was laminated | stacked. The second wiring layer 8 is formed by a sputtering method, a CVD method, a vapor deposition method, a plating method, a printing method or the like using a mask (not shown) having a predetermined pattern. Although it is desirable to form the second wiring layer 8 so that the inside of the through hole 3 is filled without a gap, there may be a gap without being completely filled.

  Next, in the ninth step shown in FIG. 2I, the second wiring layer 8 is used as a mask, and the metal mask layer 7 other than the region covered with the second wiring layer 8 is removed by etching. For example, when the metal mask layer 7 is made of Ti and the second wiring layer 8 is made of Cu, wet etching is performed using an etchant containing hydrofluoric acid as a main component.

  Thereafter, in a tenth step shown in FIG. 2J, external terminals 9 are formed on the second wiring layer 8, and the second wiring layer 8 and the second insulating layer excluding the portion where the external terminals 9 are disposed. A protective layer 10 is formed on 6. The external terminal 9 is formed of, for example, a solder material, and the protective layer 10 is formed of a polyimide resin, an epoxy resin, or a solder resist material. Next, the semiconductor substrate 2 is cut with a cutting blade of a dicer. In this way, individual pieces of the semiconductor device 1 shown in FIG. 1 are obtained.

  In the semiconductor device 1 according to the first embodiment manufactured as described above, the opening 6a of the second insulating layer 6 and the opening 4a of the first insulating layer 4 at the bottom of the through hole 3 are formed with a high diffusion preventing function. Since the metal mask layer 7 made of a resistance metal is used and the metal mask layer 7 is left on the second insulating layer 6 as it is, the metal mask layer 7 becomes the second wiring layer. In addition to having the function of preventing the diffusion of the metal constituting 8, the organic mask residue does not occur at the bottom of the through-hole 3 unlike the conventional structure. In addition, the reattachment metal generated when the first wiring layer 5 is exposed may be left as it is on the metal mask layer 7, and the wall shape of the reattachment metal generated when removing the organic mask in the conventional structure. Will not occur. Therefore, the formation of the second wiring layer 8 is easy, the filling property to the through hole 3 is good, and the electrical connectivity is improved. Furthermore, since the adhesion between the metal mask layer 7 and the second insulating layer 6 that is the base insulating film is good, the mechanical reliability is also high.

  Next, another embodiment of the present invention will be described.

  FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention, and FIGS. 4A to 4K are cross-sectional views showing respective steps of a method for manufacturing the semiconductor device of the second embodiment. FIG. In these drawings, the same parts as those in FIGS. 1 and 2A to 2J are denoted by the same reference numerals.

  As shown in FIG. 3, the semiconductor device 21 of the second embodiment has a semiconductor substrate 2 made of silicon or the like, and the semiconductor substrate 2 is formed with a through hole 3 penetrating the front surface and the back surface. . The surface of the semiconductor substrate 2 is covered with a first insulating layer 4 having an opening 4a having a diameter smaller than that of the through-hole 3 on the top of the through-hole 3, and a first wiring layer 5 is formed thereon. Is formed. The first wiring layer 5 is formed so as to cover and close the opening 4 a of the first insulating layer 4. The inner wall surface of the through hole 3 and the back surface of the semiconductor substrate 2 are covered with a second insulating layer 6. The second insulating layer 6 is formed so as to be inscribed with the first insulating layer 4 at the upper portion (surface side end portion) of the through hole 3, and the opening 4 a of the first insulating layer 4 is formed in the inscribed portion. An opening 6a having the same diameter is provided.

  Further, a metal mask layer 7 is formed from the inside of the through hole 3 to the second insulating layer 6 on the back surface of the semiconductor substrate 2. The metal mask layer 7 is made of a high resistance metal having a diffusion preventing function, and is formed so as to be inscribed in the second insulating layer 6 above the through hole 3. The inscribed portion has an opening 7 a having the same diameter as the opening 6 a of the second insulating layer 6 and the opening 4 a of the first insulating layer 4.

  Also, a base metal layer 22 having a diffusion preventing function is formed on the metal mask layer 7 on the back surface of the semiconductor substrate 2 from within the through hole 3. The base metal layer 22 is formed in the opening 4 a of the first insulating layer 4 so as to be inscribed in the first wiring layer 5 through the opening 4 a and the opening 6 a of the second insulating layer 6. Then, it is continuously formed from the inside of the through hole 3 to the metal mask layer 7 on the back surface of the semiconductor substrate 2.

  A second wiring layer 8 is formed in the through hole 3. The second wiring layer 8 is formed from the base metal layer 22 in the through hole 3 to the base metal layer 22 on the back surface of the semiconductor substrate 2, and is formed so as to fill the through hole 3 without any gap. ing. Furthermore, external terminals 9 are provided on the second wiring layer 8 on the back surface of the semiconductor substrate 2. On the back surface of the semiconductor substrate 2, the second wiring layer 8 on the second wiring layer 8 excluding the portion where the external terminals 9 are disposed and A protective layer 10 is coated on the second insulating layer 6.

The semiconductor device 21 of the second embodiment configured as described above is manufactured as follows. That is, first in the first step shown in FIG. 4A, a first insulating layer made of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), SiOF, porous SiOC, or the like is formed on the surface of the semiconductor substrate 2. 4 is formed by CVD, spin coating, spray coating, or the like.

  Next, in the second step shown in FIG. 4B, the first wiring layer 5 is formed on the first insulating layer 4 by sputtering, CVD, vapor deposition, plating, or the like. The first wiring layer 5 includes, for example, a high resistance metal material (Ti, TiN, TiW, Ni, Cr, TaN, CoWP, etc.) or a low resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, etc.) or a structure in which a plurality of layers made of the above materials are laminated.

Next, in the third step shown in FIG. 4C, a through-hole 3 is formed by plasma etching from the second surface (back surface) side of the semiconductor substrate 2 using a mask (not shown) having a predetermined pattern. The first insulating layer 4 is exposed at the bottom (surface side end) of the through hole 3. The through-hole 3 preferably has a cross section that tapers toward the first insulating layer 4. In the formation of the through-hole 3, plasma etching is performed by introducing an etching gas into the plasma so that the semiconductor substrate 2 is etched relatively larger than the first insulating layer 4. As the etching gas, for example, when the semiconductor substrate 2 is silicon (Si) and the first insulating layer 4 is a SiO ₂ film, a mixed gas of SF ₆ , O _2, and Ar is used.

  Next, in the fourth step shown in FIG. 4D, the second insulating layer is formed so as to cover the back surface of the semiconductor substrate 2 from the exposed portion of the first insulating layer 4 at the bottom of the through hole 3 and the inner wall surface of the through hole 3. 6 is formed by a CVD method, a spray coating method, a spin coating method, a film laminating method or the like. The second insulating layer 6 is made of, for example, silicon oxide, silicon nitride, polyimide resin, BCB resin, epoxy resin, or the like.

  Next, in a fifth step shown in FIG. 4E, a metal mask layer 7 is formed from the second insulating layer 6 in the through hole 3 to the second insulating layer 6 on the back surface of the semiconductor substrate 2. The metal mask layer 7 is, for example, a single layer made of a high resistance metal material (Ti, TiN, TiW, Ni, NiV, NiFe, Cr, TaN, CoWP, etc.) having a diffusion preventing function, or from the above material. It has a structure in which a plurality of layers are laminated. The metal mask layer 7 is formed by sputtering, CVD, vapor deposition, plating, printing, or the like.

  Next, in a sixth step shown in FIG. 4F, a resist mask having a predetermined pattern (not shown) is formed on the metal mask layer 7 formed so as to cover the second insulating layer 6 at the bottom of the through hole 3. Then, the opening 7a is formed by etching to expose the second insulating layer 6 again. In the formation of the opening 7a, for example, when the metal mask layer 7 is made of Ti, wet etching is performed using a mixed solution containing hydrofluoric acid as a main component as an etchant. After the opening 7a is formed in the metal mask layer 7, the resist mask is removed.

Next, in a seventh step shown in FIG. 4G, plasma etching is performed using the metal mask layer 7 as a mask to form openings 6 a and 4 a in the second insulating layer 6 and the first insulating layer 4. That is, the exposed portion of the second insulating layer 6 exposed from the opening 7a of the metal mask layer 7 and the first insulating layer 4 below the exposed portion are continuously removed by plasma etching, and the second insulating layer is removed. The opening 6a of the layer 6 is formed, and the opening 4a of the first insulating layer 4 is formed at the same position as the opening 6a to expose the first wiring layer 5. At this time, an etching gas (for example, the second insulating layer 6) is included in the plasma so that the second insulating layer 6 and the first insulating layer 4 are etched relatively larger than the metal mask layer 7. When the first insulating layer 4 and the first insulating layer 4 are both SiO ₂ films and the metal mask layer 7 is composed of Ti, plasma etching is performed by introducing a mixed gas of C ₅ F ₈ , O ₂ and Ar).

  Next, in the eighth step shown in FIG. 4H, the second insulating layer 6 and the first insulating layer are formed over the metal mask layer 7 in the through hole 3 and the metal mask layer 7 on the back surface of the semiconductor substrate 2. A base metal layer 22 is formed so as to be inscribed in the first wiring layer 5 through the openings 6 a and 4 a of the layer 4. The base metal layer 22 is, for example, a single layer made of a high resistance metal material (Ti, TiN, TiW, Ni, NiV, NiFe, Cr, TaN, CoWP, etc.) having a diffusion preventing function, or made of the above material. It has a structure in which a plurality of layers are stacked. The base metal layer 22 is formed by a sputtering method, a CVD method, a vapor deposition method, a plating method, a printing method, or the like using a mask (not shown) having a predetermined pattern.

  Next, in a ninth step shown in FIG. 4I, the second wiring layer 8 is formed on the base metal layer 22 formed continuously from the inside of the through hole 3 to the back surface of the semiconductor substrate 2. The second wiring layer 8 is, for example, a single layer made of a low-resistance metal material (Al, Al—Cu, Al—Si—Cu, Cu, Au, Ag, solder material, etc.) or a conductive resin, Or it has the structure where the several layer which consists of said material was laminated | stacked. The second wiring layer 8 is formed by a sputtering method, a CVD method, a vapor deposition method, a plating method, a printing method or the like using a mask (not shown) having a predetermined pattern. Although it is desirable to form the second wiring layer 8 so as to fill the through hole 3 without any gap, it is not necessary to completely fill the through hole 3.

  Next, in the tenth step shown in FIG. 4J, using the second wiring layer 8 as a mask, the base metal layer 22 other than the region covered by the second wiring layer 8 and the underlying metal mask layer 7 are formed. Each is removed by etching. For example, when the base metal layer 22 and the metal mask layer 7 are each composed of Ti and the second wiring layer 8 is composed of Cu, wet etching is performed using an etchant containing hydrofluoric acid as a main component.

  Thereafter, in an eleventh step shown in FIG. 4K, external terminals 9 are formed on the second wiring layer 8, and on the second wiring layer 8 and the second insulating layer excluding the portion where the external terminals 9 are disposed. A protective layer 10 is formed on 6. The external terminal 9 is formed of, for example, a solder material, and the protective layer 10 is formed of polyimide resin, epoxy resin, or solder resist material. Next, the semiconductor substrate 2 is cut with a cutting blade of a dicer. Thus, individual pieces of the semiconductor device 21 shown in FIG. 3 are obtained.

  In the semiconductor device 21 according to the second embodiment manufactured as described above, the opening 6a of the second insulating layer 6 and the opening 4a of the first insulating layer 4 at the bottom of the through hole 3 are provided with a high diffusion preventing function. Since the metal mask layer 7 made of a resistance metal is used and the metal mask layer 7 is left on the second insulating layer 6 as it is, the metal mask layer 7 becomes the second wiring layer. In addition to having the function of preventing the diffusion of the metal constituting 8, the organic mask residue does not occur at the bottom of the through-hole 3 unlike the conventional structure. In addition, the reattachment metal generated when the first wiring layer 5 is exposed may be left as it is on the metal mask layer 7, and the wall shape of the reattachment metal generated when removing the organic mask in the conventional structure. Will not occur. Therefore, the formation of the second wiring layer 8 is easy, the filling property to the through hole 3 is good, and the electrical connectivity is improved. Furthermore, since the adhesion between the metal mask layer 7 and the second insulating layer 6 that is the base insulating film is good, the mechanical reliability is also high.

  The metal mask layer 7 is covered with a base metal layer 22, and the base metal layer 22 having a diffusion prevention function is formed in the through hole 3 and the back surface of the semiconductor substrate 2 in the same manner as the metal mask layer 7 having a diffusion prevention function. Are covered by a laminated structure, the barrier property with respect to the second wiring layer 8 is further improved as compared with the first embodiment, and a semiconductor device with better electrical reliability is obtained. be able to. Further, the material constituting the metal mask layer 7 is selected in consideration of the adhesion to the semiconductor substrate 2 among the high resistance metal materials having a diffusion preventing function, and the material constituting the base metal layer 22 is a through-hole. 3 can be selected in consideration of the adhesion to the second wiring layer 8 in 3, so that the degree of freedom of material selection is widened and the mechanical reliability is further improved.

  The configuration, shape, size, and arrangement relationship described in the above embodiments are merely schematically shown, and the numerical values and the composition (material) of each configuration are merely examples. Therefore, the present invention is not limited to the above embodiment, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,21 ... Semiconductor device, 2 ... Semiconductor substrate, 3 ... Through-hole, 4 ... 1st insulating layer, 4a ... Opening of 1st insulating layer, 5 ... 1st wiring layer, 6 ... 2nd insulating layer , 6a ... opening of the second insulating layer, 7 ... metal mask layer, 8 ... second wiring layer, 9 ... external terminal, 10 ... protective layer, 22 ... underlying metal layer.

Claims (5)

A semiconductor substrate;
A through hole provided through the first surface and the second surface of the semiconductor substrate;
A first insulating layer provided on the first surface of the semiconductor substrate and having an opening having a diameter smaller than the diameter of the opening on the opening on the first surface side of the through hole;
A first conductor layer provided on the first insulating layer so as to cover the opening;
A second insulating layer connected to the second surface of the semiconductor substrate from the inner wall surface of the through hole and having an opening of the same diameter connected to the opening of the first insulating layer;
A metal mask layer made of a high resistance metal having a diffusion preventing function, provided in the through hole and on the second insulating layer on the second surface of the semiconductor substrate;
The first insulating layer and the second insulating layer provided in the through hole and on the metal mask layer on the second surface of the semiconductor substrate through the opening of the first insulating layer and the second insulating layer. A semiconductor device comprising: a second conductor layer inscribed in one conductor layer. A semiconductor substrate;
A through hole provided through the first surface and the second surface of the semiconductor substrate;
A first insulating layer provided on the first surface of the semiconductor substrate and having an opening having a diameter smaller than the diameter of the opening on the opening on the first surface side of the through hole;
A first conductor layer provided on the first insulating layer so as to cover the opening;
A second insulating layer connected to the second surface of the semiconductor substrate from the inner wall surface of the through hole and having an opening of the same diameter connected to the opening of the first insulating layer;
A metal mask layer made of a high resistance metal having a diffusion preventing function, provided in the through hole and on the second insulating layer on the second surface of the semiconductor substrate;
The first conductive layer is connected to the metal mask layer in the through hole and on the second surface of the semiconductor substrate, and through the opening of the first insulating layer and the opening of the second insulating layer. A base metal layer having a diffusion preventing function provided so as to be inscribed in the body layer;
A semiconductor device comprising: a second conductor layer provided in connection with the base metal layer in the through hole and on the second surface of the semiconductor substrate.   The metal mask layer is a single layer made of Ti, TiN, TiW, Ni, NiV, NiFe, Cr, TaN, CoWP, or a layer in which a plurality of layers made of the metal material are stacked. The semiconductor device according to claim 1 or 2. Forming a first insulating layer on a first surface of a semiconductor substrate;
Forming a first conductor layer on the first insulating layer;
Forming a through hole from the second surface side of the semiconductor substrate to the first surface side and exposing the first insulating layer on the first surface side of the through hole;
Forming a second insulating layer on the exposed first insulating layer and on the second surface of the semiconductor substrate from the inner wall surface of the through hole;
Forming a metal mask layer made of a high resistance metal having a diffusion preventing function in the through hole and on the second insulating layer on the second surface of the semiconductor substrate;
Forming a small-diameter opening in the metal mask layer formed at the end of the through hole on the first surface side, and exposing the second insulating layer;
The second insulating layer and the first insulating layer exposed from the opening of the metal mask layer are removed by etching, and the opening of the metal mask layer is formed in the second insulating layer and the first insulating layer. Forming an opening having the same diameter as each of the first wiring layer and exposing the first wiring layer;
From the metal mask layer in the through hole to the metal mask layer on the second surface of the semiconductor substrate, the exposed first through the openings of the second insulating layer and the first insulating layer. Forming a second conductor layer so as to be inscribed in the first conductor layer;
Removing the metal mask layer other than the region covered with the second conductor layer. A method for manufacturing a semiconductor device, comprising: Forming a first insulating layer on a first surface of a semiconductor substrate;
Forming a first conductor layer on the first insulating layer;
Forming a through hole from the second surface side of the semiconductor substrate to the first surface side, exposing the first insulating layer on the first surface side of the through hole;
Forming a second insulating layer on the exposed first insulating layer and on the second surface of the semiconductor substrate from the inner wall surface of the through hole;
Forming a metal mask layer made of a high resistance metal having a diffusion preventing function in the through hole and on the second insulating layer on the second surface of the semiconductor substrate;
Forming a small-diameter opening in the metal mask layer formed at the end of the through hole on the first surface side, and exposing the second insulating layer;
The second insulating layer and the first insulating layer exposed from the opening of the metal mask layer are removed by etching, and the opening of the metal mask layer is formed in the second insulating layer and the first insulating layer. Forming an opening having the same diameter as each of the first wiring layer and exposing the first wiring layer;
From the metal mask layer in the through hole to the metal mask layer on the second surface of the semiconductor substrate, the exposed first through the openings of the second insulating layer and the first insulating layer. Forming a base metal layer having a diffusion preventing function so as to be inscribed in one conductor layer;
Forming a second conductor layer connected to the base metal layer on the second surface of the semiconductor substrate from the base metal layer in the through hole;
And a step of removing the base metal layer and the metal mask layer other than the region covered with the second conductor layer.

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