JP2008300588A - Electronic apparatus, and manufacturing method thereof - Google Patents

Electronic apparatus, and manufacturing method thereof Download PDF

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JP2008300588A
JP2008300588A JP2007144492A JP2007144492A JP2008300588A JP 2008300588 A JP2008300588 A JP 2008300588A JP 2007144492 A JP2007144492 A JP 2007144492A JP 2007144492 A JP2007144492 A JP 2007144492A JP 2008300588 A JP2008300588 A JP 2008300588A
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sealing body
wiring board
sealing
resin
semiconductor device
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JP2008300588A5 (en
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Minoru Shinohara
稔 篠原
Takao Sonobe
隆生 園部
Hironori Iwasaki
浩典 岩崎
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability in an electronic apparatus in which semiconductor devices are mounted. <P>SOLUTION: By the formation of a first portion 7e in which a substrate 7g is exposed and a second portion 7h protruding toward a first sealing body 2e from the substrate 7g in a region facing opposedly the first sealing body 2e of a TSOP2 in the main plane 7a of a wiring substrate 7, when in solder connecting the TSOP2, the first sealing body 2e can be supported by the second portion 7h of the wiring substrate 7, a sufficient clearance can be formed between the first sealing body 2e and the first portion 7e of the wiring substrate 7. Thereby, a resin for sealing can be filled up between the first sealing body 2e of the TSOP2 when sealing memory module 3 with resin and the wiring substrate 7 making it possible to prevent the deformation of the first sealing body 2e and the wiring substrate 7. As the result, the improvement of reliability of a memory module 3 can be attained. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、電子装置及びその製造技術に関し、特に、半導体装置を樹脂封止して組み立てが行われる電子装置及びその製造に関する。   The present invention relates to an electronic device and a manufacturing technique thereof, and more particularly to an electronic device that is assembled by resin-sealing a semiconductor device and a manufacturing method thereof.

メモリコアチップと、インターフェースチップと、インターポーザチップと、外部接続用端子とを有するメモリモジュールにおいて、インターポーザチップは、メモリコアチップと同質の半導体材料を基板とし、一方の面に外部接続用端子を保持するためのランド、外部接続用端子に接続された配線、および配線を絶縁するための絶縁膜が一体形成されている構成が開示されている（例えば、特許文献１参照）。
特開２００６−３１９２４３号公報 In a memory module having a memory core chip, an interface chip, an interposer chip, and an external connection terminal, the interposer chip uses a semiconductor material of the same quality as the memory core chip as a substrate, and holds the external connection terminal on one surface. A structure is disclosed in which a land, a wiring connected to an external connection terminal, and an insulating film for insulating the wiring are integrally formed (see, for example, Patent Document 1).
JP 2006-319243 A

複数のメモリチップ（半導体チップ）が組み込まれた半導体モジュールとしてメモリモジュール（電子装置）が知られている。すなわち、メモリモジュールではメモリチップが複数個実装され、１パッケージ化されている。   A memory module (electronic device) is known as a semiconductor module in which a plurality of memory chips (semiconductor chips) are incorporated. That is, in the memory module, a plurality of memory chips are mounted and formed into one package.

前記特許文献１（特開２００６−３１９２４３号公報）には、複数のメモリチップが実装されたメモリモジュールの構造が記載されている。   Patent Document 1 (Japanese Patent Laid-Open No. 2006-319243) describes a structure of a memory module on which a plurality of memory chips are mounted.

しかしながら、メモリモジュール等の組み立てにおいて、半導体チップを入手しようとするとその入手性がパッケージされたものに比べて悪い。また、チップ単体では高度な電気的選別が困難で、パッケージ品に対して劣っている場合が多い。さらに、半導体チップのテストはウェハ状態で行われるためコストが高く、これに対してパッケージのテストはコストが安い上に、信頼性についても半導体チップよりパッケージの方がスクリーニングが十分に行われているため高い。   However, in assembling a memory module or the like, if an attempt is made to obtain a semiconductor chip, the availability is worse than that obtained by packaging. In addition, it is difficult to perform high-level electrical sorting with a single chip, and it is often inferior to packaged products. Furthermore, since the test of the semiconductor chip is performed in a wafer state, the cost is high. On the other hand, the cost of the package test is low, and the screening of the package is more sufficiently performed than the semiconductor chip in terms of reliability. High because.

以上の理由から複数のパッケージ（半導体装置）を１パッケージ化する要求があり、本発明者は、複数の半導体装置を搭載した半導体モジュール（電子装置）について検討した結果、以下のような問題点を見出した。   For the above reasons, there is a request to make a plurality of packages (semiconductor devices) into one package. As a result of studying a semiconductor module (electronic device) on which a plurality of semiconductor devices are mounted, the present inventors have found the following problems. I found it.

すなわち、封止体からリードが露出している構造の半導体装置を配線基板上に搭載した場合、封止体の裏面と配線基板との間の隙間が狭いため、封止の際の樹脂が入り込まず、封止体と配線基板との間に隙間が形成されてしまう。   That is, when a semiconductor device having a structure in which the lead is exposed from the sealing body is mounted on the wiring board, the gap between the back surface of the sealing body and the wiring board is narrow, so that the resin enters during sealing. In other words, a gap is formed between the sealing body and the wiring board.

その結果、半導体装置の封止体において樹脂モールディング時にその上部側から掛かる圧力により、封止体が折れ曲がるという問題が起こる。   As a result, there arises a problem that the sealing body bends due to the pressure applied from the upper side of the sealing body of the semiconductor device during resin molding.

あるいは、半導体装置と配線基板における熱膨張係数や剛性の大きさの差によって配線基板が変形するという問題も起こる。その結果、半導体モジュールの信頼性が低下することも問題である。   Alternatively, there also arises a problem that the wiring board is deformed due to a difference in thermal expansion coefficient and rigidity between the semiconductor device and the wiring board. As a result, the reliability of the semiconductor module is also problematic.

本発明の目的は、半導体装置が搭載された電子装置において信頼性を向上させることができる技術を提供することにある。   An object of the present invention is to provide a technique capable of improving reliability in an electronic device in which a semiconductor device is mounted.

また、本発明の他の目的は、半導体装置が搭載された電子装置において半導体装置の封止体の変形を防止することができる技術を提供することにある。   Another object of the present invention is to provide a technique capable of preventing deformation of a sealing body of a semiconductor device in an electronic device on which the semiconductor device is mounted.

また、本発明の他の目的は、半導体装置が搭載された電子装置において配線基板の変形を防止することができる技術を提供することにある。   Another object of the present invention is to provide a technique capable of preventing deformation of a wiring board in an electronic device on which a semiconductor device is mounted.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

すなわち、本発明は、半導体チップを樹脂封止する第１封止体を有し、前記第１封止体から露出するリードを備えた半導体装置と、基材、絶縁膜、電極及び配線部を備え、主面と前記主面に対向する裏面を有し、前記リードが前記電極に半田接続されて前記主面上に前記半導体装置を搭載する配線基板と、前記半導体装置を樹脂封止する第２封止体と、前記配線基板の裏面に設けられた複数の外部端子とを有するものである。さらに、前記配線基板の主面における前記第１封止体と対向する領域に、前記基材が露出した第１の部分と、前記基材から前記第１封止体に向かって突出する第２の部分とが形成され、前記第１封止体と前記配線基板との間に前記第２封止体の一部が形成されているものである。   That is, the present invention has a first sealing body for resin-sealing a semiconductor chip, and includes a semiconductor device including a lead exposed from the first sealing body, a base material, an insulating film, an electrode, and a wiring portion. A wiring board having a main surface and a back surface opposite to the main surface, the lead being soldered to the electrode and mounting the semiconductor device on the main surface, and a resin-sealing first semiconductor device 2 It has a sealing body and a plurality of external terminals provided on the back surface of the wiring board. Furthermore, in the area | region which opposes the said 1st sealing body in the main surface of the said wiring board, the 2nd which protrudes toward the said 1st sealing body from the said base material which exposed the said base material And a part of the second sealing body is formed between the first sealing body and the wiring board.

また、本発明は、半導体チップを樹脂封止する第１封止体を有し、前記第１封止体から露出するリードを備えた半導体装置を準備する工程と、主面と前記主面に対向する裏面を有し、基材が露出した第１の部分と前記基材から突出した細長い第２の部分とを有する配線基板を準備する工程とを有するものである。さらに、前記配線基板における前記第１の部分と前記第２の部分が前記第１封止体と前記配線基板の間に配置されるように前記配線基板上に前記半導体装置を配置した後、前記リードを前記配線基板の電極に半田接続して前記配線基板の主面上に前記半導体装置を搭載する工程を有するものである。さらに、前記細長い第２の部分の延在方向に沿って封止用樹脂を前記第１封止体と前記配線基板の間に注入するとともに、前記封止用樹脂で前記半導体装置を覆って第２封止体を形成する工程を有するものである。   The present invention also includes a step of preparing a semiconductor device having a first sealing body for resin-sealing a semiconductor chip and having a lead exposed from the first sealing body, and a main surface and the main surface. And a step of preparing a wiring board having a back surface which is opposed and having a first portion where the base material is exposed and an elongated second portion protruding from the base material. Furthermore, after disposing the semiconductor device on the wiring substrate such that the first portion and the second portion of the wiring substrate are disposed between the first sealing body and the wiring substrate, The method includes a step of mounting the semiconductor device on a main surface of the wiring board by soldering a lead to an electrode of the wiring board. Further, a sealing resin is injected between the first sealing body and the wiring board along the extending direction of the elongated second portion, and the semiconductor device is covered with the sealing resin and is 2 It has the process of forming a sealing body.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

配線基板の主面における半導体装置の第１封止体と対向する領域に、基材が露出した第１の部分と、基材から第１封止体に向かって突出した第２の部分とが形成されたことにより、半導体装置の実装の際のリードの半田接続時に、配線基板の第２の部分によって第１封止体を支えることができるため、第１封止体と配線基板の第１の部分との間に十分な隙間を形成することができる。したがって、電子装置の樹脂封止の際に、半導体装置の第１封止体と配線基板の第１の部分との間に封止用樹脂を充填することができ、第１封止体と配線基板との間に隙間は形成されないため、第１封止体や配線基板が変形することを防止できる。   In a region facing the first sealing body of the semiconductor device on the main surface of the wiring board, a first portion where the base material is exposed and a second portion protruding from the base material toward the first sealing body By being formed, the first sealing body can be supported by the second portion of the wiring board when the lead is soldered when the semiconductor device is mounted. Therefore, the first sealing body and the first of the wiring board can be supported. A sufficient gap can be formed between these portions. Therefore, at the time of resin sealing of the electronic device, the sealing resin can be filled between the first sealing body of the semiconductor device and the first portion of the wiring substrate. Since no gap is formed between the substrate and the substrate, it is possible to prevent the first sealing body and the wiring substrate from being deformed.

その結果、半導体装置が組み込まれる電子装置の信頼性の向上を図ることができる。   As a result, the reliability of the electronic device in which the semiconductor device is incorporated can be improved.

以下の実施の形態では特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。   In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

さらに、以下の実施の形態では便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明などの関係にある。   Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

また、以下の実施の形態において、要素の数など（個数、数値、量、範囲などを含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合などを除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良いものとする。   Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

（実施の形態１）
図１は本発明の実施の形態１の電子装置の構造の一例を封止体を透過して示す平面図、図２は図１のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図３は図２に示す構造の主要部の詳細構造の一例を示す拡大部分断面図、図４は図１の電子装置の組み立てにおける半導体装置実装前の構造の一例を示す拡大部分断面図、図５は図１の電子装置の組み立てにおける半導体装置の半田接合後の構造の一例を示す拡大部分断面図である。 (Embodiment 1)
FIG. 1 is a plan view showing an example of the structure of an electronic device according to Embodiment 1 of the present invention through a sealing body, and FIG. 2 is a cross section showing an example of a structure cut along the line AA in FIG. 3 is an enlarged partial cross-sectional view showing an example of a detailed structure of a main part of the structure shown in FIG. 2, and FIG. 4 is an enlarged partial cross-sectional view showing an example of the structure before mounting the semiconductor device in the assembly of the electronic device of FIG. FIG. 5 is an enlarged partial cross-sectional view showing an example of the structure after solder bonding of the semiconductor device in the assembly of the electronic device of FIG.

図１〜図３に示す本実施の形態１の電子装置は、内部に半導体装置が組み込まれた樹脂封止型のものであり、本実施の形態１では、前記電子装置の一例として、メモリモジュール３を取り上げて説明する。   The electronic device according to the first embodiment shown in FIGS. 1 to 3 is a resin-sealed type in which a semiconductor device is incorporated. In the first embodiment, a memory module is used as an example of the electronic device. 3 is taken up and explained.

メモリモジュール３の構成について説明すると、メモリ回路を備えた半導体チップ１を有する半導体装置であるＴＳＯＰ（Thin Small Outline Package) ２と、このＴＳＯＰ２が搭載される配線基板７と、ＴＳＯＰ２を樹脂封止する第２封止体６と、配線基板７の裏面７ｂに設けられた複数の外部端子７ｍとを有している。   The configuration of the memory module 3 will be described. A TSOP (Thin Small Outline Package) 2 which is a semiconductor device having the semiconductor chip 1 provided with a memory circuit, a wiring board 7 on which the TSOP 2 is mounted, and the TSOP 2 are resin-sealed. The second sealing body 6 has a plurality of external terminals 7 m provided on the back surface 7 b of the wiring board 7.

メモリモジュール３に組み込まれるＴＳＯＰ２は、半導体チップ１を支持するタブ２ａと、ワイヤ２ｄを介して半導体チップ１と電気的に接続する複数のインナリード（リード）２ｂと、それぞれのインナリード２ｂと一体に形成された複数のアウタリード（リード）２ｃと、半導体チップ１、タブ２ａ、複数のワイヤ２ｄ及び複数のインナリード２ｂを樹脂封止する第１封止体２ｅとを有している。複数のアウタリード２ｃは第１封止体２ｅの相互に対向する２つの側部から相反する方向に露出しており、実装用にガルウィング状に曲げ成形されている。   The TSOP 2 incorporated in the memory module 3 includes a tab 2a that supports the semiconductor chip 1, a plurality of inner leads (leads) 2b that are electrically connected to the semiconductor chip 1 via wires 2d, and each inner lead 2b. A plurality of outer leads (leads) 2c, and a first sealing body 2e for resin-sealing the semiconductor chip 1, the tab 2a, the plurality of wires 2d, and the plurality of inner leads 2b. The plurality of outer leads 2c are exposed in opposite directions from two mutually opposite side portions of the first sealing body 2e, and are bent into a gull wing shape for mounting.

本実施の形態１のメモリモジュール３では、図１及び図２に示すように、２つのＴＳＯＰ２が配線基板７の主面７ａ上に搭載されている。配線基板７は、図３に示すように、主面７ａと主面７ａに対向する裏面７ｂを有するとともに、基材７ｇ、絶縁膜７ｄ、電極７ｃ及び銅パターン（配線部）７ｆを備えている。これにより、ＴＳＯＰ２が搭載された際には、ＴＳＯＰ２のリードであるアウタリード２ｃが配線基板７の主面７ａの電極７ｃに半田５を介して電気的に接続される。   In the memory module 3 according to the first embodiment, as shown in FIGS. 1 and 2, two TSOPs 2 are mounted on the main surface 7 a of the wiring board 7. As shown in FIG. 3, the wiring board 7 has a main surface 7a and a back surface 7b opposite to the main surface 7a, and includes a base material 7g, an insulating film 7d, an electrode 7c, and a copper pattern (wiring portion) 7f. . Thus, when the TSOP 2 is mounted, the outer lead 2 c that is the lead of the TSOP 2 is electrically connected to the electrode 7 c on the main surface 7 a of the wiring substrate 7 via the solder 5.

また、メモリモジュール３の配線基板７には、図３に示すように、その主面７ａにおいて、ＴＳＯＰ２の第１封止体２ｅと対向する領域に、基材７ｇが露出した第１の部分７ｅと、基材７ｇから第１封止体２ｅに向かって突出する第２の部分７ｈとが形成されている。   Further, as shown in FIG. 3, the wiring board 7 of the memory module 3 has a first portion 7e in which the base material 7g is exposed in a region of the main surface 7a facing the first sealing body 2e of the TSOP2. And the 2nd part 7h which protrudes toward the 1st sealing body 2e from the base material 7g is formed.

ここで、配線基板７の主面７ａにおけるＴＳＯＰ２の第１封止体２ｅと対向する領域に形成された第１の部分７ｅは、基材７ｇが露出された領域であり、銅パターン７ｆや絶縁膜７ｄが形成されていない領域である。   Here, the 1st part 7e formed in the area | region facing the 1st sealing body 2e of TSOP2 in the main surface 7a of the wiring board 7 is an area | region where the base material 7g was exposed, and copper pattern 7f and insulation This is a region where the film 7d is not formed.

一方、ＴＳＯＰ２の第１封止体２ｅと対向する領域に形成された配線基板７の主面７ａの第２の部分７ｈは、基材７ｇから第１封止体２ｅに向かって突出した箇所である。この第２の部分７ｈは、例えば、銅パターン７ｆとこの銅パターン７ｆを覆う絶縁膜７ｄ（ソルダレジスト膜）と、絶縁膜７ｄ上に形成されたシルク印刷部４とからなり、合計の高さが、封止用樹脂が入り込むのに最低限必要とされる隙間を形成するための高さを必要とし、その高さは、例えば、最低５０μｍ程度である。一例として、銅パターン７ｆが３６μｍ、絶縁膜７ｄが５〜１０μｍ、シルク印刷部４が１０〜３０μｍである。   On the other hand, the second portion 7h of the main surface 7a of the wiring board 7 formed in the region facing the first sealing body 2e of TSOP2 is a portion protruding from the base material 7g toward the first sealing body 2e. is there. The second portion 7h includes, for example, a copper pattern 7f, an insulating film 7d (solder resist film) covering the copper pattern 7f, and a silk print portion 4 formed on the insulating film 7d, and has a total height. However, it requires a height for forming a gap that is at least required for the sealing resin to enter, and the height is, for example, at least about 50 μm. As an example, the copper pattern 7 f is 36 μm, the insulating film 7 d is 5 to 10 μm, and the silk print portion 4 is 10 to 30 μm.

このように、配線基板７上の第１封止体２ｅの下部の領域に、封止用樹脂が入り込むのに必要最低限の隙間を形成するための高さを有した第２の部分７ｈと、銅パターン７ｆや絶縁膜７ｄが形成されずに基材７ｇが露出した第１の部分７ｅとを形成することで、ＴＳＯＰ２の配線基板７への半田接続時に第１封止体２ｅが基板側に引き込まれた際に、第１封止体２ｅをその下部に形成された基板側の第２の部分７ｈによって支えることができる。   In this way, the second portion 7h having a height for forming a minimum gap necessary for the sealing resin to enter the region below the first sealing body 2e on the wiring substrate 7; By forming the first portion 7e where the base material 7g is exposed without forming the copper pattern 7f or the insulating film 7d, the first sealing body 2e is placed on the substrate side when the TSOP2 is connected to the wiring substrate 7 by soldering. The first sealing body 2e can be supported by the second portion 7h on the substrate side formed below the first sealing body 2e.

これにより、配線基板７上にＴＳＯＰ２を搭載した際に、第１封止体２ｅと配線基板７との間に封止用樹脂が入り込むために必要な隙間を形成することができる。   Thereby, when TSOP2 is mounted on the wiring board 7, a gap necessary for the sealing resin to enter between the first sealing body 2e and the wiring board 7 can be formed.

したがって、メモリモジュール３では、その組み立ての樹脂封止工程における樹脂注入時に、第１封止体２ｅと配線基板７との間に封止用樹脂を充填することができ、その結果、第１封止体２ｅと配線基板７との間に第２封止体６の一部が形成されている。   Therefore, in the memory module 3, the sealing resin can be filled between the first sealing body 2e and the wiring board 7 at the time of resin injection in the resin sealing step of the assembly, and as a result, the first sealing A part of the second sealing body 6 is formed between the stationary body 2 e and the wiring board 7.

なお、第２の部分７ｈの構成としては、銅パターン７ｆと絶縁膜７ｄとシルク印刷部４の組み合わせに限定されるものではなく、これらのうちのいずれか１つのみによって形成されていてもよく、あるいはいずれか２つの組み合わせで形成されていてもよい。   Note that the configuration of the second portion 7h is not limited to the combination of the copper pattern 7f, the insulating film 7d, and the silk print portion 4, and may be formed of only one of these. Or may be formed of any two combinations.

図４及び図５は、メモリモジュール３の組み立てにおけるＴＳＯＰ２の実装状態の一例を示すものである。図４に示すように、例えば、電極７ｃ上に半田５を予め厚めに塗布しておくことで、電極７ｃのパターンが細い場合であってもアウタリード２ｃの接合位置を高くすることができ、オープン不良の発生を防ぐことができる。   4 and 5 show an example of the mounting state of the TSOP 2 in the assembly of the memory module 3. As shown in FIG. 4, for example, by applying the solder 5 thickly on the electrode 7c in advance, the joining position of the outer lead 2c can be increased even when the pattern of the electrode 7c is thin, and the open The occurrence of defects can be prevented.

また、半田リフロー時には、図５に示すように、半田５が溶けてアウタリード２ｃが沈み込んだ際にも第１封止体２ｅを第２の部分７ｈによって支えることができ、第１封止体２ｅの変形を防ぐことができる。   Further, at the time of solder reflow, as shown in FIG. 5, the first sealing body 2e can be supported by the second portion 7h even when the solder 5 melts and the outer lead 2c sinks. 2e can be prevented from being deformed.

このように本実施の形態１のメモリモジュール３及びその組み立てによれば、配線基板７の主面７ａにおけるＴＳＯＰ２の第１封止体２ｅと対向する領域に、基材７ｇが露出した第１の部分７ｅと、基材７ｇから第１封止体２ｅに向かって突出した第２の部分７ｈとが形成されたことにより、ＴＳＯＰ２の実装の際のアウタリード２ｃの半田接続時に、配線基板７の第２の部分７ｈによって第１封止体２ｅを支えることができる。   As described above, according to the memory module 3 and the assembly thereof in the first embodiment, the first base material 7g is exposed in the region facing the first sealing body 2e of the TSOP2 on the main surface 7a of the wiring board 7. Since the portion 7e and the second portion 7h protruding from the base material 7g toward the first sealing body 2e are formed, when the outer lead 2c is connected to the solder when the TSOP 2 is mounted, The first sealing body 2e can be supported by the second portion 7h.

すなわち、半田５が溶融してアウタリード２ｃが沈んで第１封止体２ｅが基板側に引き込まれた際に、第１封止体２ｅをその下部に形成された基板側の第２の部分７ｈによって支えることができる。   That is, when the solder 5 melts and the outer lead 2c sinks and the first sealing body 2e is drawn to the substrate side, the first sealing body 2e is formed on the lower side of the substrate-side second portion 7h. Can be supported by.

これにより、第１封止体２ｅと配線基板７の第１の部分７ｅとの間に封止用樹脂を入り込ませるのに必要な十分な隙間を形成することができる。したがって、メモリモジュール３の組み立ての樹脂封止工程における樹脂注入時に、ＴＳＯＰ２の第１封止体２ｅと配線基板７の第１の部分７ｅとの間に封止用樹脂を充填することができる。   As a result, a sufficient gap can be formed between the first sealing body 2e and the first portion 7e of the wiring board 7 so as to allow the sealing resin to enter. Therefore, the sealing resin can be filled between the first sealing body 2 e of the TSOP 2 and the first portion 7 e of the wiring substrate 7 at the time of resin injection in the resin sealing process for assembling the memory module 3.

その結果、樹脂封止時に、ＴＳＯＰ２の第１封止体２ｅと配線基板７との間に隙間が形成されることは無いため、第１封止体２ｅや配線基板７が変形することを防止でき、これにより、ＴＳＯＰ２が組み込まれるメモリモジュール３の信頼性の向上を図ることができる。   As a result, no gap is formed between the first sealing body 2e of the TSOP 2 and the wiring board 7 at the time of resin sealing, thereby preventing the first sealing body 2e and the wiring board 7 from being deformed. Thus, the reliability of the memory module 3 in which the TSOP 2 is incorporated can be improved.

（実施の形態２）
図６は本発明の実施の形態２の電子装置の構造の一例を封止体を透過して示す平面図、図７は図６のＡ−Ａ線に沿って切断した構造の一例を示す断面図、図８は図７のＢ部の構造の一例を示す拡大部分断面図、図９は図６に示す電子装置に組み込まれる配線基板の第１及び第２の部分の形成範囲の一例を示す平面図、図１０は図６に示す電子装置の組み立ての樹脂封止工程における樹脂の注入方向の一例を示す平面図である。さらに、図１１は本発明の実施の形態２の変形例の電子装置における第２の部分の構造を示す平面図である。 (Embodiment 2)
6 is a plan view showing an example of the structure of the electronic device according to the second embodiment of the present invention through the sealing body, and FIG. 7 is a cross-sectional view showing an example of the structure cut along the line AA in FIG. 8 is an enlarged partial cross-sectional view showing an example of the structure of part B in FIG. 7. FIG. 9 shows an example of the formation range of the first and second parts of the wiring board incorporated in the electronic device shown in FIG. FIG. 10 is a plan view showing an example of the resin injection direction in the resin sealing step of assembling the electronic device shown in FIG. Further, FIG. 11 is a plan view showing the structure of the second portion in the electronic device according to the modification of the second embodiment of the present invention.

図６〜図８に示す本実施の形態２の電子装置は、配線基板７上にＱＦＰ（Quad Flat Package)８タイプの半導体装置と、ＴＳＯＰ２タイプの半導体装置を搭載したものであり、ＱＦＰ８は制御用のマイコンチップ、ＴＳＯＰ２はメモリチップである。すなわち、この場合の電子装置は、ＳＩＰ（System In Package)９である。   6 to 8 includes a QFP (Quad Flat Package) 8 type semiconductor device and a TSOP2 type semiconductor device mounted on a wiring board 7, and the QFP 8 is controlled. The microcomputer chip TSOP2 is a memory chip. That is, the electronic device in this case is a SIP (System In Package) 9.

本実施の形態２のＳＩＰ９では、その配線基板７の主面７ａ上の第１封止体２ｅに対応する領域に、図９に示すように、細長い第２の部分７ｈが２列に平行な位置に形成されている。   In the SIP 9 according to the second embodiment, in the region corresponding to the first sealing body 2e on the main surface 7a of the wiring substrate 7, the elongated second portions 7h are parallel to two rows as shown in FIG. Formed in position.

このように、細長い第２の部分７ｈを２列に平行な位置に形成することで、半田溶融時に第１封止体２ｅが基板方向に引き込まれた際にも、第１封止体２ｅを安定して支えることができる。   In this way, by forming the elongated second portions 7h in positions parallel to the two rows, the first sealing body 2e can be moved even when the first sealing body 2e is pulled in the direction of the substrate during solder melting. Can be supported stably.

なお、図８に示すように第１封止体２ｅと第２の部分７ｈとの間には僅かな隙間は形成されてもよい。すなわち、樹脂注入時に第１封止体２ｅが変形しない程度の僅かな隙間であれば、第１封止体２ｅと第２の部分７ｈとの間に隙間は形成されていてもよい。   As shown in FIG. 8, a slight gap may be formed between the first sealing body 2e and the second portion 7h. That is, a clearance may be formed between the first sealing body 2e and the second portion 7h as long as the clearance is such that the first sealing body 2e is not deformed when the resin is injected.

さらに、ＳＩＰ９の組み立ての樹脂封止工程における樹脂注入時に、図１０に示すように、細長い第２の部分７ｈの延在方向に沿って封止用樹脂を第１封止体２ｅと図８に示す配線基板７の間に注入することで、封止用樹脂は細長い第２の部分７ｈに沿って流れるため、封止用樹脂を円滑に第１封止体２ｅと配線基板７の間に充填することができる。   Further, at the time of resin injection in the resin sealing step of assembling the SIP 9, as shown in FIG. 10, the sealing resin is transferred to the first sealing body 2e and FIG. 8 along the extending direction of the elongated second portion 7h. By injecting between the illustrated wiring boards 7, the sealing resin flows along the elongated second portion 7h, so that the sealing resin is smoothly filled between the first sealing body 2e and the wiring board 7. can do.

なお、図１１は第２の部分７ｈの変形例の構造を示すものであるが、第２の部分７ｈを複数箇所に設けることで、半田溶融時に第１封止体２ｅが基板方向に引き込まれた際にも、細長い第２の部分７ｈが２列に平行に設けられた場合と同様に、第１封止体２ｅを安定して支えることができる。   FIG. 11 shows a structure of a modified example of the second portion 7h. However, by providing the second portion 7h at a plurality of locations, the first sealing body 2e is drawn in the direction of the substrate when the solder is melted. In this case, the first sealing body 2e can be stably supported as in the case where the elongated second portions 7h are provided in parallel in two rows.

本実施の形態２のＳＩＰ９のその他の構造については、実施の形態１のメモリモジュール３と同様であるため、その重複説明は省略する。   Since the other structure of the SIP 9 according to the second embodiment is the same as that of the memory module 3 according to the first embodiment, a duplicate description thereof is omitted.

また、前記ＳＩＰ９によって得られるその他の効果については、前記メモリモジュール３によって得られる効果と同じであるため、その重複説明は省略する。   Further, since other effects obtained by the SIP 9 are the same as the effects obtained by the memory module 3, redundant description thereof is omitted.

（実施の形態３）
図１２は本発明の実施の形態３の電子装置の構造の一例を封止体を透過して示す平面図、図１３は図１２の電子装置の主要部の構造の一例を示す拡大部分断面図、図１４は図１２の電子装置に組み込まれる配線基板の凹部の形成範囲の一例を示す平面図、図１５は図１２の電子装置の組み立てにおける半導体装置実装前の構造の一例を示す拡大部分断面図である。さらに、図１６は図１２の電子装置の組み立てにおける半導体装置の半田接合後の構造の一例を示す拡大部分断面図、図１７は図１２の電子装置の組み立てにおける樹脂モールディング後の構造の一例を示す拡大部分断面図である。 (Embodiment 3)
FIG. 12 is a plan view showing an example of the structure of the electronic device according to the third embodiment of the present invention through a sealing body, and FIG. 13 is an enlarged partial sectional view showing an example of the structure of the main part of the electronic device of FIG. 14 is a plan view showing an example of the formation range of the concave portion of the wiring board incorporated in the electronic device of FIG. 12, and FIG. 15 is an enlarged partial cross section showing an example of the structure before mounting the semiconductor device in the assembly of the electronic device of FIG. FIG. Further, FIG. 16 is an enlarged partial sectional view showing an example of the structure after solder bonding of the semiconductor device in the assembly of the electronic device of FIG. 12, and FIG. 17 shows an example of the structure after resin molding in the assembly of the electronic device of FIG. It is an expanded partial sectional view.

図１２〜図１４に示す本実施の形態３の電子装置は、実施の形態２の電子装置と同様に、配線基板７上にマイコンチップであるＱＦＰ８と、メモリチップであるＴＳＯＰ２が搭載された構造のＳＩＰ９である。配線基板７には、その主面７ａにおける第１封止体２ｅと対向する領域に、基材７ｇが露出した状態で凹部であるザグリ７ｉが形成されている。ザグリ７ｉは、図１３及び図１４に示すように、ＱＦＰ８やＴＳＯＰ２のそれぞれの第１封止体２ｅの裏面２ｆに対応した領域に形成されており、ザグリ面には銅パターン７ｆや絶縁膜７ｄは形成されていない。   The electronic device according to the third embodiment shown in FIGS. 12 to 14 has a structure in which a microcomputer chip QFP 8 and a memory chip TSOP 2 are mounted on a wiring board 7, as in the electronic device according to the second embodiment. SIP9. In the wiring substrate 7, a counterbore 7i that is a recess is formed in a region of the main surface 7a facing the first sealing body 2e with the base material 7g exposed. As shown in FIGS. 13 and 14, the counterbore 7i is formed in a region corresponding to the back surface 2f of the first sealing body 2e of each of the QFP 8 and TSOP2, and the counterbore surface has a copper pattern 7f and an insulating film 7d. Is not formed.

図１５〜図１７は本実施の形態３のＳＩＰ９の組み立てにおける半導体装置（ＴＳＯＰ２）の実装〜封止までを示すものである。図１５に示すように配線基板７の主面７ａ上に半田５を介してＴＳＯＰ２を配置し、その後、図１６に示すように、リフローによって半田５を溶融してアウタリード２ｃと配線基板７の電極７ｃとを半田接続する。   15 to 17 show from mounting to sealing of the semiconductor device (TSOP2) in the assembly of the SIP 9 of the third embodiment. As shown in FIG. 15, the TSOP 2 is arranged on the main surface 7a of the wiring board 7 via the solder 5, and then the solder 5 is melted by reflow to melt the outer lead 2c and the electrode of the wiring board 7 as shown in FIG. 7c is soldered.

その際、半田５が溶けてアウタリード２ｃが沈み込んで第１封止体２ｅが基板側に引き込まれた際にも、第１封止体２ｅに対応した領域にザグリ７ｉが形成されているため、第１封止体２ｅと配線基板７との間に封止用樹脂を入り込ませるのに必要な十分な隙間を形成することができる。   At that time, the counterbore 7i is formed in the region corresponding to the first sealing body 2e even when the solder 5 melts and the outer lead 2c sinks and the first sealing body 2e is pulled to the substrate side. A sufficient gap necessary to allow the sealing resin to enter between the first sealing body 2e and the wiring board 7 can be formed.

したがって、図１７に示す樹脂封止工程における樹脂注入時に、ＴＳＯＰ２の第１封止体２ｅと配線基板７のザグリ７ｉとの間に封止用樹脂を充填することができ、第１封止体２ｅと配線基板７のザグリ７ｉとの間に第２封止体６の一部が形成される。   Therefore, at the time of resin injection in the resin sealing step shown in FIG. 17, the sealing resin can be filled between the first sealing body 2e of TSOP2 and the counterbore 7i of the wiring board 7, and the first sealing body A part of the second sealing body 6 is formed between 2 e and the counterbore 7 i of the wiring board 7.

その結果、樹脂封止時に、ＴＳＯＰ２の第１封止体２ｅと配線基板７との間に隙間が形成されることは無いため、第１封止体２ｅや配線基板７が変形することを防止でき、これにより、ＴＳＯＰ２が組み込まれるＳＩＰ９の信頼性の向上を図ることができる。このことはＱＦＰ８についても同様である。   As a result, no gap is formed between the first sealing body 2e of the TSOP 2 and the wiring board 7 at the time of resin sealing, thereby preventing the first sealing body 2e and the wiring board 7 from being deformed. Thus, the reliability of the SIP 9 in which the TSOP 2 is incorporated can be improved. The same applies to QFP8.

本実施の形態３のＳＩＰ９によって得られるその他の効果については、前記実施の形態１のメモリモジュール３によって得られる効果と同じであるため、その重複説明は省略する。   The other effects obtained by the SIP 9 of the third embodiment are the same as the effects obtained by the memory module 3 of the first embodiment, and therefore redundant description thereof is omitted.

（実施の形態４）
図１８は本発明の実施の形態４の電子装置の構造の一例を封止体を透過して示す平面図、図１９は図１８の電子装置の主要部の構造の一例を示す拡大部分断面図、図２０は図１８の電子装置に組み込まれる配線基板のシルク印刷の形成範囲の一例を示す平面図、図２１は図１８の電子装置の組み立ての樹脂封止工程における樹脂の注入方向の一例を示す平面図である。 (Embodiment 4)
18 is a plan view showing an example of the structure of the electronic device according to the fourth embodiment of the present invention through a sealing body, and FIG. 19 is an enlarged partial sectional view showing an example of the structure of the main part of the electronic device of FIG. 20 is a plan view showing an example of the silk printing formation range of the wiring board incorporated in the electronic device of FIG. 18, and FIG. 21 is an example of the resin injection direction in the resin sealing step of assembling the electronic device of FIG. FIG.

図１８〜図２０に示す本実施の形態４の電子装置は、実施の形態２の電子装置と同様に、配線基板７上にマイコンチップであるＱＦＰ８と、メモリチップであるＴＳＯＰ２が搭載された構造のＳＩＰ９である。配線基板７には、その主面７ａにおける第１封止体２ｅと対向する領域に、第１封止体２ｅの裏面全体に亘って対向し、かつ第１封止体２ｅに向かって突出する第３の部分７ｊが形成されている。   The electronic device according to the fourth embodiment shown in FIGS. 18 to 20 has a structure in which the microcomputer chip QFP 8 and the memory chip TSOP 2 are mounted on the wiring board 7 in the same manner as the electronic device according to the second embodiment. SIP9. The wiring substrate 7 is opposed to the region of the main surface 7a facing the first sealing body 2e across the entire back surface of the first sealing body 2e and protrudes toward the first sealing body 2e. A third portion 7j is formed.

すなわち、第１封止体２ｅの下部にはその裏面全体に亘って対応して第３の部分７ｊが配置されていて、封止用樹脂が第１封止体２ｅの下部、すなわち、第１封止体２ｅと配線基板７の間にもぐり込めない構造となっている。   That is, the lower portion of the first sealing body 2e is provided with a third portion 7j corresponding to the entire back surface thereof, and the sealing resin is located below the first sealing body 2e, that is, the first portion. It has a structure that cannot be inserted between the sealing body 2e and the wiring board 7.

なお、図１９に示すように第１封止体２ｅと第３の部分７ｊとの間には僅かな隙間は形成されてもよい。すなわち、樹脂注入時に第１封止体２ｅが変形しない程度の僅かな隙間であれば、第１封止体２ｅと第３の部分７ｊとの間に隙間は形成されていてもよい。   As shown in FIG. 19, a slight gap may be formed between the first sealing body 2e and the third portion 7j. That is, a clearance may be formed between the first sealing body 2e and the third portion 7j as long as the clearance is such that the first sealing body 2e is not deformed when the resin is injected.

また、本実施の形態４の第３の部分７ｊは、実施の形態１の第２の部分７ｈと同様に、銅パターン７ｆと絶縁膜７ｄとシルク印刷からなるが、前記シルク印刷は、第１封止体２ｅの裏面全体に亘って対向するような図２０に示すベタ印刷である広域シルク印刷部４ａとなっている。   The third portion 7j of the fourth embodiment is composed of a copper pattern 7f, an insulating film 7d, and silk printing, similar to the second portion 7h of the first embodiment. The wide area silk printing portion 4a which is the solid printing shown in FIG. 20 that faces the entire back surface of the sealing body 2e.

第３の部分７ｊの構成としては、銅パターン７ｆと絶縁膜７ｄとシルク印刷等の組み合わせに限定されるものではなく、これらのうちのいずれか１つのみによって形成されていてもよく、あるいはいずれか２つの組み合わせで形成されていてもよい。   The configuration of the third portion 7j is not limited to the combination of the copper pattern 7f, the insulating film 7d, silk printing, and the like, and may be formed by any one of these, or any Or a combination of the two.

すなわち、第３の部分７ｊの最上層に形成される部材が、ベタの広域パターンとして形成可能な部材（層）であれば、シルク印刷以外のものであってもよい。   That is, as long as the member formed in the uppermost layer of the third portion 7j is a member (layer) that can be formed as a solid wide-area pattern, it may be other than silk printing.

なお、本実施の形態４のＳＩＰ９の組み立ての樹脂封止工程における樹脂注入時には、図２１に示すようなレジン注入方向から樹脂を注入することで第２封止体６を形成することができる。   At the time of resin injection in the resin sealing step for assembling the SIP 9 of the fourth embodiment, the second sealing body 6 can be formed by injecting resin from the resin injection direction as shown in FIG.

本実施の形態４のＳＩＰ９によれば、配線基板７の主面７ａにおける第１封止体２ｅと対向する領域に、第１封止体２ｅの裏面全体に亘って対向し、かつ第１封止体２ｅに向かって突出する第３の部分７ｊが形成されているため、樹脂注入時に、第１封止体２ｅと配線基板７との間に封止用樹脂が入り込むことはない。   According to the SIP 9 of the fourth embodiment, the main surface 7a of the wiring substrate 7 is opposed to the region facing the first sealing body 2e across the entire back surface of the first sealing body 2e, and the first sealing is performed. Since the third portion 7j protruding toward the stop body 2e is formed, the sealing resin does not enter between the first sealing body 2e and the wiring board 7 at the time of resin injection.

すなわち、第１封止体２ｅの下部には常にその裏面全体に亘って第３の部分７ｊが配置されており、したがって、樹脂封止時に、ＴＳＯＰ２の第１封止体２ｅと配線基板７との間に隙間が形成されることは無い。その結果、第１封止体２ｅや配線基板７が変形することを防止でき、これにより、ＴＳＯＰ２が組み込まれるＳＩＰ９の信頼性の向上を図ることができる。このことはＱＦＰ８についても同様である。   That is, the lower portion of the first sealing body 2e is always provided with the third portion 7j over the entire back surface thereof. Therefore, at the time of resin sealing, the first sealing body 2e of the TSOP 2 and the wiring board 7 No gap is formed between the two. As a result, it is possible to prevent the first sealing body 2e and the wiring board 7 from being deformed, thereby improving the reliability of the SIP 9 in which the TSOP2 is incorporated. The same applies to QFP8.

本実施の形態４のＳＩＰ９によって得られるその他の効果については、前記実施の形態１のメモリモジュール３によって得られる効果と同じであるため、その重複説明は省略する。   The other effects obtained by the SIP 9 of the fourth embodiment are the same as the effects obtained by the memory module 3 of the first embodiment, and a duplicate description thereof is omitted.

（実施の形態５）
図２２は本発明の実施の形態５の電子装置の構造の一例を封止体を透過して示す平面図、図２３は図２２の電子装置の主要部の構造の一例を示す拡大部分断面図、図２４は図２２の電子装置に組み込まれる配線基板の主面の構造の一例を示す平面図である。 (Embodiment 5)
22 is a plan view showing an example of the structure of an electronic device according to Embodiment 5 of the present invention through a sealing body, and FIG. 23 is an enlarged partial sectional view showing an example of the structure of the main part of the electronic device of FIG. 24 is a plan view showing an example of the structure of the main surface of the wiring board incorporated in the electronic device of FIG.

図２２〜図２４に示す本実施の形態５の電子装置は、実施の形態２の電子装置と同様に、配線基板７上にマイコンチップであるＱＦＰ８と、メモリチップであるＴＳＯＰ２が搭載された構造のＳＩＰ９である。   The electronic device according to the fifth embodiment shown in FIGS. 22 to 24 has a structure in which a QFP 8 that is a microcomputer chip and a TSOP2 that is a memory chip are mounted on a wiring board 7 in the same manner as the electronic device according to the second embodiment. SIP9.

図２２〜図２４に示す本実施の形態５のＳＩＰ９は、第１封止体２ｅと配線基板７の間、及び第１封止体２ｅの側部の周囲にアンダーフィル１０を充填したものである。アンダーフィル１０の場合、第１封止体２ｅと配線基板７の隙間が狭い場合であってもアンダーフィル１０が確実に前記隙間に入り込むため、アンダーフィル充填後に、第１封止体２ｅと配線基板７の間に隙間が形成されることは無い。   The SIP 9 of the fifth embodiment shown in FIGS. 22 to 24 is one in which the underfill 10 is filled between the first sealing body 2e and the wiring substrate 7 and around the side portion of the first sealing body 2e. is there. In the case of the underfill 10, since the underfill 10 surely enters the gap even when the gap between the first sealing body 2e and the wiring board 7 is narrow, after filling the underfill, the first sealing body 2e and the wiring There is no gap formed between the substrates 7.

その結果、第１封止体２ｅや配線基板７が変形することを防止でき、これにより、ＴＳＯＰ２が組み込まれるＳＩＰ９の信頼性の向上を図ることができる。このことはＱＦＰ８についても同様である。   As a result, it is possible to prevent the first sealing body 2e and the wiring board 7 from being deformed, thereby improving the reliability of the SIP 9 in which the TSOP2 is incorporated. The same applies to QFP8.

本実施の形態５のＳＩＰ９によって得られるその他の効果については、前記実施の形態１のメモリモジュール３によって得られる効果と同じであるため、その重複説明は省略する。   The other effects obtained by the SIP 9 of the fifth embodiment are the same as the effects obtained by the memory module 3 of the first embodiment, and a duplicate description thereof is omitted.

（実施の形態６）
図２５は本発明の実施の形態６の電子装置の構造の一例を封止体を透過して示す平面図、図２６は図２５の電子装置の主要部の構造の一例を示す拡大部分断面図、図２７は図２５の電子装置に組み込まれる配線基板の主面の構造の一例を示す平面図である。 (Embodiment 6)
FIG. 25 is a plan view showing an example of the structure of an electronic device according to Embodiment 6 of the present invention through a sealing body, and FIG. 26 is an enlarged partial sectional view showing an example of the structure of the main part of the electronic device of FIG. 27 is a plan view showing an example of the structure of the main surface of the wiring board incorporated in the electronic device of FIG.

図２５〜図２７に示す本実施の形態６の電子装置は、実施の形態２の電子装置と同様に、配線基板７上にマイコンチップであるＱＦＰ８と、メモリチップであるＴＳＯＰ２が搭載された構造のＳＩＰ９である。   The electronic device of the sixth embodiment shown in FIGS. 25 to 27 has a structure in which the microcomputer chip QFP 8 and the memory chip TSOP 2 are mounted on the wiring board 7 in the same manner as the electronic device of the second embodiment. SIP9.

図２５〜図２７に示す本実施の形態６のＳＩＰ９は、配線基板７の主面７ａの第１封止体２ｅに対応する領域に、配線パターンやソルダレジストが形成されずに基材７ｇが露出しているものである。   In the SIP 9 of the sixth embodiment shown in FIGS. 25 to 27, the base material 7 g is formed in a region corresponding to the first sealing body 2 e of the main surface 7 a of the wiring substrate 7 without forming a wiring pattern or a solder resist. Exposed.

配線基板７の主面７ａの第１封止体２ｅに対応する領域に、配線パターンやソルダレジストを形成しないことにより、第１封止体２ｅと配線基板７の隙間を広げることができるため、樹脂封止工程において封止用樹脂を注入した際に第１封止体２ｅと配線基板７の間に封止用樹脂を充填することができる。   By not forming a wiring pattern or solder resist in a region corresponding to the first sealing body 2e on the main surface 7a of the wiring board 7, the gap between the first sealing body 2e and the wiring board 7 can be widened. When the sealing resin is injected in the resin sealing step, the sealing resin can be filled between the first sealing body 2e and the wiring board 7.

これにより、第１封止体２ｅと配線基板７の間に第２封止体６の一部が形成されるため、第１封止体２ｅや配線基板７が変形することを防止でき、その結果、ＴＳＯＰ２が組み込まれるＳＩＰ９の信頼性の向上を図ることができる。このことはＱＦＰ８についても同様である。   Thereby, since a part of the second sealing body 6 is formed between the first sealing body 2e and the wiring board 7, it is possible to prevent the first sealing body 2e and the wiring board 7 from being deformed. As a result, it is possible to improve the reliability of the SIP 9 in which the TSOP2 is incorporated. The same applies to QFP8.

本実施の形態６のＳＩＰ９によって得られるその他の効果については、前記実施の形態１のメモリモジュール３によって得られる効果と同じであるため、その重複説明は省略する。   Since the other effects obtained by the SIP 9 of the sixth embodiment are the same as the effects obtained by the memory module 3 of the first embodiment, a duplicate description thereof is omitted.

（実施の形態７）
図２８は本発明の実施の形態７の電子装置の組み立てにおける樹脂封止方法の一例を示す部分断面図、図２９は本発明の実施の形態７の電子装置の組み立てにおける変形例の樹脂封止方法を示す部分断面図である。 (Embodiment 7)
FIG. 28 is a partial cross-sectional view showing an example of a resin sealing method in assembling an electronic device according to the seventh embodiment of the present invention. FIG. 29 is a resin sealing of a modified example in assembling the electronic device according to the seventh embodiment of the present invention. It is a fragmentary sectional view showing a method.

本実施の形態７は、配線基板７と第１封止体２ｅの間をモールドレジン（封止用樹脂）１３によって埋める方法について説明するものである。   In the seventh embodiment, a method of filling the space between the wiring substrate 7 and the first sealing body 2e with a mold resin (sealing resin) 13 will be described.

図２８は、トランスファーモールド方式によって配線基板７と第１封止体２ｅの間及びその周囲をモールドレジン１３で埋めるものである。   In FIG. 28, the mold resin 13 fills the space between the wiring board 7 and the first sealing body 2e by the transfer molding method.

まず、貫通孔７ｋが形成された配線基板７を準備し、その後、第１封止体２ｅの裏面２ｆと貫通孔７ｋとが対向するように配線基板７の主面７ａ上にＴＳＯＰ２を配置し、さらに、アウタリード２ｃを配線基板７の電極７ｃ（図２６参照）に半田接続して配線基板７の主面７ａ上にＴＳＯＰ２を搭載する。   First, the wiring board 7 in which the through hole 7k is formed is prepared, and then the TSOP 2 is disposed on the main surface 7a of the wiring board 7 so that the back surface 2f of the first sealing body 2e and the through hole 7k face each other. Further, the outer leads 2 c are soldered to the electrodes 7 c (see FIG. 26) of the wiring board 7, and the TSOP 2 is mounted on the main surface 7 a of the wiring board 7.

その後、樹脂成形金型１１のプランジャ１２によってモールドレジン１３を押し出し、配線基板７の裏面７ｂ側からモールドレジン１３を貫通孔７ｋを介して第１封止体２ｅと配線基板７の間に注入する。さらに、ＴＳＯＰ２の周囲全体をモールドレジン１３で覆って第２封止体６を形成する。   Thereafter, the mold resin 13 is pushed out by the plunger 12 of the resin molding die 11, and the mold resin 13 is injected between the first sealing body 2e and the wiring board 7 through the through hole 7k from the back surface 7b side of the wiring board 7. . Further, the entire periphery of the TSOP 2 is covered with the mold resin 13 to form the second sealing body 6.

このように配線基板７の裏面７ｂ側から貫通孔７ｋを介してモールドレジン１３を配線基板７と第１封止体２ｅの間に注入することで、第１封止体２ｅと配線基板７の間にも確実にモールドレジン１３（封止用樹脂）を充填することができる。   In this way, by injecting the mold resin 13 between the wiring board 7 and the first sealing body 2e from the back surface 7b side of the wiring board 7 through the through hole 7k, the first sealing body 2e and the wiring board 7 are The mold resin 13 (sealing resin) can be reliably filled in between.

これにより、第１封止体２ｅと配線基板７の間に第２封止体６（図２６参照）の一部が形成されるため、第１封止体２ｅや配線基板７が変形することを防止でき、その結果、ＴＳＯＰ２が組み込まれる電子装置の信頼性の向上を図ることができる。   As a result, a part of the second sealing body 6 (see FIG. 26) is formed between the first sealing body 2e and the wiring board 7, so that the first sealing body 2e and the wiring board 7 are deformed. As a result, it is possible to improve the reliability of the electronic device in which the TSOP 2 is incorporated.

なお、図２９は変形例であり、ノズル吐出方式によって配線基板７と第１封止体２ｅの間をモールドレジン１３によって埋めるものである。   FIG. 29 shows a modification, in which the space between the wiring board 7 and the first sealing body 2e is filled with the mold resin 13 by a nozzle discharge method.

すなわち、配線基板７の貫通孔７ｋの裏面７ｂ側にディスペンサノズル１４を配置し、ディスペンサノズル１４からモールドレジン１３を吐出することで、配線基板７の裏面７ｂ側からモールドレジン１３を貫通孔７ｋを介して第１封止体２ｅと配線基板７の間に注入するとともに、ＴＳＯＰ２の周囲全体をモールドレジン１３で覆って前記第２封止体６を形成するものである。   That is, by disposing the dispenser nozzle 14 on the back surface 7b side of the through hole 7k of the wiring substrate 7 and discharging the mold resin 13 from the dispenser nozzle 14, the mold resin 13 is passed through the through hole 7k from the back surface 7b side of the wiring substrate 7. The second sealing body 6 is formed by injecting between the first sealing body 2 e and the wiring substrate 7 and covering the entire periphery of the TSOP 2 with the mold resin 13.

これにより、第１封止体２ｅと配線基板７の間にも確実にモールドレジン１３を充填することができ、その結果、第１封止体２ｅと配線基板７の間に前記第２封止体６の一部を形成することができる。   Accordingly, the mold resin 13 can be reliably filled between the first sealing body 2e and the wiring board 7. As a result, the second sealing is provided between the first sealing body 2e and the wiring board 7. A part of the body 6 can be formed.

以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

例えば、前記実施の形態１〜７では、電子装置に組み込まれるＴＳＯＰ２等の半導体装置が配線基板７上に単層（１段）で実装されている場合を説明したが、電子装置は、図３０及び図３１の変形例に示すように、ＴＳＯＰ２等の半導体装置を２段重ねで実装したメモリモジュール１５等であってもよい。   For example, in the first to seventh embodiments, the case where the semiconductor device such as TSOP2 incorporated in the electronic device is mounted on the wiring substrate 7 in a single layer (one stage) has been described. As shown in the modification of FIG. 31, the memory module 15 or the like in which semiconductor devices such as TSOP2 are mounted in two layers may be used.

また、電子装置の配線基板７上に搭載される半導体装置は、ＴＳＯＰ２やＱＦＰ８に限らず、リードタイプの半導体装置であれば、例えば、ＱＦＮ（Quad Flat Non-leaded Package) 等であってもよい。   The semiconductor device mounted on the wiring board 7 of the electronic device is not limited to the TSOP 2 or the QFP 8, but may be, for example, a QFN (Quad Flat Non-leaded Package) as long as it is a lead type semiconductor device. .

本発明は、半導体装置が組み込まれ、かつ樹脂封止が行われて組み立てられる電子装置に好適である。   The present invention is suitable for an electronic device in which a semiconductor device is incorporated and assembled by resin sealing.

本発明の実施の形態１の電子装置の構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the electronic device of Embodiment 1 of this invention. 図１のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図２に示す構造の主要部の詳細構造の一例を示す拡大部分断面図である。FIG. 3 is an enlarged partial sectional view showing an example of a detailed structure of a main part of the structure shown in FIG. 2. 図１に示す電子装置の組み立てにおける半導体装置実装前の構造の一例を示す拡大部分断面図である。FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a structure before mounting a semiconductor device in the assembly of the electronic device illustrated in FIG. 1. 図１に示す電子装置の組み立てにおける半導体装置の半田接合後の構造の一例を示す拡大部分断面図である。FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a structure after solder bonding of a semiconductor device in the assembly of the electronic device illustrated in FIG. 1. 本発明の実施の形態２の電子装置の構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the electronic device of Embodiment 2 of this invention. 図６のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図７のＢ部の構造の一例を示す拡大部分断面図である。It is an expanded partial sectional view which shows an example of the structure of the B section of FIG. 図６に示す電子装置に組み込まれる配線基板の第１及び第２の部分の形成範囲の一例を示す平面図である。FIG. 7 is a plan view illustrating an example of a formation range of first and second portions of a wiring board incorporated in the electronic device illustrated in FIG. 6. 図６に示す電子装置の組み立ての樹脂封止工程における樹脂の注入方向の一例を示す平面図である。It is a top view which shows an example of the injection direction of the resin in the resin sealing process of the assembly of the electronic apparatus shown in FIG. 本発明の実施の形態２の変形例の電子装置における第２の部分の構造を示す平面図である。It is a top view which shows the structure of the 2nd part in the electronic device of the modification of Embodiment 2 of this invention. 本発明の実施の形態３の電子装置の構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the electronic device of Embodiment 3 of this invention. 図１２の電子装置の主要部の構造の一例を示す拡大部分断面図である。FIG. 13 is an enlarged partial cross-sectional view illustrating an example of a structure of a main part of the electronic device in FIG. 12. 図１２の電子装置に組み込まれる配線基板の凹部の形成範囲の一例を示す平面図である。It is a top view which shows an example of the formation range of the recessed part of the wiring board integrated in the electronic device of FIG. 図１２の電子装置の組み立てにおける半導体装置実装前の構造の一例を示す拡大部分断面図である。FIG. 13 is an enlarged partial cross-sectional view illustrating an example of a structure before mounting a semiconductor device in the assembly of the electronic device of FIG. 12. 図１２の電子装置の組み立てにおける半導体装置の半田接合後の構造の一例を示す拡大部分断面図である。FIG. 13 is an enlarged partial cross-sectional view illustrating an example of a structure after solder bonding of a semiconductor device in the assembly of the electronic device of FIG. 12. 図１２の電子装置の組み立てにおける樹脂モールディング後の構造の一例を示す拡大部分断面図である。FIG. 13 is an enlarged partial cross-sectional view illustrating an example of a structure after resin molding in the assembly of the electronic device of FIG. 12. 本発明の実施の形態４の電子装置の構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the electronic device of Embodiment 4 of this invention. 図１８の電子装置の主要部の構造の一例を示す拡大部分断面図である。FIG. 19 is an enlarged partial cross-sectional view illustrating an example of a structure of a main part of the electronic device in FIG. 18. 図１８の電子装置に組み込まれる配線基板のシルク印刷の形成範囲の一例を示す平面図である。It is a top view which shows an example of the formation range of the silk printing of the wiring board integrated in the electronic device of FIG. 図１８の電子装置の組み立ての樹脂封止工程における樹脂の注入方向の一例を示す平面図である。It is a top view which shows an example of the injection direction of the resin in the resin sealing process of the assembly of the electronic device of FIG. 本発明の実施の形態５の電子装置の構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the electronic device of Embodiment 5 of this invention. 図２２の電子装置の主要部の構造の一例を示す拡大部分断面図である。FIG. 23 is an enlarged partial cross-sectional view illustrating an example of a structure of a main part of the electronic device in FIG. 22. 図２２の電子装置に組み込まれる配線基板の主面の構造の一例を示す平面図である。FIG. 23 is a plan view illustrating an example of a structure of a main surface of a wiring board incorporated in the electronic device of FIG. 22. 本発明の実施の形態６の電子装置の構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the electronic device of Embodiment 6 of this invention. 図２５の電子装置の主要部の構造の一例を示す拡大部分断面図である。FIG. 26 is an enlarged partial cross-sectional view illustrating an example of a structure of a main part of the electronic device in FIG. 25. 図２５の電子装置に組み込まれる配線基板の主面の構造の一例を示す平面図である。FIG. 26 is a plan view illustrating an example of a structure of a main surface of a wiring board incorporated in the electronic device of FIG. 25. 本発明の実施の形態７の電子装置の組み立てにおける樹脂封止方法の一例を示す部分断面図である。It is a fragmentary sectional view which shows an example of the resin sealing method in the assembly of the electronic device of Embodiment 7 of this invention. 本発明の実施の形態７の電子装置の組み立てにおける変形例の樹脂封止方法を示す部分断面図である。It is a fragmentary sectional view which shows the resin sealing method of the modification in the assembly of the electronic device of Embodiment 7 of this invention. 本発明における変形例の電子装置の構造を封止体を透過して示す平面図である。It is a top view which permeate | transmits a sealing body and shows the structure of the electronic device of the modification in this invention. 図３０のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG.

符号の説明Explanation of symbols

１ 半導体チップ
２ ＴＳＯＰ（半導体装置）
２ａ タブ
２ｂ インナリード（リード）
２ｃ アウタリード（リード）
２ｄ ワイヤ
２ｅ 第１封止体
２ｆ 裏面
３ メモリモジュール（電子装置）
４ シルク印刷部
４ａ 広域シルク印刷部
５ 半田
６ 第２封止体
７ 配線基板
７ａ 主面
７ｂ 裏面
７ｃ 電極
７ｄ 絶縁膜
７ｅ 第１の部分
７ｆ 銅パターン（配線部）
７ｇ 基材
７ｈ 第２の部分
７ｉ ザグリ（凹部）
７ｊ 第３の部分
７ｋ 貫通孔
７ｍ 外部端子
８ ＱＦＰ（半導体装置）
９ ＳＩＰ（電子装置）
１０ アンダーフィル
１１ 樹脂成形金型
１２ プランジャ
１３ モールドレジン（封止用樹脂）
１４ ディスペンサノズル
１５ メモリモジュール（電子装置） 1 Semiconductor chip 2 TSOP (semiconductor device)
2a Tab 2b Inner lead (lead)
2c Outer lead (lead)
2d wire 2e first sealing body 2f back surface 3 memory module (electronic device)
4 Silk printing part 4a Wide area silk printing part 5 Solder 6 Second sealing body 7 Wiring board 7a Main surface 7b Back surface 7c Electrode 7d Insulating film 7e First part 7f Copper pattern (wiring part)
7g Base material 7h Second part 7i Counterbore (recess)
7j Third part 7k Through hole 7m External terminal 8 QFP (semiconductor device)
9 SIP (electronic equipment)
10 Underfill 11 Resin Mold 12 Plunger 13 Mold Resin (Resin for Sealing)
14 Dispenser nozzle 15 Memory module (electronic device)

Claims (5)

半導体チップを樹脂封止する第１封止体を有し、前記半導体チップと電気的に接続するとともに前記第１封止体から露出するリードを備えた半導体装置と、
基材、絶縁膜、電極及び配線部を備え、主面と前記主面に対向する裏面を有し、前記リードが前記電極に半田接続されて前記主面上に前記半導体装置を搭載する配線基板と、
前記半導体装置を樹脂封止する第２封止体と、
前記配線基板の裏面に設けられた複数の外部端子とを有し、
前記配線基板の主面における前記第１封止体と対向する領域に、前記基材が露出した第
１の部分と、前記基材から前記第１封止体に向かって突出する第２の部分とが形成され、
前記第１封止体と前記配線基板との間に前記第２封止体の一部が形成されていることを特徴とする電子装置。 A semiconductor device having a first sealing body for resin-sealing a semiconductor chip, and a lead electrically connected to the semiconductor chip and exposed from the first sealing body;
A wiring board comprising a base material, an insulating film, an electrode, and a wiring portion, having a main surface and a back surface facing the main surface, wherein the lead is soldered to the electrode and the semiconductor device is mounted on the main surface When,
A second sealing body for resin-sealing the semiconductor device;
A plurality of external terminals provided on the back surface of the wiring board;
A first portion where the base material is exposed in a region facing the first sealing body on the main surface of the wiring board, and a second portion projecting from the base material toward the first sealing body And formed,
A part of the second sealing body is formed between the first sealing body and the wiring board. 半導体チップを樹脂封止する第１封止体を有し、前記半導体チップと電気的に接続するとともに前記第１封止体から露出するリードを備えた半導体装置と、
基材、絶縁膜、電極及び配線部を備え、主面と前記主面に対向する裏面を有し、前記リードが前記電極に半田接続されて前記主面上に前記半導体装置を搭載する配線基板と、
前記半導体装置を樹脂封止する第２封止体と、
前記配線基板の裏面に設けられた複数の外部端子とを有し、
前記配線基板の主面における前記第１封止体と対向する領域に、前記基材が露出した状態で凹部が形成され、
前記第１封止体と前記配線基板の凹部との間に前記第２封止体の一部が形成されていることを特徴とする電子装置。 A semiconductor device having a first sealing body for resin-sealing a semiconductor chip, and a lead electrically connected to the semiconductor chip and exposed from the first sealing body;
A wiring board comprising a base material, an insulating film, an electrode, and a wiring portion, having a main surface and a back surface facing the main surface, wherein the lead is soldered to the electrode and the semiconductor device is mounted on the main surface When,
A second sealing body for resin-sealing the semiconductor device;
A plurality of external terminals provided on the back surface of the wiring board;
In a region facing the first sealing body on the main surface of the wiring board, a recess is formed in a state where the base material is exposed,
A part of said 2nd sealing body is formed between the said 1st sealing body and the recessed part of the said wiring board, The electronic device characterized by the above-mentioned. 半導体チップを樹脂封止する第１封止体を有し、前記半導体チップと電気的に接続するとともに前記第１封止体から露出するリードを備えた半導体装置と、
基材、絶縁膜、電極及び配線部を備え、主面と前記主面に対向する裏面を有し、前記リードが前記電極に半田接続されて前記主面上に前記半導体装置を搭載する配線基板と、
前記半導体装置を樹脂封止する第２封止体と、
前記配線基板の裏面に設けられた複数の外部端子とを有し、
前記配線基板の主面における前記第１封止体と対向する領域に、前記第１封止体の裏面全体に亘って対向して前記第１封止体に向かって突出する第３の部分が形成されていることを特徴とする電子装置。 A semiconductor device having a first sealing body for resin-sealing a semiconductor chip, and a lead electrically connected to the semiconductor chip and exposed from the first sealing body;
A wiring board comprising a base material, an insulating film, an electrode, and a wiring portion, having a main surface and a back surface facing the main surface, wherein the lead is soldered to the electrode and the semiconductor device is mounted on the main surface When,
A second sealing body for resin-sealing the semiconductor device;
A plurality of external terminals provided on the back surface of the wiring board;
In a region facing the first sealing body on the main surface of the wiring board, there is a third portion that faces the entire back surface of the first sealing body and protrudes toward the first sealing body. An electronic device is formed. （ａ）半導体チップを樹脂封止する第１封止体を有し、前記半導体チップと電気的に接続するとともに前記第１封止体から露出するリードを備えた半導体装置を準備する工程と、
（ｂ）基材、絶縁膜、電極及び配線部を備え、主面と前記主面に対向する裏面を有し、前記基材が露出した第１の部分と前記基材から突出した細長い第２の部分とを有する配線基板を準備する工程と、
（ｃ）前記配線基板における前記第１の部分と前記第２の部分が前記第１封止体と前記配線基板の間に配置されるように前記配線基板上に前記半導体装置を配置した後、前記リードを前記配線基板の電極に半田接続して前記配線基板の主面上に前記半導体装置を搭載する工程と、
（ｄ）前記細長い第２の部分の延在方向に沿って封止用樹脂を前記第１封止体と前記配線基板の間に注入するとともに、前記封止用樹脂で前記半導体装置を覆って第２封止体を形成する工程とを有することを特徴とする電子装置の製造方法。 (A) preparing a semiconductor device having a first sealing body for resin-sealing a semiconductor chip, including a lead electrically connected to the semiconductor chip and exposed from the first sealing body;
(B) A base material, an insulating film, an electrode, and a wiring portion, and having a main surface and a back surface facing the main surface, a first portion where the base material is exposed, and an elongated second protruding from the base material. A step of preparing a wiring board having a portion of
(C) after disposing the semiconductor device on the wiring substrate such that the first portion and the second portion of the wiring substrate are disposed between the first sealing body and the wiring substrate; Mounting the semiconductor device on the main surface of the wiring board by solder-connecting the lead to the electrode of the wiring board;
(D) Injecting a sealing resin between the first sealing body and the wiring board along the extending direction of the elongated second portion, and covering the semiconductor device with the sealing resin. And a step of forming a second sealing body. （ａ）半導体チップを樹脂封止する第１封止体を有し、前記半導体チップと電気的に接続するとともに前記第１封止体から露出するリードを備えた半導体装置を準備する工程と、
（ｂ）主面と前記主面に対向する裏面を有し、貫通孔が形成された配線基板を準備する工程と、
（ｃ）前記第１封止体の裏面と前記貫通孔とが対向するように前記配線基板上に前記半導体装置を配置した後、前記リードを前記配線基板の電極に半田接続して前記配線基板の主面上に前記半導体装置を搭載する工程と、
（ｄ）前記配線基板の裏面側から封止用樹脂を前記貫通孔を介して前記第１封止体と前記配線基板の間に注入するとともに、前記封止用樹脂で前記半導体装置を覆って第２封止体を形成する工程とを有することを特徴とする電子装置の製造方法。 (A) preparing a semiconductor device having a first sealing body for resin-sealing a semiconductor chip, including a lead electrically connected to the semiconductor chip and exposed from the first sealing body;
(B) preparing a wiring board having a main surface and a back surface facing the main surface and having a through hole;
(C) After arranging the semiconductor device on the wiring board so that the back surface of the first sealing body and the through hole face each other, the leads are soldered to the electrodes of the wiring board to connect the wiring board. Mounting the semiconductor device on the main surface of
(D) Injecting sealing resin between the first sealing body and the wiring board through the through hole from the back side of the wiring board, and covering the semiconductor device with the sealing resin. And a step of forming a second sealing body.
JP2007144492A 2007-05-31 2007-05-31 Electronic apparatus, and manufacturing method thereof Pending JP2008300588A (en)

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