JP2008294193A - Method of manufacturing substrate for flexible wiring board - Google Patents

Method of manufacturing substrate for flexible wiring board Download PDF

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Publication number
JP2008294193A
JP2008294193A JP2007137655A JP2007137655A JP2008294193A JP 2008294193 A JP2008294193 A JP 2008294193A JP 2007137655 A JP2007137655 A JP 2007137655A JP 2007137655 A JP2007137655 A JP 2007137655A JP 2008294193 A JP2008294193 A JP 2008294193A
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wiring board
copper
flexible wiring
cathode
layer
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JP2007137655A
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Japanese (ja)
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Koichiro Maki
槇孝一郎
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Sumitomo Metal Mining Co Ltd
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Sumitomo Metal Mining Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a substrate for flexible wiring board which has no pinhole. <P>SOLUTION: When a base having a seed layer made of chromium, nickel, copper, or alloy thereof on a top surface of an insulating film by a dry plating method, namely, a thin underlayer comprising the seed layer and a copper layer provided thereupon by a dry plating method is used to manufacture the substrate for flexible wiring board by providing a copper layer on the top surface of the underlayer by an electrolytic copper plating method using the underlayer of the base as a cathode, the cathode is provided on the back side of the insulating film of the base (on the opposite side from an anode) and on an external wall surface of an electrolytic cell, and a voltage applied to the cathode is set higher than a voltage applied to the underlayer of the base. In this invention, it is effective that the underlayer is grounded to be held at 0 V. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、電気、電子、通信などの分野で用いられるフレキシブル配線板用の基材の製造方法に関し、より具体的には、絶縁性フィルムとその表面に設けられたシード層と、その上に設けられた導電層から構成されるフレキシブル配線板用基板において、ピンホールを有さないシード層を有するものの提供に関する。   The present invention relates to a method for producing a substrate for a flexible wiring board used in fields such as electricity, electronics, and communications, and more specifically, an insulating film and a seed layer provided on the surface thereof, The present invention relates to provision of a flexible wiring board substrate having a seed layer that does not have a pinhole, in a substrate for a flexible wiring board that includes a conductive layer.

近年、各種電気電子部品の高集積化や小型化が要望されてきている。これを受け、特に省スペース性が要求されるノート型パーソナルコンピューター、携帯電話などの電気電子機器などには、屈曲性を有する絶縁性フィルム上に金属配線を施したフレキシブル配線板が多用されてきている。   In recent years, high integration and miniaturization of various electric and electronic parts have been demanded. In response, flexible wiring boards in which metal wiring is provided on a flexible insulating film have been widely used in electrical and electronic devices such as notebook personal computers and mobile phones that require space saving. Yes.

こうしたフレキシブル配線板は、一般的に、カプトンなどのポリイミドフィルム上に直接導電層が設けられた、所謂2層基板を用い、セミアディティブ法で製造される。この2層基板は、ポリイミドフィルム上に真空蒸着法やスパッタリング法によりシード層を形成し、このシード層の上に、要すれば銅スパッタ膜を設け、その上に電解銅めっき法により導電層を設けたものであり、シード層と導電層とを合わせて下地層として取り扱うことが多い。   Such a flexible wiring board is generally manufactured by a semi-additive method using a so-called two-layer substrate in which a conductive layer is directly provided on a polyimide film such as Kapton. In this two-layer substrate, a seed layer is formed on a polyimide film by a vacuum deposition method or a sputtering method, and a copper sputtered film is provided on the seed layer if necessary, and a conductive layer is formed thereon by an electrolytic copper plating method. In many cases, the seed layer and the conductive layer are combined and handled as a base layer.

セミアディティブ法では、まず、2層基板の前記下地層表面に、コーターやスクリーン印刷によりフォトレジスト層を設け、所望の回路パターンを有するフォトマスクを用いて露光し、現像してめっき用マスクを得る。   In the semi-additive method, first, a photoresist layer is provided on the surface of the base layer of a two-layer substrate by a coater or screen printing, exposed using a photomask having a desired circuit pattern, and developed to obtain a plating mask. .

次に、マスクの開口部に露出する下地層の上に電気銅めっき法により銅を析出させて銅層を形成する。   Next, copper is deposited by electrolytic copper plating on the base layer exposed in the opening of the mask to form a copper layer.

次に、めっき用マスクを除去し、これに伴い露出した下地層を除去し、回路パターンを得る。   Next, the plating mask is removed, and the underlying layer exposed thereby is removed to obtain a circuit pattern.

ところで、下地層は、一般にクロム、ニッケルまたはこれらの合金をターゲットとして蒸着法やスパッタリング法によりで形成されるシード層のみで構成され、あるいはこのシード層の上に同様な方法で設けられた銅層との組み合わせで構成される。シード層は銅層と溶解特性が異なるため、シード層のエッチング除去に際しては銅が浸食されにくいエッチング液を選択できる。とはいえ、シード層が厚いと、シード層をエッチング除去する間に銅回路部自体も犯され、良好な回路パターンを得ることができない。このため、シード層の厚さは可能な限り薄いことが望まれる。また、シード層の上に設けられる銅スパッタ層に関しても、あまり厚い銅スパッタ層を得ようとすると、生産コストが大きくなり、好ましくない。こうした結果、下地層全体として、後工程での電解銅メッキに支障が出ない程度に可能な限り薄いことが求められている。こうした薄い下地層では、その製法上もからピンホールを十分無くすことはできていない。   By the way, the base layer is generally composed of only a seed layer formed by vapor deposition or sputtering using chromium, nickel or an alloy thereof as a target, or a copper layer provided on the seed layer by a similar method. It is composed of the combination. Since the seed layer has different dissolution characteristics from the copper layer, an etchant that is less susceptible to copper erosion can be selected when the seed layer is etched away. However, if the seed layer is thick, the copper circuit portion itself is also violated while the seed layer is etched away, and a good circuit pattern cannot be obtained. For this reason, the thickness of the seed layer is desired to be as thin as possible. Further, regarding the copper sputter layer provided on the seed layer, it is not preferable to obtain a too thick copper sputter layer because the production cost increases. As a result, the entire underlayer is required to be as thin as possible so as not to hinder electrolytic copper plating in the subsequent process. Such a thin underlayer cannot sufficiently eliminate pinholes because of its manufacturing method.

こうしたピンホールを有する下地層の上に電解銅メッキして得たフレキシブル配線板用基板を用いて微細な回路パターンを有するフレキシブル配線板をセミアディティブ法で作成すると、ピンホール部には銅が析出しないため、配線の密着強度が十分なものとならないという現象が起きる。   When a flexible wiring board having a fine circuit pattern is prepared by a semi-additive method using a substrate for flexible wiring board obtained by electrolytic copper plating on an underlayer having such pinholes, copper is deposited in the pinhole portion. Therefore, a phenomenon that the adhesion strength of the wiring is not sufficient occurs.

こうしたピンホールを有さない下地層を得る方法として、クロム、ニッケルまたはこれらの合金で構成シード層の厚みを1〜1000nmとし、シード層の上に設ける銅スパッタ膜の厚みを50〜3000nmとすることが開示されている(特許文献1参照)。
特開2007−073935号公報
As a method for obtaining such a base layer having no pinhole, the thickness of the seed layer made of chromium, nickel or an alloy thereof is set to 1 to 1000 nm, and the thickness of the copper sputtered film provided on the seed layer is set to 50 to 3000 nm. (See Patent Document 1).
JP 2007-073935 A

特許文献1に開示された方法においても、近年要求される高密度回路パターンを有するフレキシブル配線板を得るための薄い下地層の基板を得ようとすれば、下地層よりピンホールを無くすことはできない。   Even in the method disclosed in Patent Document 1, pinholes cannot be eliminated from the base layer if an attempt is made to obtain a thin base layer substrate for obtaining a flexible wiring board having a high-density circuit pattern required in recent years. .

本発明は、ピンホールを有さないフレキシブル配線板用基板の製造方法の提供を目的とする。   An object of this invention is to provide the manufacturing method of the board | substrate for flexible wiring boards which does not have a pinhole.

前記課題を解決すべく本発明者は種々検討した結果、クロム、ニッケルまたは銅やこれらの合金で構成したシード層の上に、あるいはこのシード層の上に銅スパッタ膜が設けられた基材の上に所望厚の厚さの銅層を電解銅めっき法により得て、フレキシブル配線板用基板を得る方法において、被めっき物である基材の背面に新たな電極を設けることにより下地層のピンホール内に銅を析出させることを見いだし、本発明に至った。   As a result of various studies by the present inventors to solve the above-mentioned problems, a substrate having a copper sputtered film formed on a seed layer made of chromium, nickel, copper, or an alloy thereof, or on the seed layer is disclosed. In a method of obtaining a flexible wiring board substrate by obtaining a copper layer having a desired thickness on the substrate by electrolytic copper plating, a pin for the underlayer is provided by providing a new electrode on the back surface of the substrate to be plated. It has been found that copper is deposited in the hole, and the present invention has been achieved.

すなわち、前記課題を解決する本発明は、絶縁性フィルムの表面に乾式めっき法により薄い下地層が設けられた基材を用い、この基材の下地層を陰極として電解銅めっき法により下地層表面に銅層を設けてフレキシブル配線板用基板を製造するに際して、前記基材の絶縁性フィルムの背面側(陽極と反対側)で電解槽外壁面に陰極を設け、この陰極に掛ける電圧を前記基材の下地層に掛ける電圧より高い電圧とするものである。   That is, the present invention that solves the above problems uses a base material in which a thin base layer is provided on the surface of an insulating film by a dry plating method, and the base layer surface is formed by an electrolytic copper plating method using the base layer of the base material as a cathode. When a flexible wiring board substrate is manufactured by providing a copper layer on the substrate, a cathode is provided on the outer wall surface of the electrolytic cell on the back side (opposite side of the anode) of the insulating film of the base material, and the voltage applied to the cathode is applied to the base. The voltage is higher than the voltage applied to the base layer of the material.

また、本発明において下地層をアースし、0ボルトとすることも有効である。   In the present invention, it is also effective to ground the base layer to 0 volts.

本発明によれば、プリント配線板用基板の下地層のピンホール内にも銅を析出させることができる。従って、本発明のプリント配線板用基板を用いて高密度で配線幅の狭い回路パターンを有するプリント配線板を作成しても、回路パターンの密着強度は十分なものとなる。   According to the present invention, copper can be deposited also in the pinhole of the base layer of the printed wiring board substrate. Therefore, even when a printed wiring board having a circuit pattern with a high density and a narrow wiring width is produced using the printed wiring board substrate of the present invention, the adhesion strength of the circuit pattern is sufficient.

本発明において、基材を構成する絶縁フィルムの背面側で電解槽外壁面に陰極を新たに設けるのは、この陰極の形成する電磁場により基材下地層のピンホール内部まで銅イオンを引きつけ、銅イオンを周囲の下地層と接触させて金属としてピンホール内に析出させようとするものである。   In the present invention, a cathode is newly provided on the outer wall surface of the electrolytic cell on the back side of the insulating film constituting the base material by attracting copper ions to the inside of the pinhole of the base material underlayer by the electromagnetic field formed by the cathode. The ions are brought into contact with the surrounding base layer to precipitate as metal in the pinhole.

従って、この陰極に印可する電圧は、前記目的より、ピンホール部での電場の強さが、下地層表面の電場の強さより強くすることが必要であるため、絶縁フィルム表面の下地層に印可する電圧より高くする。   Therefore, the voltage applied to the cathode must be applied to the underlayer on the surface of the insulating film because the electric field strength at the pinhole portion needs to be stronger than the electric field strength on the surface of the underlayer. Higher than the voltage to be applied.

また、印可する電圧の強さは、当然ではあるが、絶縁性フィルムと前記陰極との間隔により異なることになる。また、この間隔は電解槽そのものの構造にも影響を受ける。   The strength of the voltage to be applied is naturally different depending on the distance between the insulating film and the cathode. This interval is also affected by the structure of the electrolytic cell itself.

従って、実施に際しては、予め最適条件を求めておくことが好ましい。   Therefore, it is preferable to obtain optimum conditions in advance for implementation.

なお、本発明において絶縁性フィルムとしては、ポリイミドフィルム、ポリエチレンフィルム、ポリプロピレンフィルム等を用いることができる。   In the present invention, a polyimide film, a polyethylene film, a polypropylene film, or the like can be used as the insulating film.

以下、実施例を用いて本発明を説明する。   Hereinafter, the present invention will be described using examples.

電解槽の中に、電極BとCとを対向するように配置し、電極B側の電解槽外壁面に電極Aを配置した。電解槽内に硫酸銅めっき液を入れ、電極Bを陰極とし、電極Cを陽極として通常のめっき電圧(1〜2V)をBとCとの間に印加して電極Bに銅がめっきされることを確認した。   In the electrolytic cell, the electrodes B and C were disposed so as to face each other, and the electrode A was disposed on the outer surface of the electrolytic cell on the electrode B side. A copper sulfate plating solution is placed in the electrolytic bath, and the electrode B is used as a cathode, the electrode C is used as an anode, and a normal plating voltage (1 to 2 V) is applied between B and C so that copper is plated on the electrode B. It was confirmed.

次に、電極Bを、厚さ35μmのポリイミドフィルムにシード層としてニッケル・クロム合金層を設け、その上に、厚さ10μmで直径20μm程度のピンホールを有する銅膜を設けたものに変更し、さらに電極Aにはマイナス100Vの電圧を印可しつつ前記と同様に電解銅めっきを行った。なお、この際、電極Cはアース(0V)した。   Next, the electrode B was changed to a 35 μm thick polyimide film provided with a nickel-chromium alloy layer as a seed layer and a copper film having a pinhole of 10 μm thickness and a diameter of about 20 μm. Further, electrolytic copper plating was performed in the same manner as described above while applying a voltage of minus 100 V to the electrode A. At this time, the electrode C was grounded (0 V).

得られた電極を観察したところ、ピンホールの周囲にめっき成長の著しい傾向が見られ、ピンホールの直径が10ミクロンと小さくなっていることがわかった。   When the obtained electrode was observed, it was found that a remarkable tendency of plating growth was observed around the pinhole, and the diameter of the pinhole was as small as 10 microns.

この現象を解析するために、シミュレーションを行ったところ、ピンホールからは図1に示すように高い電界がめっき液内部へ漏洩していることがわかった。この高電界によって電解液中の金属イオンが集まり、イオン密度を増加させたものと推測できる。   A simulation was performed to analyze this phenomenon, and it was found that a high electric field leaked from the pinhole into the plating solution as shown in FIG. It can be presumed that the metal ions in the electrolytic solution are gathered by this high electric field and the ion density is increased.

実施例で行ったシミュレーション結果を示した図である。It is the figure which showed the simulation result performed in the Example.

Claims (2)

絶縁性フィルムの表面に乾式めっき法により薄い下地層が設けられた基材を用い、この基材の下地層を陰極として電解銅めっき法により下地層表面に銅層を設けてフレキシブル配線板用基板を製造するに際して、前記基材の絶縁性フィルムの背面側(陽極と反対側)で電解槽外壁面に陰極を設け、この陰極に掛ける電圧を前記基材の下地層に掛ける電圧より高い電圧とすることを特徴とするフレキシブル配線板用基板の製造方法。 A substrate for a flexible wiring board using a base material on which a thin base layer is provided by a dry plating method on the surface of an insulating film, and using the base layer of this base material as a cathode, a copper layer is provided on the base layer surface by an electrolytic copper plating method When a cathode is provided on the outer wall surface of the electrolytic cell on the back side (opposite side of the anode) of the insulating film of the base material, the voltage applied to the cathode is higher than the voltage applied to the base layer of the base material. A method for producing a flexible wiring board substrate, comprising: 前記陰極に掛ける電圧を0ボルトとすることを特徴とするフレキシブル配線板用基板の製造方法。   A method of manufacturing a substrate for a flexible wiring board, wherein a voltage applied to the cathode is 0 volts.
JP2007137655A 2007-05-24 2007-05-24 Method of manufacturing substrate for flexible wiring board Pending JP2008294193A (en)

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