JP2008294156A - Method of manufacturing substrate for semiconductor film deposition - Google Patents

Method of manufacturing substrate for semiconductor film deposition Download PDF

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JP2008294156A
JP2008294156A JP2007137064A JP2007137064A JP2008294156A JP 2008294156 A JP2008294156 A JP 2008294156A JP 2007137064 A JP2007137064 A JP 2007137064A JP 2007137064 A JP2007137064 A JP 2007137064A JP 2008294156 A JP2008294156 A JP 2008294156A
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substrate
etching
mask
forming
semiconductor film
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Masahiro Koto
雅弘 湖東
Hiroaki Okagawa
広明 岡川
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Mitsubishi Chemical Corp
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Mitsubishi Chemical Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method which can improve true manufacturing efficiency of a substrate for semiconductor film deposition with formed with concavo-convex portions installed on the surface. <P>SOLUTION: By conducting a process of partially forming a mask on the surface of a substrate and a process of forming concave portions by etch-removing a portion of the surface of the substrate which is not covered with the mask by a dry etching method in this order, concave-convex portions are formed on the surface of the substrate. In the process of forming the concave portions, etching is conducted, in such a manner that deposition is suppressed by making the etch rate of the substrate from half to twice the etching rate of the mask in a final stage of etching and then etching is finished. Since the occurrence of defective substrates which are not suitable for semiconductor film deposition can be suppressed, true manufacturing efficiency of substrates can be improved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体成膜用基板の製造方法に関し、とりわけ、表面に凹凸部を設けた半導体成膜用基板の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor film forming substrate, and more particularly, to a method for manufacturing a semiconductor film forming substrate having an uneven portion on the surface.

サファイア、炭化ケイ素、スピネル等の基板上に、AlGaInNなどの3−5族化合物からなる半導体膜を成長させる場合、基板と半導体膜の格子定数差や熱膨張率差が原因となって、半導体膜の結晶性が著しく低くなるという問題があった。この問題に対し、基板表面に凹凸部を設け、これにより結晶のラテラル成長を発生させて、転位密度を低減した高品質な半導体膜を得ることが行われている(特許文献1)。 When a semiconductor film made of a Group 3-5 compound such as AlGaInN is grown on a substrate such as sapphire, silicon carbide, or spinel, the semiconductor film is caused by a difference in lattice constant or thermal expansion coefficient between the substrate and the semiconductor film. There was a problem that the crystallinity of the remarkably decreased. In order to solve this problem, a high-quality semiconductor film with a reduced dislocation density is obtained by providing uneven portions on the substrate surface, thereby generating lateral growth of crystals (Patent Document 1).

また、サファイア等の基板上にAlGaInNなどの3−5族化合物からなる半導体膜を成膜することにより構成されるLEDなどの発光素子において、基板表面に凹凸部を設けると、基板と半導体膜との界面に凹凸状の屈折率界面が形成されることにより、発光素子の光取出効率が改善される効果が得られることが知られている(特許文献2、特許文献3、特許文献4)。この場合、凹凸部における凹部の表面から半導体結晶が成長を開始するように成膜すると、凹部内が半導体結晶で充填された構造が形成されるために、光取出効率の改善効果がより高くなる。 In addition, in a light-emitting element such as an LED formed by forming a semiconductor film made of a Group 3-5 compound such as AlGaInN on a substrate such as sapphire, a substrate and a semiconductor film It is known that the effect of improving the light extraction efficiency of the light emitting element can be obtained by forming a concavo-convex refractive index interface at the interface (Patent Document 2, Patent Document 3, and Patent Document 4). In this case, when the film is formed so that the semiconductor crystal starts growing from the surface of the concave portion in the concave and convex portion, a structure in which the concave portion is filled with the semiconductor crystal is formed, so that the effect of improving the light extraction efficiency becomes higher. .

基板表面に凹凸部を形成する方法としては、基板表面にマスクを部分的に形成する工程と、RIE(Reactive Ion Etching:反応性イオンエッチング)などのドライエッチング法を用いて該基板表面の該マスクに覆われていない部分をエッチング除去して凹部を形成する工程とを、この順に行う方法が一般的である。
特開2000−331947号公報 特開2002−280611号公報 特開2003−318441号公報 特開2005−101566号公報
As a method for forming the concavo-convex portion on the substrate surface, a step of partially forming a mask on the substrate surface and a dry etching method such as RIE (Reactive Ion Etching) are used to form the mask on the substrate surface. In general, the step of forming the recesses by etching away the portions not covered by the coating is performed in this order.
JP 2000-331947 A JP 2002-280611 A JP 2003-318441 A JP 2005-101656 A

ドライエッチング法を用いて基板表面に凹部を形成するとき、[(基板のエッチング速度)/(マスクのエッチング速度)]である選択比を高くする程、凹部の形成を効率よく行うことができる。しかしながら、本発明者等が研究した結果、この選択比を高くした条件で凹部を形成した基板上に半導体膜を成長させると、凹部の表面において結晶の異常成長が発生し易いことが判明した。つまり、この選択比を高くすると凹部が速く形成できるので、製造効率が高くなるように見えるのであるが、実際には、半導体の成膜に適さない不良基板が多く発生するので、基板の真の製造効率は低下するのである。 When the concave portion is formed on the substrate surface by using the dry etching method, the concave portion can be formed more efficiently as the selection ratio [(substrate etching speed) / (mask etching speed)] is increased. However, as a result of studies by the present inventors, it has been found that when a semiconductor film is grown on a substrate in which a recess is formed under the condition where the selectivity is increased, abnormal crystal growth is likely to occur on the surface of the recess. In other words, if this selection ratio is increased, the recesses can be formed quickly, so that it seems that the manufacturing efficiency is increased, but in reality, many defective substrates are not suitable for film formation of semiconductors. Manufacturing efficiency is reduced.

本発明は上記問題を解決するためになされたものであり、その主な目的は、表面に凹凸部を設けた半導体成膜用基板の、真の製造効率を改善するための製造方法を提供することである。 The present invention has been made to solve the above-mentioned problems, and its main object is to provide a manufacturing method for improving the true manufacturing efficiency of a semiconductor film forming substrate having an uneven portion on the surface. That is.

上記目的を達成するための好適な手段として、次の発明を開示する。
(1)基板の表面に部分的にマスクを形成する工程と、ドライエッチング法を用いて前記基板の表面の前記マスクに覆われていない部分をエッチング除去して凹部を形成する工程とを、この順に行うことにより、基板の表面に凹凸部を設ける、半導体成膜用基板の製造方法であって、前記凹部を形成する工程においては、少なくとも最後に基板のエッチング速度をマスクのエッチング速度の半分〜2倍とすることによりデポジションを抑制しながらエッチングを行ったところでエッチングを終了することを特徴とする、半導体成膜用基板の製造方法。
(2)前記凹部を形成する工程においては、最初から最後まで基板のエッチング速度をマスクのエッチング速度の半分〜2倍とすることによりデポジションを抑制しながらエッチングを行う、前記(1)に記載の製造方法。
(3)前記凹部を形成する工程においては、少なくとも最後に基板のエッチング速度とマスクのエッチング速度とを略同じにしてエッチングを行ったところでエッチングを終了する、前記(1)に記載の製造方法。
The following invention is disclosed as a suitable means for achieving the above object.
(1) A step of partially forming a mask on the surface of the substrate, and a step of etching and removing a portion of the surface of the substrate that is not covered with the mask by using a dry etching method. A method for manufacturing a substrate for semiconductor film formation, in which an uneven portion is provided on the surface of the substrate by performing in order, and in the step of forming the recess, at least the etching rate of the substrate is at least half the etching rate of the mask. A method of manufacturing a substrate for semiconductor film formation, characterized in that the etching is terminated when etching is performed while suppressing deposition by setting it to double.
(2) In the step of forming the recess, etching is performed while suppressing deposition by setting the etching rate of the substrate to be half to twice the etching rate of the mask from the beginning to the end. Manufacturing method.
(3) The manufacturing method according to (1), wherein in the step of forming the concave portion, the etching is terminated at least when the etching rate of the substrate and the etching rate of the mask are finally made substantially the same.

本発明に係る半導体成膜用基板の製造方法によれば、凹凸部を設けた表面上に半導体膜を成長させたときに、凹部の表面における結晶の異常成長が発生しない半導体成膜用基板を得ることができる。凹部の形成の効率が低くなって、基板の製造効率が低下するように見えるが、半導体の成膜に適さない不良基板の発生が抑えられるので、基板の真の製造効率は改善される。 According to the method for manufacturing a semiconductor film forming substrate of the present invention, there is provided a semiconductor film forming substrate in which abnormal growth of crystals on the surface of the concave portion does not occur when the semiconductor film is grown on the surface provided with the concave and convex portions. Obtainable. Although the efficiency of forming the recesses decreases and the manufacturing efficiency of the substrate seems to decrease, the generation of defective substrates that are not suitable for semiconductor film formation can be suppressed, and the true manufacturing efficiency of the substrate is improved.

次に、本発明の実施形態に係る半導体成膜用基板の製造方法を、図1を用いて説明する。 Next, a method for manufacturing a semiconductor film forming substrate according to an embodiment of the present invention will be described with reference to FIG.

この製造方法では、まず、図1(a)に示すように、基板1の表面にマスク2を部分的に形成する。基板1は、例えば、C面サファイア基板である。マスク2は、例えば、スピンコーターを用いて成膜し、フォトリソグラフィ技法によりパターニングした、フォトレジスト膜である。 In this manufacturing method, first, a mask 2 is partially formed on the surface of the substrate 1 as shown in FIG. The substrate 1 is, for example, a C-plane sapphire substrate. The mask 2 is, for example, a photoresist film formed using a spin coater and patterned by a photolithography technique.

次に、この基板1を一般的なRIE装置のエッチング容器内に装着し、図1(b)に示すように、基板1の表面の、マスク2に覆われていない部分をエッチング除去して、凹部11を形成する。凹部11の深さは、例えば、0.1μm〜3μmである。図1(b)に示す断面図は、凹部11の形成が完了した状態を示しているが、凹部11の形成前後におけるマスク2の膜厚の変化Δtと、凹部11の深さDとが略同じとなっている。このようにするには、例えば、エッチング工程の最初から最後まで、基板1のエッチング速度Rの、マスク2のエッチング速度Rに対する比である選択比(R/R)が約1となる条件の下で、エッチング加工を行う。選択比は、アンテナパワー、バイアス電圧、エッチング容器内のガス雰囲気などによって調整が可能である。エッチングガスとしては、Cl、SiCl、BCl、HBr、SF、CHF、C、CF、Arなどを用いることができる。 Next, the substrate 1 is mounted in an etching container of a general RIE apparatus, and the portion of the surface of the substrate 1 not covered with the mask 2 is removed by etching as shown in FIG. A recess 11 is formed. The depth of the recess 11 is, for example, 0.1 μm to 3 μm. The cross-sectional view shown in FIG. 1B shows a state in which the formation of the recess 11 is completed, but the change Δt in the thickness of the mask 2 before and after the formation of the recess 11 and the depth D of the recess 11 are approximately. It is the same. To do this, for example, the first etching step until the last, of the substrate 1 of the etching rate R 1, selection ratio, which is the ratio of the etching rate R 2 of the mask 2 (R 1 / R 2) is about 1 Etching is performed under the following conditions. The selection ratio can be adjusted by the antenna power, the bias voltage, the gas atmosphere in the etching container, and the like. As an etching gas, Cl 2 , SiCl 4 , BCl 3 , HBr, SF 6 , CHF 3 , C 4 F 8 , CF 4 , Ar, or the like can be used.

凹部11の形成後、図1(c)に示すようにマスク2を除去することにより、凹凸部を備えた半導体成膜用基板が完成する。マスク2がフォトレジスト膜の場合は、市販のレジストリムーバを用いて除去することができる。 After the formation of the recess 11, the mask 2 is removed as shown in FIG. 1C to complete a semiconductor film forming substrate having an uneven portion. When the mask 2 is a photoresist film, it can be removed using a commercially available registry mover.

凹凸部を設けた半導体成膜用基板の製造において、ドライエッチング法を用いて凹部を形成するときの[(基板のエッチング速度)/(マスクのエッチング速度)]である選択比を高くすると、得られた基板上に半導体を成膜するときに凹部の表面において結晶の異常成長が生じ易くなり、この選択比を低くすることによりこの異常成長が防止できる理由について、本発明者等は次のように考えている:
(イ)ドライエッチング(とりわけ、RIE)には化学エッチングの側面と物理エッチングの側面がある。ドライエッチングにおける選択比が高い条件とは、異なる材料からなる基板とマスクとの間でエッチング速度が大きく異なる条件である。材料の相違がエッチング速度に強く影響することから、このような条件でのエッチングは、化学エッチングの側面が強いといえる。逆に、選択比が1に近い条件、すなわち、異なる材料間でエッチング速度があまり異ならない条件でのエッチングは、物理エッチングの側面が強いといえる。
(ロ)ドライエッチングの過程では、プラズマの形で供給されるエネルギーによってエッチングガスおよび/または被加工物(基板およびマスク)の一部が化学反応を起こし、該反応の生成物が基板上に堆積することがある。この現象をデポジションという。デポジションにより基板表面に堆積する物質を構成する材料は、通常、基板の材料と同じではない。よって、化学エッチングの側面が強い条件下では、基板と堆積物質との間でエッチング速度に差が生じる。選択比の大きな条件(基板のエッチング速度が大きくなるように設定されている)では、たいてい、基板のエッチング速度が堆積物のエッチング速度よりもかなり大きくなるために、この堆積物がエッチングマスクのように働き、その結果として凹部の表面に微細構造が形成される。この微細構造は、基板上に半導体を成膜させたときに、凹部表面での結晶の異常成長を発生させる原因になると考えられる。
(ハ)ドライエッチングによる凹部形成後、マスクを除去するが、この工程では、通常、使用したマスクができるだけ完全に除去される方法と条件が選択される。しかし、デポジションにより生じる基板上の堆積物質を構成する材料は、マスクの材料と同じではない。そのために、マスクを略完全に除去できる方法と条件を用いても、この堆積物質は除去し切れない可能性がある。残留した堆積物質は、得られた基板上に半導体膜を成長させたときに、凹部表面での結晶の異常成長を発生させる原因となることが考えられる。
(ニ)物理エッチングの側面が強いエッチング条件の下では、材料の違いによるエッチング速度の差が小さいために、デポジションが発生し難い。なぜなら、基板表面上に堆積する物質も、基板とともにエッチング除去されていくからである(このことから、堆積物質がエッチングマスクとして働くことによる微細構造の形成も起こり難い)。そのために、物理エッチングの側面が強いエッチング条件を用いてデポジションを抑制しながら凹部を形成した基板では、半導体膜を成長させたときに凹部表面での結晶の異常成長が発生し難くなるものと考えられる。
In the manufacture of a semiconductor film formation substrate provided with a concavo-convex part, it can be obtained by increasing the selectivity ratio [(substrate etching speed) / (mask etching speed)] when forming a concave part using a dry etching method. Regarding the reason why abnormal growth of crystals is likely to occur on the surface of the recess when a semiconductor is formed on the formed substrate, and the abnormal growth can be prevented by lowering this selection ratio, the inventors have as follows. I am thinking about:
(A) Dry etching (especially RIE) has a chemical etching side and a physical etching side. The condition with a high selectivity in dry etching is a condition in which the etching rate differs greatly between the substrate and the mask made of different materials. Since the difference in material strongly affects the etching rate, it can be said that the etching under such conditions has a strong aspect of chemical etching. On the other hand, it can be said that etching under conditions where the selectivity is close to 1, that is, under conditions where the etching rate is not very different between different materials, has a strong aspect of physical etching.
(B) In the dry etching process, the etching gas and / or a part of the workpiece (substrate and mask) cause a chemical reaction by the energy supplied in the form of plasma, and the product of the reaction is deposited on the substrate. There are things to do. This phenomenon is called deposition. The material constituting the material deposited on the substrate surface by deposition is usually not the same as the material of the substrate. Therefore, under conditions where the side surface of chemical etching is strong, a difference occurs in the etching rate between the substrate and the deposited material. Under conditions with a high selectivity (which is set so that the etching rate of the substrate is increased), the etching rate of the substrate is usually much higher than the etching rate of the deposit, so that the deposit is like an etching mask. As a result, a fine structure is formed on the surface of the recess. This fine structure is considered to cause abnormal growth of crystals on the surface of the recess when a semiconductor is deposited on the substrate.
(C) After forming the recess by dry etching, the mask is removed. In this step, a method and conditions for removing the used mask as completely as possible are usually selected. However, the material constituting the deposited material on the substrate caused by deposition is not the same as the material of the mask. Therefore, even if a method and conditions that can remove the mask almost completely are used, the deposited material may not be completely removed. The remaining deposited material may cause abnormal growth of crystals on the surface of the recess when a semiconductor film is grown on the obtained substrate.
(D) Under the etching conditions where the side of physical etching is strong, the difference in etching rate due to the difference in materials is small, so that it is difficult for deposition to occur. This is because the substance deposited on the surface of the substrate is also removed by etching together with the substrate (this makes it difficult to form a fine structure due to the deposited substance acting as an etching mask). For this reason, in a substrate in which a recess is formed while suppressing deposition using etching conditions with strong physical etching side surfaces, abnormal growth of crystals on the surface of the recess is less likely to occur when a semiconductor film is grown. Conceivable.

なお、本発明に係る半導体成膜用基板の製造方法において、エッチングにより形成する凹部は、孔状の凹部であってもよいし、溝状の凹部であってもよい。また、凹部を形成することにより相補的に形成される凸部が、柱状(円柱、角柱など)や錘台状(円錐台、角錘台など)を呈すような、凹部であってもよい。凹部の断面形状は矩形状に限定されるものではなく、台形状、逆台形状、V字状、U字状などであってもよい。上記にいう基板のエッチング速度は、エッチングにより形成される凹部が明瞭な底面を有する形状であるか否かに関わりなく、凹部の深さの時間当りの増加率と定義される。ここでいう凹部の深さとは、凹部の最も深い部分における深さである。また、マスクのエッチング速度は、マスクの高さの時間当りの減少率と定義される。ここでいうマスクの高さは、マスクの最も厚い部分における厚さといってもよい。 In the method for manufacturing a semiconductor film forming substrate according to the present invention, the recess formed by etching may be a hole-like recess or a groove-like recess. Moreover, the convex part complementarily formed by forming a recessed part may be a recessed part which exhibits columnar shape (a cylinder, a prism, etc.) or frustum shape (a truncated cone, a truncated pyramid, etc.). The cross-sectional shape of the recess is not limited to a rectangular shape, and may be trapezoidal, inverted trapezoidal, V-shaped, U-shaped, or the like. The etching rate of the substrate mentioned above is defined as the rate of increase of the depth of the concave portion per hour regardless of whether or not the concave portion formed by etching has a shape having a clear bottom surface. The depth of the recess here is the depth at the deepest portion of the recess. The etching rate of the mask is defined as the rate of decrease of the mask height per time. The height of the mask here may be referred to as the thickness at the thickest portion of the mask.

本発明に係る半導体成膜用基板の製造方法は、AlGaInN系半導体(例えば、GaN、AlN、GaAlN、GaInN、AlGaInN)などの3−5族化合物半導体の成膜用基板をはじめとして、各種の半導体成膜用基板の製造に適用することができる。 The method for manufacturing a semiconductor film forming substrate according to the present invention includes various semiconductors including a film forming substrate for a Group 3-5 compound semiconductor such as an AlGaInN-based semiconductor (for example, GaN, AlN, GaAlN, GaInN, AlGaInN). The present invention can be applied to the manufacture of a film formation substrate.

本発明をAlGaInN系半導体成膜用基板の製造に適用する場合、使用可能な出発基板(凹凸を設ける前の基板)として、サファイア(C面、A面、R面)基板、SiC(6H、4H、3C)基板、GaN基板、AlN基板、Si基板、スピネル基板、ZnO基板、GaAs基板、NGO基板、LGO基板、LAO基板、ZrB基板、TiB基板などが好ましく例示される。サファイア、SiC、GaN、AlN、Si、スピネル、ZnO、GaAs、NGO、LGO、LAO、ZrB、TiBなどからなる単結晶層を表層として有する多層構造基板も好ましく使用可能である。 When the present invention is applied to the production of an AlGaInN-based semiconductor film-forming substrate, sapphire (C-plane, A-plane, R-plane) substrate, SiC (6H, 4H) can be used as a usable starting substrate (substrate before unevenness is provided). 3C) Substrate, GaN substrate, AlN substrate, Si substrate, spinel substrate, ZnO substrate, GaAs substrate, NGO substrate, LGO substrate, LAO substrate, ZrB 2 substrate, TiB 2 substrate and the like are preferably exemplified. A multilayer structure substrate having a single crystal layer made of sapphire, SiC, GaN, AlN, Si, spinel, ZnO, GaAs, NGO, LGO, LAO, ZrB 2 , TiB 2 or the like as a surface layer can also be preferably used.

本発明の製造方法において、基板の表面に形成するマスクには、フォトレジスト膜の他、SiO、Siなどからなる無機膜、ニッケル(Ni)、クロム(Cr)、アルミニウム(Al)、チタン(Ti)、白金(Pt)などからなる金属膜を用いることができる。 In the manufacturing method of the present invention, the mask formed on the surface of the substrate includes a photoresist film, an inorganic film made of SiO 2 , Si 3 N 4 , nickel (Ni), chromium (Cr), aluminum (Al). A metal film made of titanium (Ti), platinum (Pt), or the like can be used.

本発明の製造方法において、ドライエッチング法を用いた凹部の形成は、公知のRIE装置を用いて行うことができる。エッチングガスとしては、塩素、フッ素などのハロゲン元素を含むガスが好ましく例示され、塩素ガス(Cl)、四塩化ケイ素(SiCl)、三塩化ホウ素(BCl)、臭化水素(HBr)、六フッ化イオウ(SF)、トリフロロメタン(CHF)、テトラフロロメタン(CF)などのガスを単独で、または混合して用いることができる。これらのガスを、アルゴン(Ar)などの不活性ガスと混合して用いることもできる。不活性ガスを単独で用いることも可能である。 In the manufacturing method of the present invention, the formation of the concave portion using the dry etching method can be performed using a known RIE apparatus. As the etching gas, a gas containing a halogen element such as chlorine and fluorine is preferably exemplified, and chlorine gas (Cl 2 ), silicon tetrachloride (SiCl 4 ), boron trichloride (BCl 3 ), hydrogen bromide (HBr), Gases such as sulfur hexafluoride (SF 6 ), trifluoromethane (CHF 3 ), and tetrafluoromethane (CF 4 ) can be used alone or in combination. These gases can be mixed with an inert gas such as argon (Ar). It is also possible to use an inert gas alone.

好ましい実施形態のひとつでは、基板に凹部を形成する工程において、デポジションを十分に抑制するために、最初から最後まで選択比0.5〜2(基板のエッチング速度がマスクのエッチング速度の半分〜2倍)という条件でエッチングを行うことができるが、限定されるものではない。この工程では、少なくとも最後に選択比0.5〜2でエッチングを行って、エッチングを終了すれば、それまでに基板上に堆積した堆積物の少なくとも一部は除去できるので、本発明の効果を得ることができる。特に、凹部を深く形成する場合(例えば、深さ1μm以上)には、最初の1/2〜3/4は選択比が2より大きい条件でエッチングを行い、残りの部分を選択比0.5〜2でエッチングすることが好ましい。具体的にいうと、深さ1.2μmの凹部を形成する場合であれば、深さが0.6μm〜0.9μmとなるまでは2より大きい選択比でエッチングを行い、その後、エッチング条件を変化させて選択比を下げて0.5〜2とし、深さが1.2μmとなるまでエッチングを行うのである。なぜなら、最初から最後まで選択比0.5〜2という条件でエッチングを行おうとすると、凹部の形成に要する時間が長くなって製造効率が低下するだけでなく、マスクを厚く形成する必要が生じる関係から、マスク材料の消費量が増加する問題、マスク形成に要する時間が長くなる問題、マスクの正確なパターニングが難しくなる問題、マスクパターンが壊れ易くなる問題、エッチング後のマスク除去に要する時間が長くなる問題、マスク除去に必要な薬剤や洗浄液の消費量が増加する問題など、種々の問題が発生し得るからである。 In one of the preferred embodiments, in order to sufficiently suppress the deposition in the step of forming the recesses in the substrate, the selection ratio is 0.5 to 2 from the beginning to the end (the substrate etching rate is half the mask etching rate). Etching can be performed under the condition of (twice), but is not limited. In this step, at least lastly, etching is performed at a selection ratio of 0.5 to 2, and at the end of the etching, at least a part of the deposits deposited on the substrate can be removed. Obtainable. In particular, when the concave portion is formed deeply (for example, a depth of 1 μm or more), the first 1/2 to 3/4 are etched under a condition where the selectivity is larger than 2, and the remaining portion is etched with a selectivity of 0.5. Etching at ~ 2 is preferred. Specifically, in the case of forming a recess having a depth of 1.2 μm, etching is performed with a selection ratio larger than 2 until the depth reaches 0.6 μm to 0.9 μm, and then the etching conditions are changed. Etching is performed until the selection ratio is lowered to 0.5 to 2 and the depth is 1.2 μm. This is because if etching is performed from the first to the last with a selection ratio of 0.5 to 2, not only does the time required for forming the recesses increase, the manufacturing efficiency decreases, but also the mask needs to be formed thicker. Therefore, there is a problem that the consumption of the mask material increases, a problem that the time required for mask formation becomes long, a problem that accurate patterning of the mask becomes difficult, a problem that the mask pattern is easily broken, and a time that it takes to remove the mask after etching is long. This is because various problems may occur, such as a problem that the consumption of chemicals and cleaning liquid necessary for mask removal increases.

本発明の好ましい実施形態では、選択比0.5〜2でドライエッチングするときの選択比として1に近い選択比を用いる。前述のように、選択比が1に近いほど物理エッチングの側面が強く、デポジションが効果的に抑制されると考えられる。 In a preferred embodiment of the present invention, a selection ratio close to 1 is used as the selection ratio when dry etching is performed at a selection ratio of 0.5-2. As described above, it is considered that the closer the selection ratio is to 1, the stronger the side surface of physical etching, and the more effective the deposition is suppressed.

エッチング後のマスク除去は、従来公知の方法を用いて行うことができる。マスクが無機膜あるいは金属膜である場合には、酸またはアルカリを用いて除去することができる。 The mask removal after the etching can be performed using a conventionally known method. When the mask is an inorganic film or a metal film, it can be removed using acid or alkali.

本発明の実施形態に係る半導体成膜用基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the board | substrate for semiconductor film-forming concerning embodiment of this invention.

符号の説明Explanation of symbols

1 基板
2 マスク
1 Substrate 2 Mask

Claims (3)

基板の表面に部分的にマスクを形成する工程と、ドライエッチング法を用いて前記基板の表面の前記マスクに覆われていない部分をエッチング除去して凹部を形成する工程とを、この順に行うことにより、基板の表面に凹凸部を設ける、半導体成膜用基板の製造方法であって、
前記凹部を形成する工程においては、少なくとも最後に基板のエッチング速度をマスクのエッチング速度の半分〜2倍とすることによりデポジションを抑制しながらエッチングを行ったところでエッチングを終了することを特徴とする、半導体成膜用基板の製造方法。
A step of partially forming a mask on the surface of the substrate, and a step of forming a recess by etching away a portion of the surface of the substrate that is not covered with the mask using a dry etching method are performed in this order. A method for manufacturing a semiconductor film-forming substrate, wherein an uneven portion is provided on the surface of the substrate,
In the step of forming the recess, at least the etching rate of the substrate is set to half to twice the etching rate of the mask, and the etching is terminated when the etching is performed while suppressing deposition. , A method of manufacturing a semiconductor film forming substrate.
前記凹部を形成する工程においては、最初から最後まで基板のエッチング速度をマスクのエッチング速度の半分〜2倍とすることによりデポジションを抑制しながらエッチングを行う、請求項1に記載の製造方法。 2. The manufacturing method according to claim 1, wherein in the step of forming the recess, etching is performed while suppressing deposition by setting the etching rate of the substrate from half to two times the etching rate of the mask from the beginning to the end. 前記凹部を形成する工程においては、少なくとも最後に基板のエッチング速度とマスクのエッチング速度とを略同じにしてエッチングを行ったところでエッチングを終了する、請求項1に記載の製造方法。 2. The manufacturing method according to claim 1, wherein in the step of forming the concave portion, the etching is terminated when the etching is performed at least last with the etching rate of the substrate and the etching rate of the mask being substantially the same.
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Publication number Priority date Publication date Assignee Title
JP2012129342A (en) * 2010-12-15 2012-07-05 Panasonic Corp Plasma processing method of substrate
JP5550196B2 (en) * 2010-06-16 2014-07-16 株式会社アルバック Substrate etching method and sapphire substrate manufacturing method
JP2018093017A (en) * 2016-12-01 2018-06-14 國家中山科學研究院 Method of patterning with high aspect ratio on polycrystalline aluminum nitride substrate

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JP2000232095A (en) * 1999-02-12 2000-08-22 Nippon Telegr & Teleph Corp <Ntt> Formation method for fine pattern of semiconductor surface
JP2005327821A (en) * 2004-05-12 2005-11-24 Nichia Chem Ind Ltd Nitride semiconductor, nitride semiconductor substrate, nitride semiconductor element and those manufacturing method

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JP2000232095A (en) * 1999-02-12 2000-08-22 Nippon Telegr & Teleph Corp <Ntt> Formation method for fine pattern of semiconductor surface
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JP5550196B2 (en) * 2010-06-16 2014-07-16 株式会社アルバック Substrate etching method and sapphire substrate manufacturing method
JP2012129342A (en) * 2010-12-15 2012-07-05 Panasonic Corp Plasma processing method of substrate
JP2018093017A (en) * 2016-12-01 2018-06-14 國家中山科學研究院 Method of patterning with high aspect ratio on polycrystalline aluminum nitride substrate

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