JP2008288622A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve productivity in assembling a semiconductor integrated circuit device. <P>SOLUTION: After preparing a multipiece substrate 3g, a semiconductor chip is placed on a first heating stage 9b. After that, on the first heating stage 9b, the multipiece substrate 3g is placed on the semiconductor chip. Subsequently, while the semiconductor chip is directly heated on the first heating stage 9b, the semiconductor chip and the multipiece substrate 3g are tentatively bonded with heat crimping. After the tentative bonding, the tentatively bonded multipiece substrate 3g is placed on a second heating stage 10b arranged adjacent to the first heating stage 9b. After that, while the semiconductor chip, on the second heating stage 10b, is directly heated with the second heating stage 10b, the semiconductor chip is pressed, and the semiconductor chip and the multipiece substrate 3g are subjected to final bonding with heat crimping. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a method for manufacturing a semiconductor integrated circuit device in which a semiconductor chip is bonded to a substrate.

In the conventional bonding of a substrate and a silicon chip, a substrate is arranged on a substrate rest (stage), a plurality of silicon chips are arranged on the substrate, and the silicon chip is interposed via the substrate by a heating cartridge provided on the substrate rest. (For example, see Patent Document 1 and Patent Document 2 which is a European patent application corresponding to Patent Document 1).
Japanese translation of PCT publication No. 2002-534799 (FIG. 2) EP1030349A2 (FIG. 2)

  In the bonding of the wiring substrate and the semiconductor chip by flip chip connection, the semiconductor chip is picked up from the semiconductor wafer, and the semiconductor chip is arranged on the substrate with the main surface of the semiconductor chip facing the substrate side, and then the semiconductor chip and the wiring substrate are heated. They are joined by crimping.

  Therefore, a mechanism for transporting the semiconductor chip onto the substrate is disposed on the upper side of the wiring substrate. On the other hand, the heating mechanism is disposed on the upper side of the substrate because the transport mechanism is disposed on the upper side of the substrate, and is thus embedded in the stage on the lower side of the wiring substrate.

  If heating is performed from the stage side in this structure, the bonding portion between the chip and the substrate is heated via the wiring substrate, so that the temperature of the bonding portion does not rise sufficiently and a defective bonding occurs. Become.

  Further, when the heating temperature is increased so as to obtain a sufficient temperature of the joint portion, there arises a problem that deformation such as warpage occurs in the wiring substrate, or that the crimp portion is peeled off and a defect occurs in the subsequent process.

  An object of the present invention is to provide a technique capable of improving productivity.

  Another object of the present invention is to provide a technique capable of stabilizing the bonding quality of a chip.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention includes (a) a step of preparing an organic wiring board having a plurality of device formation regions and a base substrate made of an organic material; (b) a main surface on which an integrated circuit is formed; Preparing a plurality of semiconductor chips having a back surface opposite to the main surface; (c) bonding the plurality of semiconductor chips with an adhesive so that the main surface side of the plurality of semiconductor chips faces the organic wiring substrate; A step of temporarily adhering to the plurality of device formation regions of the organic wiring substrate via the step; (d) the plurality of semiconductor chips are temporarily bonded so that the back surfaces of the plurality of semiconductor chips are in contact with a heating stage; A step of disposing the organic wiring substrate on the heating stage; (e) the plurality of semiconductor chips are heated at the first temperature by the heating stage and disposed above the organic wiring substrate; A step of heating the organic wiring substrate at a second temperature by a thermo jig to fully bond the plurality of semiconductor chips to the device forming region of the organic wiring substrate with the adhesive. The second temperature by the jig is lower than the first temperature by the heating stage.

The outline of other inventions of the present application is divided into sections and shown below. That is,
1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) preparing a substrate;
(B) a step of disposing a plurality of semiconductor chips on the stage with each major surface facing upward;
(C) disposing the substrate above the plurality of semiconductor chips;
(D) A step of bonding the plurality of semiconductor chips to the substrate by thermocompression bonding (referring to pressure bonding, bonding, adhesion, etc. with heating).

    2. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an organic substrate is used as the substrate.

3. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) preparing a substrate;
(B) placing a plurality of semiconductor chips on a heating stage;
(C) disposing the substrate above the plurality of semiconductor chips;
(D) While directly heating the plurality of semiconductor chips by the heating stage, the corresponding semiconductor chips are added by a plurality of pressure blocks that are supported independently of the plurality of semiconductor chips. Pressing the plurality of semiconductor chips together by thermocompression bonding.

    4). In the method of manufacturing a semiconductor integrated circuit device according to the item 3, when the substrate and the semiconductor chip are sandwiched and crimped by the plurality of pressure blocks and the heating stage in the step (d), Air of a first pressure is applied to the plurality of pressure blocks, and in this state, each of the plurality of pressure blocks is brought into contact with the substrate, or the plurality of semiconductor chips are brought into contact with the heating stage. A method of manufacturing a semiconductor integrated circuit device, wherein air compression is performed by applying air having a second pressure higher than the first pressure to the plurality of pressure blocks.

    5. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the pressure applied to the pressure block in the step (d) is gradually increased from a low pressure and connected to a support block portion that supports the plurality of pressure blocks. A load change detecting means provided as described above detects a change point of a load applied to the load change detecting means, thereby obtaining a magnitude of pressure applied to the plurality of semiconductor chips. Production method.

    6). 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the plurality of pressure blocks and the heating stage are brought into contact with each other before the step (b), and the pressure applied to the pressure blocks in this state is applied. By gradually increasing the pressure from the low pressure and detecting the change point of the load applied to the load change detecting means by the load change detecting means provided in connection with the support block portion supporting the plurality of pressurizing blocks, A method for manufacturing a semiconductor integrated circuit device, comprising: obtaining a set value of pressure applied to the plurality of pressure blocks when the semiconductor chip is placed on the heating stage and thermocompression bonded.

    7. 4. The manufacturing method of a semiconductor integrated circuit device according to claim 3, wherein the plurality of pressurizing blocks are pressurized with air through a single sheet-like elastic film. Method.

8). A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) preparing a substrate;
(B) placing the semiconductor chip on the first heating stage;
(C) Disposing the substrate above the semiconductor chip on the first heating stage, and then thermocompression bonding the semiconductor chip and the substrate while directly heating the semiconductor chip by the first heating stage. A step of temporarily joining by:
(D) After the step (c), placing the temporarily bonded semiconductor chip and the substrate on a second heating stage provided adjacent to the first heating stage;
(E) While directly heating the semiconductor chip on the second heating stage by the second heating stage, pressurizing the semiconductor chip for a time longer than the pressing on the first heating stage, the semiconductor chip And a step of joining the substrate and the substrate by thermocompression bonding.

    9. 9. The manufacturing method of a semiconductor integrated circuit device according to claim 8, wherein the plurality of semiconductor chips are arranged on the second heating stage, and the plurality of semiconductor chips are directly heated by the second heating stage. A method of manufacturing a semiconductor integrated circuit device, wherein the semiconductor chips are collectively bonded to the substrate by thermocompression bonding.

    10. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein, before the step (b), the pressurizing blocks are respectively applied to a plurality of pressurizing blocks that are independently movable corresponding to the plurality of semiconductor chips. A high pressure is applied so that the block cannot be pushed up, and the plurality of pressure blocks and the second heating stage are brought into contact with each other in this state, and are connected to a support block portion that supports the plurality of pressure blocks. A method for manufacturing a semiconductor integrated circuit device, wherein landing heights of the plurality of pressure blocks are obtained by detecting a change point of a load applied to the load change detecting means by the load change detecting means.

    11. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein a support block portion that supports a plurality of pressure blocks that are supported independently of each other corresponding to the plurality of semiconductor chips is detachably attached to the main body portion. A method for manufacturing a semiconductor integrated circuit device, comprising:

    12 12. The manufacturing method of a semiconductor integrated circuit device according to claim 11, wherein the support block portion is detachably provided on the main body portion via a spacer.

    13. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the second heating stage is provided with a plurality of small stages smaller than the back surface of the semiconductor chip, and the semiconductor chip is disposed on the plurality of small stages. A method for manufacturing a semiconductor integrated circuit device, characterized by comprising:

    14 9. The manufacturing method of a semiconductor integrated circuit device according to claim 8, wherein the second heating stage is provided with a plurality of suction systems that open to a surface on the chip arrangement side, and heat of the semiconductor chip and the substrate is provided. A method of manufacturing a semiconductor integrated circuit device, wherein the foreign matter on the surface on the chip arrangement side is removed by suction through the suction system of the second heating stage at the time of pressure bonding.

15. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) preparing a substrate;
(B) placing the semiconductor chip on the heating stage;
(C) disposing the substrate above the semiconductor chip;
(D) The semiconductor chip is heated by the heating stage, the substrate is heated by heating means disposed above the semiconductor chip, and the semiconductor chip side is heated at a higher temperature than the substrate side to The process of joining the substrate by thermocompression bonding.

    16. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the substrate side is heated at 150 ° C. or less by the heating means.

    17. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the substrate side is heated at 100 ° C. or less by the heating means.

    18. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the substrate side is heated at 50 ° C. or less by the heating means.

    19. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the substrate side is heated at room temperature by the heating means.

    20. 16. The method for manufacturing a semiconductor integrated circuit device according to item 15, wherein an organic substrate is used as the substrate.

Furthermore, the outline | summary of the other invention of this application is divided into items and is shown below. That is,
1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) preparing a multi-chip substrate in which a plurality of device regions which are regions of the semiconductor integrated circuit device are formed in a matrix arrangement;
(B) a step of disposing each of the plurality of semiconductor chips on the stage with each main surface facing upward;
(C) placing the multi-cavity substrate above the plurality of semiconductor chips;
(D) A step of collectively bonding the plurality of semiconductor chips to the multi-chip substrate by thermocompression bonding for each column or a plurality of columns in the width direction of the device region in the matrix arrangement of the multi-chip substrate.
2. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) preparing a multi-chip substrate in which a plurality of device regions which are regions of the semiconductor integrated circuit device are formed in a matrix arrangement;
(B) placing a plurality of semiconductor chips on a heating stage;
(C) placing the multi-cavity substrate above the plurality of semiconductor chips;
(D) While directly heating the plurality of semiconductor chips by the heating stage, the corresponding semiconductor chips are added by a plurality of pressure blocks that are supported independently of the plurality of semiconductor chips. Pressing the plurality of semiconductor chips together in one or more columns in the width direction of the device region of the matrix arrangement of the multi-chip substrate by thermocompression bonding.

Furthermore, the summary of other inventions of the present application is divided into sections and shown below.
3. Semiconductor manufacturing apparatus having the following configuration:
(A) a heating stage on which a plurality of semiconductor chips can be arranged;
(B) A plurality of pressurizing blocks supported independently of each other corresponding to the plurality of semiconductor chips are provided, and a space for supplying air for pressurizing the plurality of pressurizing blocks is provided. Support block;
(C) an air intake portion for taking air into the space portion of the support block portion;
(D) A load change detection means that is provided in connection with the support block portion and detects a load change point.
4). Semiconductor manufacturing apparatus having the following configuration:
(A) a heating stage on which a plurality of semiconductor chips can be arranged;
(B) a plurality of pressurizing blocks that are supported independently of each other in correspondence with the plurality of semiconductor chips, and have a space for supplying air for pressurizing the plurality of pressurizing blocks; And a support block part detachably provided on the main body part;
(C) an air intake portion for taking air into the space portion of the support block portion;
(D) A load change detection means that is provided in connection with the support block portion and detects a load change point.
5. Semiconductor manufacturing apparatus having the following configuration:
(A) a heating stage in which a semiconductor chip can be arranged in each, and a plurality of small stages smaller than the back surface of the semiconductor chip are provided;
(B) It has a plurality of pressurizing blocks supported independently of each other so as to correspond to the plurality of semiconductor chips, and has a space for supplying air for pressurizing the plurality of pressurizing blocks. Support block;
(C) an air intake portion for taking air into the space portion of the support block portion;
(D) A load change detection means that is provided in connection with the support block portion and detects a load change point.
6). Semiconductor manufacturing apparatus having the following configuration:
(A) a heating stage on which a plurality of semiconductor chips can be arranged;
(B) It has a plurality of pressurizing blocks supported independently of each other so as to correspond to the plurality of semiconductor chips, and has a space for supplying air for pressurizing the plurality of pressurizing blocks. Support block;
(C) a sheet-like elastic membrane disposed in the support block portion and in close contact with the plurality of pressure blocks;
(D) an air intake portion for taking air into the space portion of the support block portion;
(E) A load change detection means that is connected to the support block portion and detects a load change point.

  The effects obtained by the embodiments corresponding to the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  Die bonding is divided into a first heating stage and a second heating stage, temporary bonding is performed in a short time on the first heating stage, and a plurality of semiconductor chips are collectively bonded together on the second heating stage. As a result, the bonding time can be shortened. Thereby, the throughput of die bonding can be improved and the productivity can be improved.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  In addition, when referring to the component of the member (for example, the member X made of A), it is not excluded to exclude other components unless specifically stated otherwise or otherwise clearly stated. . The same applies to atmospheric gases.

  In addition, the term “semiconductor integrated circuit device” (simply a semiconductor chip) is used not only on a silicon semiconductor chip but also on an SOI substrate, unless otherwise specified. Including those made on other substrates such as TFT liquid crystal.

  Similarly, when referring to an integrated circuit chip or the like, except for a case where it is not specifically stated, not only a silicon single crystal chip but also an approximately square or rectangular shape for producing an SOI substrate, a GaAs substrate, and other TFT liquid crystals. Includes integrated circuit boards and the like.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
FIG. 1 is a perspective view showing an example of the structure on the external terminal side of the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 2 shows an example of the internal structure on the chip side of the semiconductor integrated circuit device shown in FIG. FIG. 3 is a sectional view showing an example of the structure of the semiconductor integrated circuit device shown in FIG. 1, and FIG. 4 is a manufacturing process flow showing an example of an assembly procedure of the semiconductor integrated circuit device shown in FIG. 5 is a plan view showing an example of the structure on the front side of the wiring board in the assembly shown in FIG. 4, FIG. 6 is a plan view showing an example of the structure on the back side of the wiring board in the assembly shown in FIG. Is a plan view showing an example of the structure on the back side of the wiring board after die bonding in the assembly shown in FIG. 4, FIG. 8 is a plan view showing an example of a schematic structure of the semiconductor manufacturing apparatus according to the embodiment of the present invention, FIG. Is the structure of the main part of the semiconductor manufacturing apparatus shown in FIG. FIG. 10 is a perspective view showing an example of the structure of the main part of the semiconductor manufacturing apparatus shown in FIG. 8, and FIG. 11 shows an example of the structure on the second heating stage side of the main part shown in FIG. 12 is a cross-sectional view showing an example of an operation flow at the time of low-load landing of the main part shown in FIG. 11, and FIG. 13 is a cross-sectional view showing an operation flow at the time of low-load landing of a modification of the main part shown in FIG. 14 is a cross-sectional view showing an example of the structure at the time of landing detection of the main part shown in FIG. 11, FIG. 15 is a cross-sectional view showing an example of the structure at the time of setting the load of the main part shown in FIG. 11, and FIG. 11 is a cross-sectional view showing an example of the structure of the main part shown in FIG. 11 when the product type is switched, FIG. 17 is a cross-sectional view showing an example of the elastic body contact state in the main part shown in FIG. 11, and FIG. FIG. 19 is a sectional view showing an example of the suction state, and FIG. FIG. 20 is a perspective view showing an example of a mounting method of the support block shown in FIG. 19, and FIG. 21 is a configuration of internal components of the support block shown in FIG. 22 is a cross-sectional view showing an example of the structure of the support block portion shown in FIG. 20, FIG. 23 is a cross-sectional view showing the structure of various modifications of the support block portion shown in FIG. These are sectional drawings which show the structure of the semiconductor integrated circuit device of the modification of embodiment of this invention.

  The semiconductor integrated circuit device of the present embodiment is a resin-encapsulated semiconductor package in which an organic substrate 3 that is a wiring substrate and a semiconductor chip 1 are bonded. In the present embodiment, an example thereof is shown in FIG. Such a BOC (Board On Chip) 7 will be described.

  The structure of the BOC 7 shown in FIGS. 1 to 3 will be described. It has an elongated opening 3e formed along the longitudinal direction at the center of one surface, and further in two rows on both sides of the opening 3e. An organic substrate 3 having a plurality of bonding electrodes 3c provided adjacent to the bump lands 3f and the openings 3e and wiring 3d for electrically connecting the bump lands 3f and the bonding electrodes 3c; The semiconductor chip 1 bonded to the other surface of the semiconductor chip 3 via the insulating die-bonding tape 2, and a plurality of pads (surface electrodes) 1a of the semiconductor chip 1 and the bonding electrodes 3c corresponding thereto are electrically connected. A wire 4, a sealing body 6 that seals the semiconductor chip 1 and the plurality of wires 4 with resin, and a plurality of solder boards that are external terminals provided on each bump land 3 f Consisting of 5.

  The semiconductor chip 1 is formed of, for example, silicon and has an integrated circuit incorporated therein. Further, the semiconductor chip 1 is bonded to the organic substrate 3 via a die bond tape 2 (also referred to as an elastomer, a die attach tape, or a die bond film) with its main surface (first main surface) 1b facing the substrate side. .

  That is, the organic substrate 3 is disposed on the main surface 1b of the semiconductor chip 1 via the die-bonding tape 2, and the pad 1a of the semiconductor chip 1 is connected via the opening 3e of the organic substrate 3 as shown in FIG. A bonding electrode 3 c shown in FIG. 1 of the organic substrate 3 corresponding to this is connected by a wire 4.

  The wire 4 is, for example, a gold wire.

  The organic substrate 3 is an organic wiring substrate in which wiring 3d made of copper or the like, bump lands 3f, and bonding electrodes 3c are formed on a base substrate made of an organic material. The wiring 3d is covered and insulated and protected by a solder resist film which is an organic insulating film (organic layer).

  The sealing body 6 is, for example, an epoxy resin.

  Next, assembly of the BOC 7 will be described.

  First, as shown in step S1 of FIG. 4 and FIG. 5, a multi-piece substrate 3g in which device regions 3h that are regions of a plurality of BOCs 7 are formed in a matrix arrangement is prepared. That is, the multi-cavity substrate 3g has a plurality of organic substrates 3. FIG. 5 shows a structure on the surface 3a side of the multi-piece substrate 3g. In each device region 3h, a plurality of wirings 3d are formed on both sides of the central opening 3e.

  FIG. 6 shows the structure on the back surface 3b side of the multi-chip substrate 3g. In each device region 3h, the die bond tape 2 as an elastomer is attached to both sides of the central opening 3e. Yes. Alternatively, an adhesive such as a thermoplastic resin may be applied as an elastomer.

  The adhesive material may be either thermoplastic or thermosetting, and is made of, for example, a single-layer material. When the adhesive is an application material, a semi-cured application material is applied.

  Thereafter, as shown in step S2 of FIG. 4 and FIG. 7, die bonding is performed in which the semiconductor chip 1 is bonded to each device region 3h on the back surface 3b side of the multi-piece substrate 3g via the die bond tape 2. At that time, the main surface 1b side of the semiconductor chip 1 is bonded to the die-bonding tape 2 so that the pads 1a of the semiconductor chip 1 are arranged in the openings 3e of the device regions 3h of the multi-chip substrate 3g. Join.

  Thereafter, wire bonding shown in step S3 is performed.

  That is, as shown in FIG. 3, the pads 1a of the semiconductor chip 1 and the bonding electrodes 3c (see FIG. 1) in the device region 3h of the multi-chip substrate 3g corresponding thereto are connected by the wires 4.

  Thereafter, resin molding shown in step S4 is performed.

  Here, a plurality of device regions 3h on the multi-piece substrate 3g are collectively molded with resin.

  Thereafter, ball mounting shown in step S5 is performed.

  Here, solder balls 5 serving as external terminals are mounted on the bump lands 3f in the device regions 3h of the multi-chip substrate 3g.

  Thereafter, dicing shown in step S6 is performed to separate each package. That is, the multi-chip substrate 3g and the sealing body 6 are cut into individual device regions 3h by dicing to be separated into individual pieces.

  Thereby, the assembly of the BOC 7 is completed.

  Next, as a method for manufacturing the semiconductor integrated circuit device (BOC7) of the present embodiment, details of die bonding in assembling the BOC7 will be described.

  First, the main configuration of the chip mounter (semiconductor manufacturing apparatus) 8 used in the die bonding (chip mounting) process will be described.

  A chip mounter 8 shown in FIG. 8 includes a first pressure-bonding portion 9 that performs temporary pressure bonding (temporary bonding) between the multi-piece substrate 3g and the semiconductor chip 1, and a second pressure bonding (main bonding) after the temporary pressure bonding. The crimping section 10, the stocker 11 for storing the multi-piece substrate 3g before chip crimping, the handler 13 for taking out the multi-piece substrate 3g from the stocker 11 and transferring it to the guide rail 12, and the multi-piece substrate 3g. A pre-baking section 14 for loading, a load port 15 for storing a diced semiconductor wafer, a carry-out robot 16 for taking out the semiconductor wafer from the load port 15 and transferring it to the wafer stage 17, and a semiconductor chip 1 from the semiconductor wafer on the wafer stage 17 Pick-up unit 18 that picks up and conveys it to the first crimping unit 9 and the semiconductor chip 1 after the final crimping And a product unloader 19 for accommodating the matrix substrate 3g.

  As shown in FIGS. 9 and 10, the first pressure-bonding portion 9 includes a first head 9 a that applies pressure, a first heating stage (first stage) 9 b on which the semiconductor chip 1 can be mounted, Are provided, and a heater 9c as a heating means is incorporated in each. The first head 9a is provided with a support block portion 9f having a pressure block 9g at the tip thereof, and the support block portion 9f is attached to the block main body portion 9d. Further, the block main body portion 9d is connected to the inclination adjusting mechanism portion 9e.

  The first heating stage 9b is attached to the XY stage 9h.

  As described above, as shown in FIG. 9, the first crimping section 9 performs positioning of the semiconductor chip 1 and temporary crimping of the semiconductor chip 1 and the multi-piece substrate 3g as one step. The temporary pressure bonding is bonding to such an extent that the semiconductor chip 1 is not peeled off. In the first pressure bonding section 9, the heat bonding is performed for each chip by the first head 9a.

  In the thermocompression bonding, the semiconductor chip 1 is directly heated by the first heating stage 9b without interposing the multi-chip substrate 3g, and the block main body 9d disposed above the multi-chip substrate 3g. The junction between the semiconductor chip 1 and the multi-chip substrate 3g is heated by the heater 9c through the multi-chip substrate 3g. The pressurizing time for one semiconductor chip 1 in the first crimping section 9 is, for example, about 0.1 second.

  On the other hand, the second pressure bonding part 10 is provided with a second head 10a for applying pressure and a second heating stage (second stage) 10b on which the semiconductor chip 1 can be mounted. A heater 10c which is a heating means is incorporated. The second head 10a includes a support block portion 10m having a plurality of pressure blocks 10n at the tip thereof, and the support block portion 10m is detachably attached to a block main body portion (main body portion) 10d. It has been. Further, the block main body 10d is connected to the tilt adjusting mechanism 10i.

  Further, the plurality of pressure blocks 10n are arranged in a space portion 10p formed inside by the support block portion 10m and the block main body portion 10d, and in the space portion 10p, a single sheet-like elastic film 10t is used. Each is supported in the support block 10m in a state of being pressed independently and vertically.

  An air supply system 10q, which is an air passage for supplying air to the space 10p, is formed in the block main body 10d.

  As described above, in the second crimping portion 10, as shown in FIG. 9, the multi-chip substrate of a plurality of semiconductor chips 1 is obtained as two steps with respect to the semiconductor chip 1 that has been temporarily crimped by the first crimping portion 9. A main pressure bonding to 3 g is performed. During the main pressure bonding, a high pressure is supplied from the air supply system 10q of the block main body 10d to the space 10p to pressurize each pressure block 10n with a desired set load, and a plurality of semiconductor chips 1 are provided. Is directly heated by the second heating stage 10b.

  That is, in the second crimping section 10, a plurality of semiconductor chips 1 (for example, three semiconductor chips 1 in FIG. 9) are heated and pressed together (simultaneously). The pressurizing time for one semiconductor chip 1 in the second crimping part 10 is much longer than that of the first crimping part 9, for example, about 4 seconds.

  Further, as shown in FIG. 11, the load cell 10e, which is a load change detecting means, is incorporated in the second head 10a, and the total load applied to the semiconductor chip 1 during actual thermocompression bonding is as follows. The landing height of the head tip (tip of the pressure block 10n) can be detected.

  The load cell 10e is arranged on the load cell support portion 10h, and is sandwiched and supported by the height control plate 10f, and has a structure capable of canceling the dead weight of the block on the tip side after the load cell 10e. Yes. The height control plate 10f can be height-controlled by a servo driving motor 10g. Further, the load cell support portion 10h is connected to the block main body portion 10d via the inclination adjustment mechanism portion 10i. The inclination adjusting mechanism 10i adjusts the inclination of the block main body 10d.

  The height of the second heating stage 10b can also be servo-controlled.

  Further, in the second head 10a, it is possible to control the load only with the tip pressure. That is, the load applied to the plurality of pressure blocks 10n can be switched by controlling the amount of air sent from the air supply system 10q of the block body 10d to the space 10p.

  Thereby, at the time of thermocompression bonding in the second crimping portion 10, as shown in FIGS. 12A to 12D, the plurality of pressure blocks 10n can be landed on the product with a low load.

  That is, the multi-chip substrate 3g on which each semiconductor chip 1 is temporarily bonded by the first heating stage 9b of the first pressure bonding part 9 is used as the second pressure bonding part 10 adjacent to the first pressure bonding part 9. It arrange | positions on the heating stage 10b. At this time, the semiconductor chip 1 is arranged on the lower side of the multi-piece substrate 3g, that is, on the second heating stage 10b side, and the air pressure from the air supply system 10q of the block main body 10d to the space 10p is low (first Air) is applied to a plurality of pressure blocks 10n (A in FIG. 12).

  Subsequently, the second heating stage 10b is raised in this state, and a plurality of semiconductor chips 1 are placed on the second heating stage 10b (B in FIG. 12). Since the heater 10c is incorporated in the second heating stage 10b, each of the plurality of semiconductor chips 1 is directly heated by the second heating stage 10b.

  Thereafter, the second head 10a is lowered, and a plurality of pressure blocks 10n supported by the support block 10m so as to be independently movable are brought into contact with the substrate 3g (C in FIG. 12).

  After the multi-chip substrate 3g and the plurality of semiconductor chips 1 are sandwiched between the second heating stage 10b and the plurality of pressure blocks 10n, the high pressure (second pressure) is higher than the low pressure (first pressure). Air is supplied from the air supply system 10q of the block main body 10d to the space 10p and applied to the plurality of pressure blocks 10n (D in FIG. 12).

  At that time, after all the pressure blocks 10n have landed on the multi-piece substrate 3g with a small load, the pressure is switched to a high pressure in a state where the variation in the height of each pressure block 10n is absorbed by the elastic film 10t.

  In this state, on the second heating stage 10b of the second crimping section 10, the multiple heating substrate 3g, the plurality of semiconductor chips 1, and the plurality of semiconductor chips 1 are directly heated by the second heating stage 10b. This is a thermocompression bonding.

  That is, in the second head 10a of the present embodiment, when performing the main pressure bonding, a large number of low loads are applied to the substrate 3g until the plurality of pressure blocks 10n come into contact with the product. The initial set load is picked up and applied to the substrate 3g and the semiconductor chip 1 respectively.

  Thereby, at the time of head landing at the time of the main pressure bonding, it is possible to prevent the product from being damaged by the impact of the pressure block 10n on the product.

  Note that the pressurization by the second head 10a in the second crimping section 10 pressurizes the semiconductor chip 1 for a longer time than the pressurization in the first heating stage 9b.

  For example, the pressurization time at the first heating stage 9b is about 0.1 second, while the pressurization time at the second heating stage 10b is about 4 seconds.

  Accordingly, since the second heating stage 10b can be pressurized for a relatively long time, the heating temperature of the product can be set lower than in the conventional die bonding method.

  FIG. 13 shows a modification of the chip mounting method shown in FIG. 12, in which the multi-chip substrate 3g and the semiconductor chip 1 temporarily bonded by the first heating stage 9b are arranged on the second heating stage 10b (FIG. 13). After A) of 13, the second head 10 a is lowered and a plurality of pressure blocks 10 n are picked up and brought into contact with the substrate 3 g (B in FIG. 13). Thereafter, the second heating stage 10b is raised, and the multiple substrate 3g and the semiconductor chip 1 are sandwiched between the plurality of pressure blocks 10n and the second heating stage 10b (C in FIG. 13). Similar to the chip mounting method shown in FIG.

  Thereafter, similarly to the chip mounting method shown in FIG. 12, high-pressure (second pressure) air larger than the low-pressure (first pressure) is supplied from the air supply system 10q of the block body 10d to the space 10p. Then, it is applied to the plurality of pressure blocks 10n, and the main pressure bonding is performed in this state (D in FIG. 13).

  When performing the main pressure bonding in the second pressure bonding section 10, the semiconductor chip 1 disposed on the lower side of the multi-piece substrate 3g is subjected to the second heating from the back surface (second main surface) 1c side. The substrate 10g is heated directly on the stage 10b without interposing the substrate, and the multi-piece substrate 3g is passed through the support block portion 10m and the pressure block 10n by the heater 10c in the block main body portion 10d disposed above the substrate 10g. Heat. As a result, the multi-chip substrate 3g and the joint portions of the respective semiconductor chips 1 are heated from the upper and lower sides and thermocompression bonded.

  That is, the semiconductor chip 1 is heated from the second heating stage 10b side, and the multi-piece substrate 3g is further heated from the opposite side of the second heating stage 10b with the multi-piece substrate 3g interposed therebetween for thermocompression bonding. Do.

  At that time, the semiconductor chip side is heated at a higher temperature than the substrate side. For example, since the semiconductor chip 1 is silicon and has a relatively good thermal conductivity, the semiconductor chip side is heated at about 200 ° C. On the other hand, the multi-cavity substrate 3g is mainly made of an insulating member, and therefore has a low thermal conductivity, and is likely to cause thermal deformation and wiring disconnection. The temperature is set to 100 ° C. or lower, preferably 50 ° C. or lower, and optimally normal temperature.

  Here, an example of the structure of the multi-cavity substrate 3g (organic substrate 3) will be described. An organic resin member that is a base material constituting the main part is made of, for example, BT resin (bismaleimide / triazine resin). A wiring layer made of copper is formed on both the front and back surfaces of the organic resin member, and a solder resist film that is an organic insulating film (organic layer) is formed on the surface of a predetermined region of each wiring layer. Yes. Therefore, the multi-chip substrate 3g (organic substrate 3) in this case is a multilayer wiring board having two wiring layers.

  In addition, the glass transition temperature (Tg) of BT resin is 240-330 degreeC, for example, Therefore, the heating temperature from the back surface 1c side of the semiconductor chip 1 on the 2nd heating stage 10b in this case (200 degreeC) Is lower than the glass transition temperature (240 to 330 ° C.) of the BT resin, and can prevent the occurrence of defects due to heat such as thermal deformation of the substrate.

  Further, the rigidity of the solder resist film is lower than that of the BT resin that is the organic resin member. Therefore, the rigidity of the bonding between the semiconductor chip 1 and the multi-chip substrate 3g (organic substrate 3) is lower than that of the BT resin. Since it is performed through the solder resist film which is an organic layer, the adhesion between the semiconductor chip 1 and the substrate can be increased.

  The structure of the multi-piece substrate 3g is not limited to the above structure, and may be, for example, a multilayer wiring board having two or more wiring layers, and an organic material constituting the main part. The resin member may be a resin other than the BT resin.

  Further, the bonding between the semiconductor chip 1 and the adhesive such as the die bond tape 2 is the bonding between the surface which is the main surface 1b of the semiconductor chip 1 and the adhesive. For example, a protective film is formed on the surface of the semiconductor chip 1. If this is the case, the protective film and the adhesive are bonded, that is, thermocompression bonded.

  Next, FIG. 14 shows the landing detection of the pressure block 10n at the tip of the second head 10a.

  When performing the landing detection, first, with no product placed on the second heating stage 10b, a plurality of pressure blocks 10n supported by the support block 10m so as to be independently movable are applied. A high pressure that does not allow the pressure block 10n to be pushed up is applied from the air supply system 10q of the block main body 10d. That is, a high pressure is applied to the pressure block 10n so that the pressure block 10n cannot be pushed up under a normal load.

  In this state, the second heating stage 10b is raised to bring the plurality of pressure blocks 10n into contact with the second heating stage 10b. Further, the motor 10g is driven to lower the height control plate 10f, and the position where the load cell 10e shows a change is the initial height of the pressure block 10n. By using this method, the landing height of the pressure block 10n can be obtained.

  Furthermore, in a state where the product is placed on the second heating stage 10b, the pressure applied to the pressure block 10n is gradually increased from the low pressure, and the change point of the load applied to the load cell 10e is detected, The magnitude of the pressure applied to the plurality of semiconductor chips 1 can be obtained. That is, it is possible to determine how much load is applied to the semiconductor chip 1 during the actual press-bonding of the semiconductor chip 1.

  Next, FIG. 15 shows detection of a set load.

  The set load is detected in a state in which a product is not placed on the second heating stage 10b, and first, the second heating stage 10b is raised while a low pressure is applied to the pressure block 10n, and a plurality of pressures are applied. The block 10n is brought into contact with the second heating stage 10b. That is, the pressure block 10n is landed with a small pressure. In this state, the height control plate 10f is lowered by a certain amount by driving the motor 10g, and the load cell 10e is pushed in.

  Thereafter, by gradually increasing the pressure applied to the plurality of pressurizing blocks 10n and detecting the change point of the load applied to the load cell 10e, the plurality of semiconductor chips 1 are arranged on the second heating stage 10b and thermocompression bonded. The magnitude of the set value of the pressure to be applied to the plurality of pressure blocks 10n at the time of (final pressure bonding) can be obtained.

  Thereby, the magnitude | size of the setting load at the time of carrying out the thermocompression bonding of the several semiconductor chip 1 simultaneously can be detected only by the chip mounter 8. FIG.

  The chip mounter 8 stores the set air pressure in the chip mounter 8 after detecting the set load when the load is reached.

  Next, FIG. 16 is a diagram illustrating a method for exchanging tools.

  That is, in the chip mounter 8 of the present embodiment, in the second head 10a, a support block portion 10m (also referred to as a tool) that supports a plurality of pressure blocks 10n is provided detachably with respect to the block main body portion 10d. By removing and replacing only the support block portion 10m (only the tool), it becomes possible to easily cope with a change in product type. The change depends on, for example, the number of semiconductor chips 1, the chip size, or the load.

  Next, FIG. 17 shows the absorption of variation in the magnitude of the load applied to the pressure block 10n and the height of the pressure block 10n. The magnitude of the load applied to each pressure block 10n is shown in FIG. P × pressure receiving area S. Further, at low pressure, the elastic membrane 10t is deformed so as to follow the shape of the head of the pressure block 10n, thereby absorbing the height error of the pressure block 10n and then adjusting to the set pressure. As a result, it is possible to absorb variations in the height of each pressure block 10n.

  Next, FIG. 18 shows prevention of generation of silicon waste (foreign matter) and prevention of sandwiching of waste in the second heating stage 10b.

  That is, the second heating stage 10b is provided with a plurality of small stages 10j each having a smaller surface than the back surface (second main surface) 1c of the semiconductor chip 1 on the stage surface. As a result, even when each semiconductor chip 1 is placed on each small stage 10j, the end of the back surface 1c of the semiconductor chip 1 does not contact the small stage 10j, so that the chipping starting point by dicing of the semiconductor chip 1 can be obtained. Therefore, generation of silicon scraps can be prevented.

  Further, the second heating stage 10b is provided with a plurality of suction systems 10k that open to the surface on the chip arrangement side, and the chip is formed during the thermocompression bonding of the semiconductor chip 1 and the multi-chip substrate 3g by the main pressure bonding. Foreign matters such as silicon scraps dropped on the surface on the arrangement side can be sucked and removed through the suction system 10k.

  That is, even when foreign matter such as silicon dust is generated, it can be removed from the suction system 10k, and thus foreign matter can be prevented from being caught between the semiconductor chip 1 and the stage.

  Next, FIG. 19 shows an external structure in which the support block portion 10m is attached to the block main body portion 10d, and it is slid into the lower portion of the block main body portion 10d as shown in FIG. Fix it.

  As shown in FIG. 21, the support block portion 10m is formed in a concave shape, and the number of through holes 10x corresponding to the pressure block 10n to be arranged is formed at the bottom thereof. As shown in FIG. 22, each pressure block 10n has a convex shape and serves as a plunger. Thereby, the convex part of each pressure block 10n is arrange | positioned in each through-hole 10x of the bottom part of the support block part 10m. When assembled in this way, the tip of each pressure block 10n slightly protrudes from the support block 10m with the tip directed downward.

  Further, in the support block portion 10m, as shown in FIG. 21, a thin plate-like elastic film 10t is arranged on the pressure block 10n, and then a frame-like elastic spacer 10s is arranged on the elastic film 10t. Then, the frame-shaped metal spacer 10r is arranged on the uppermost stage.

  Further, as shown in FIG. 22, the support block 10m is detachably attached to the block body 10d.

  The frame-like elastic spacer 10s is made of, for example, fluorine rubber, and seals the space 10p to prevent vacuum leakage. Furthermore, the load on the peripheral edge of the plurality of pressure blocks 10n can be stabilized by the elastic force of the elastic spacer 10s.

  Further, the metal spacer 10r is formed of, for example, stainless steel and prevents the elastic spacer 10s from sticking to the block main body portion 10d, and preventing the sticking or sticking to the block main body portion 10d. Easy to attach and detach. That is, the support block portion 10m is detachably attached to the block main body portion 10d via the metal spacer 10r.

  The elastic film 10t is a sheet-like member formed of, for example, fluorine rubber and having a thickness of about 0.5 mm. This elastic film 10t pressurizes the heads of the plurality of pressure blocks 10n at a time when air pressure is applied to the space 10p, but is an extremely thin member. It can move following the vertical movement of the pressure block 10n.

  Further, as shown in FIG. 22, an air supply system 10q communicating with the space 10p is formed in the block main body 10d to which the support block 10m is attached, and this air supply is supplied to the block main body 10d. A relay pipe (air intake part) 10u for taking in air is attached to the system 10q. A hose 10v is connected to the relay pipe 10u, and air at the time of pressurization is sent to the air supply system 10q through the hose 10v and the relay pipe 10u.

  Therefore, it is preferable that the relay pipe 10u is long enough not to transfer heat to the hose 10v. That is, if the relay pipe 10u is short, heat is transferred to the hose 10v and the hose 10v expands, and the amount of air changes. Therefore, the relay pipe 10u is lengthened so that the amount of supplied air does not change. It is desirable to increase heat resistance.

  FIG. 23 shows various structures for stabilizing the load in the support block portion 10m. The structure in which the elastic film 10t is thinned by reducing the thickness of the seal to increase the responsiveness of the elastic film 10t. A structure in which the elastic membrane 10t is a diaphragm type with a reduced thickness, a structure in which a gap is provided between adjacent pressure blocks 10n due to expansion between plunger pitches, and between the pressure blocks 10n of the elastic membrane 10t by a seal buffer mechanism A structure is shown in which a corresponding portion is provided with a bend and less affected by the operation of the adjacent pressure block 10n.

  In the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, in die bonding in which the semiconductor chip 1 is bonded to the multi-chip substrate 3g, the die bonding is divided into the first heating stage 9b and the second heating stage 10b. Then, temporary bonding (temporary pressure bonding) is performed in the first heating stage 9b in a short time, and then the second heating stage 10b is moved to perform main bonding (final pressure bonding) of a plurality of semiconductor chips 1 at once. The bonding time can be shortened.

  Thereby, the throughput of die bonding can be improved and the productivity can be improved.

  In addition, since the second heating stage 10b can be pressurized for a relatively long time, the heating temperature can be set lower than that of the conventional die bonding method.

  As a result, when the multi-piece substrate 3g is an organic substrate having the wiring 3d, deformation such as warpage of the organic substrate can be reduced, and occurrence of defects such as peeling of the wiring pattern can be reduced. be able to.

  That is, in an organic substrate, the thermal expansion coefficient of the solder resist film, which is an insulating film (organic layer) on the substrate surface, and the copper wiring are greatly different. When the heating temperature is high, the difference in the thermal expansion coefficient is caused. Although peeling of the wiring pattern and substrate deformation are likely to occur, in this embodiment, since the heating temperature can be set low, the occurrence of the defect of the organic substrate can be reduced. Furthermore, since the deformation of the substrate can be reduced, the adhesive force between the substrate and the semiconductor chip 1 can be stabilized.

  Further, in the conventional bonding of the wiring substrate and the semiconductor chip 1 by flip chip connection, the semiconductor chip 1 is picked up from the semiconductor wafer, and the semiconductor chip 1 is arranged on the substrate with the main surface 1b of the semiconductor chip 1 facing the substrate side. Thereafter, the semiconductor chip 1 and the wiring substrate are joined by thermocompression bonding or the like, and in this case, a mechanism for transporting the semiconductor chip 1 onto the substrate is disposed on the upper side of the wiring substrate. Furthermore, the heating mechanism in this case is difficult to place on the upper side of the wiring board because the transport mechanism is placed on the upper side of the board, and is embedded in the lower stage of the wiring board. If the heating is performed from above, the bonding portion between the chip and the substrate is heated via the wiring substrate, so that the temperature of the bonding portion does not rise sufficiently and a bonding failure occurs. Furthermore, if the heating temperature is increased so as to obtain a sufficient temperature at the joint, deformation such as warping or peeling of the crimping part occurs in the wiring board.

  In comparison, in the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, the semiconductor chip 1 is arranged on the stage with its main surface 1b facing upward at the time of die bonding, and above the semiconductor chip 1. Since the multi-chip substrate 3g is arranged and bonded together, the back surface 1c of the semiconductor chip 1 can be directly heated without interposing the substrate, and the chip can be efficiently heated.

  As a result, the junction between the semiconductor chip 1 and the multi-chip substrate 3g, which is a wiring board, can be sufficiently heated, and the heating temperature from the substrate side can be set lower than that on the chip side.

  Thereby, the thermal deformation of the wiring board can be reduced.

  Furthermore, since the junction between the semiconductor chip 1 and the wiring substrate can be sufficiently heated, the junction of the semiconductor chip 1 can be stabilized. As a result, it is possible to prevent the occurrence of defects such as peeling of the bonded portion (crimped portion), to stabilize the bonding quality of the semiconductor chip 1 and to improve the reliability of the product.

  Further, when using the semiconductor chip 1 thinned by thinning the semiconductor integrated circuit device such as the BOC 7, a chip front / back reversing mechanism is required for joining the wiring substrate and the semiconductor chip 1 by the conventional flip chip connection. As a result, it becomes difficult to handle the thinned chip, and problems are likely to occur when the chip is turned upside down.

  In contrast, in the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, the semiconductor chip 1 is placed on the stage with the main surface 1b facing upward without using the front / back reversing mechanism. The structure of the semiconductor manufacturing apparatus can be simplified as much as it becomes unnecessary, and direct heating without interposing the substrate from the back surface 1c side of the semiconductor chip 1 on the stage is performed, so that the semiconductor chip 1 becomes thinner as the semiconductor chip 1 becomes thinner. And the wiring substrate can be heated more efficiently.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the BOC 7 is described as an example of the semiconductor integrated circuit device. However, the semiconductor device uses a substrate such as a multi-chip substrate 3g and bonds the substrate and the semiconductor chip 1 together. The semiconductor device is not limited to the BOC 7 as long as it can be assembled, and may be another semiconductor device such as a LOC (Lead On Chip) 20 as shown in FIG.

  The LOC 20 is obtained by bonding the inner lead 20a and the semiconductor chip 1 via the die bond tape 2, and the inner lead 20a and the semiconductor chip 1 are electrically connected by the wire 4 across the bus bar lead 20c. . Further, the outer lead 20b is formed in a gull wing shape.

  In assembling the LOC 20, when the lead frame (substrate) having the inner leads 20a and the outer leads 20b and the semiconductor chip 1 are joined, the manufacturing method of the semiconductor integrated circuit device of the present embodiment is applied.

  The present invention is suitable for a technique for manufacturing a semiconductor integrated circuit device for bonding a substrate and a semiconductor chip.

It is a perspective view which shows an example of the structure by the side of the external terminal of the semiconductor integrated circuit device of embodiment of this invention. FIG. 2 is a perspective view showing an example of an internal structure on the chip side of the semiconductor integrated circuit device shown in FIG. 1 through a sealing body. FIG. 2 is a cross-sectional view showing an example of the structure of the semiconductor integrated circuit device shown in FIG. 1. FIG. 7 is a manufacturing process flow chart showing an example of an assembly procedure of the semiconductor integrated circuit device shown in FIG. 1. It is a top view which shows an example of the structure of the surface side of the wiring board in the assembly shown in FIG. It is a top view which shows an example of the structure of the back surface side of the wiring board in the assembly shown in FIG. FIG. 5 is a plan view showing an example of the structure on the back side of the wiring board after die bonding in the assembly shown in FIG. 4. It is a top view which shows an example of schematic structure of the semiconductor manufacturing apparatus of embodiment of this invention. It is sectional drawing which shows an example of the structure of the principal part of the semiconductor manufacturing apparatus shown in FIG. It is a perspective view which shows an example of the structure of the principal part of the semiconductor manufacturing apparatus shown in FIG. It is sectional drawing which shows an example of the structure by the side of the 2nd heating stage of the principal part shown in FIG. It is sectional drawing which shows an example of the operation | movement flow at the time of the low load landing of the principal part shown in FIG. It is sectional drawing which shows the operation | movement flow at the time of the low load landing of the modification of the principal part shown in FIG. It is sectional drawing which shows an example of the structure at the time of the landing detection of the principal part shown in FIG. It is sectional drawing which shows an example of the structure at the time of the load setting of the principal part shown in FIG. It is sectional drawing which shows an example of the structure at the time of the kind change of the principal part shown in FIG. It is sectional drawing which shows an example of the elastic body contact | adherence state in the principal part shown in FIG. It is sectional drawing which shows an example of the foreign material suction state in the principal part shown in FIG. It is a perspective view which shows an example of the structure of the support block part attachment state in the principal part shown in FIG. It is a perspective view which shows an example of the attachment method of the support block part shown in FIG. It is a perspective view which shows an example of a structure of the internal component of the support block part shown in FIG. It is sectional drawing which shows an example of the structure of the support block part shown in FIG. It is sectional drawing which shows the structure of the various modifications of the support block part shown in FIG. It is sectional drawing which shows the structure of the semiconductor integrated circuit device of the modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Pad 1b Main surface 1c Back surface 2 Die-bonding tape 3 Organic substrate (substrate)
3a Front surface 3b Back surface 3c Bonding electrode 3d Wiring 3e Opening 3f Bump land 3g Multi-layer substrate (substrate)
3h Device area 4 Wire 5 Solder ball 6 Sealing body 7 BOC (semiconductor integrated circuit device)
8 Chip mounter 9 First pressure bonding portion 9a First head 9b First heating stage 9c Heater (heating means)
9d Block main body (main body)
9e Inclination adjusting mechanism 9f Support block 9g Pressure block 9h XY stage 10 Second crimping part 10a Second head 10b Second heating stage 10c Heater (heating means)
10d Block body (main body)
10e Load cell (Load change detection means)
10f Height control plate 10g Motor 10h Load cell support portion 10i Tilt adjusting mechanism portion 10j Small stage 10k Suction system 10m Support block portion 10n Pressure block 10p Air space 10q Air supply system 10r Metal spacer 10s Elastic spacer 10t Elastic film 10u Relay pipe (Air intake part)
10v Hose 10w Fixing screw 10x Through hole 11 Stocker 12 Guide rail 13 Handler 14 Pre-bake part 15 Load port 16 Unloading robot 17 Wafer stage 18 Pick-up part 19 Product unloader 20 LOC (semiconductor integrated circuit device)
20a Inner lead 20b Outer lead 20c Bus bar lead

Claims (8)

(A) preparing an organic wiring substrate having a plurality of device formation regions and having a base substrate made of an organic material;
(B) preparing a plurality of semiconductor chips having a main surface on which an integrated circuit is formed and a back surface opposite to the main surface;
(C) temporarily bonding the plurality of semiconductor chips to the plurality of device formation regions of the organic wiring board with an adhesive so that the main surface side of the plurality of semiconductor chips faces the organic wiring board;
(D) placing the organic wiring board on which the plurality of semiconductor chips are temporarily bonded on the heating stage such that the back surfaces of the plurality of semiconductor chips are in contact with the heating stage;
(E) The plurality of semiconductor chips are heated at a first temperature by the heating stage, and the organic wiring board is heated at a second temperature by a heating jig disposed above the organic wiring board. A step of permanently bonding the plurality of semiconductor chips to the device formation region of the organic wiring substrate with the adhesive.
The method of manufacturing a semiconductor integrated circuit device, wherein the second temperature by the heating jig is lower than the first temperature by the heating stage.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the heating jig has a pressurizing mechanism, and the step (e) moves the organic wiring board in the direction of the plurality of semiconductor chips by the heating jig. A method of manufacturing a semiconductor integrated circuit device, wherein the plurality of semiconductor chips are thermocompression-bonded to the device formation region of the organic wiring substrate by applying pressure.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second temperature is 150 [deg.] C. or lower.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second temperature is 100 [deg.] C. or less.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second temperature is 50 [deg.] C. or lower.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the first temperature is lower than a glass transition temperature of a base substrate of the organic wiring substrate.   7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the first temperature is about 200.degree. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the organic wiring board in the step (a) includes the adhesive supplied to each of the plurality of device formation regions.
The temporary bonding in the step (c) is individually applied to the plurality of semiconductor chips, and the main bonding in the step (e) is collectively applied to the plurality of semiconductor chips. A method of manufacturing a semiconductor integrated circuit device.

Images