JP2008288292A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor storage device having a structure minimally suppressing the performance degradation of a phase-change memory or the like having a phase-change film and an interface film and a manufacturing method for the semiconductor storage device. <P>SOLUTION: In the semiconductor storage device, an anisotropic etching gas 33 for obtaining a phase-change memory element M1 is operated under a condition having an etching rate to the interface film 7 lower than a GST film 23 and an upper electrode 24. Consequently, the interface film 7 can be patterned so as to contain the whole plane shape of the GST film 23 as the phase-change film and be made wider than the plane shape of the GST film 23. The interface film 7 is not made smaller than the plane shapes of the GST film 23 and the upper electrode 24 in dimensions even when the side wall of the interface film 7 is etched and retreated more or less by a post-process by finishing the plane shape of the interface film 7 in a size wider than that of the GST film 23, and a recess is not generated as seen in a conventional manufacturing method. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having phase change memory cells (elements) formed using a phase change material such as chalcogenide. It is.

  13 to 16 are cross-sectional views illustrating a conventional method of manufacturing a phase change memory. An example of the phase change memory is the phase change memory disclosed in Patent Document 1. Hereinafter, a conventional method of manufacturing a phase change memory will be described with reference to these drawings.

First, as shown in FIG. 13, the selection transistor Q <b> 1 is formed on the main surface of the semiconductor substrate 11. The selection transistor Q1 can be obtained by the same method as the conventional transistor formation method. Next, after an interlayer insulating film IF1 made of SiO ₂ or the like is formed on the entire surface including the selection transistor Q1, the surface of the interlayer insulating film IF1 is flattened by CMP processing or the like. Thereafter, a contact hole 18 penetrating the interlayer insulating film IF1 is selectively formed, and an opening is formed on the silicide region 17 of one source / drain region 14 of the selection transistor Q1.

  Next, as shown in FIG. 14, a film is formed so as to bury W (tungsten) in the contact hole 18. At this time, even if a barrier metal is formed before the formation of W so that Ta (tantalum), Ti (titanium), or a nitride film thereof is formed between the W film and the source / drain regions 14. Good.

  After that, as shown in FIG. 14, the W film is polished by CMP or the like, so that tungsten is left only in the contact hole 18 to obtain the tungsten plug WP1. Furthermore, it is characterized by comprising at least one selected from Ti oxide film, Zr oxide film, Hf oxide film, Ta oxide film, Nb oxide film, Cr oxide film, Mo oxide film, W oxide film, and Al oxide film. An interface film 27 having a thickness of 0.5 nm or more and 5 nm or less is formed using the insulating interface film. As the interface film 27, a semiconductor interface film made of amorphous silicon or a conductive metal interface film may be formed instead of the insulating interface film. The interface film 27 having the above composition also works effectively as an adhesion film that improves the adhesion between the interlayer insulating film IF1 and the GST film 23.

Further, as shown in FIG. 14, a GST film 23 having a composition such as Ge ₂ Sb ₂ Te _{5 is formed} . Next, the upper electrode 24 is formed on the GST film 23. Next, a resist 26 patterned by photolithography or the like is formed on the upper electrode 24 so as to leave only the upper electrode 24, the GST film 23, and the interface film 27 located immediately above the tungsten plug WP1.

  Thereafter, as shown in FIG. 15, the interface film 27, the GST film 23, and the upper electrode 24 are patterned by performing anisotropic etching using the resist 26, and the patterned interface film 27, GST film 23, and A phase change memory element M11 including the upper electrode 24 is obtained.

Further, as shown in FIG. 15, after an interlayer insulating film IF2 made of SiO ₂ or the like is formed on the entire surface, the surface of the interlayer insulating film IF2 is flattened by a CMP process or the like. Next, a contact hole that selectively penetrates the upper layer portion of the interlayer insulating film IF2 is formed, and a part of the upper electrode 24 is opened. Next, a film is formed so as to bury W in the contact hole. At this time, a barrier metal (not shown) may be formed between Ta and Ti or a nitride film thereof between W and the upper electrode 24. Next, the W film is polished by CMP or the like, leaving W only in the contact hole, and obtaining the tungsten plug WP2.

Next, as shown in FIG. 16, using an Al—Cu mixture or the like, the bit line BL1 is formed on the interlayer insulating film IF2, and is electrically connected to the tungsten plug WP2. After that, the second wiring may be used for wiring such as a peripheral circuit. Next, a plasma SiN film or a SiO ₂ film is formed as the passivation film PF1.

  Next, although not shown in the drawing, only the portions where the passivation film is to be removed, such as bonding pads and dicing lines, are opened by photolithography and dry etching. Thereafter, a polyimide film or the like may be formed.

  FIG. 17 is a plan view showing a planar structure of a memory cell 1-bit formation region including the phase change memory element M11 having the structure shown in FIG. The AA cross section of the figure corresponds to the structure of FIG.

  As shown in FIG. 17, the bit line BL1 is formed across the adjacent memory cell 1 bit formation regions 31 and 32 in plan view, and the memory cell 1 bit formation regions 31 and 32 overlap with the bit line BL1 in plan view. Field regions FR1 and FR2 of select transistors Q1 and Q2 are formed therein.

  Phase change memory element M11 is provided in a plane overlap region between bit line BL1 and field region FR1, and phase change memory element M12 is provided in a plan view overlap region between bit line BL1 and field region FR2.

  Selection transistors Q1 and Q2 are provided with tungsten plugs WP1 (WP2) in phase change memory elements M11 and M12, respectively, and gate electrodes are formed in the vertical direction in the drawing in the vicinity of the planar view edges of phase change memory elements M11 and M12. Is provided.

JP 2006-352082 A

  Since the conventional phase change memory is manufactured as described above, several process problems occur.

  In order to obtain the phase change memory element M11, a Cl-based gas and an F-based gas are generally used as anisotropic etching so that only the upper electrode 24, the GST film 23, and the interface film 27 are selectively left. It was. By using Cl-based / F-based gas, residues 29 such as Cl and F remain on the interlayer insulating film IF1 and on the side walls of the upper electrode 24, the GST film 23, and the interface film 27 (see FIG. 15). As a result, it is diffused into each film (interlayer insulating film IF1, interface film 27, GST film 23, and upper electrode 24) by a heat treatment in a later process, thereby reducing the adhesion between the interlayer insulating film IF1 and the GST film 23 and the GST. There was a problem that the film quality of the film 23 and the interface film 27 deteriorated.

  Further, in the processing after the etching, the side wall of the interface film 27 continues to be exposed, so that the interface film 27 retreats to form a recess 28 (see FIGS. 15 and 16), and the film quality of the interface film 27 is deteriorated. At the same time, there is a problem that a leak or a short circuit occurs between the GST film 23 and the tungsten plug WP1.

  Further, if a misalignment occurs when forming the pattern of the tungsten plug WP2 (see FIGS. 15 and 16), the tungsten plug WP2 and the side surface of the GST film 23 or the interface film 27 are directly shorted, and the GST film 23 and the interface film are formed. 27 film quality deterioration occurs, and as a result, there is a problem in that rewriting failure of the phase change memory element M11 occurs.

  The present invention has been made in order to solve the above-described problems, and provides a semiconductor memory device having a structure in which performance deterioration such as a phase change memory having a phase change film and an interface film is minimized, and a method for manufacturing the same. Objective.

  According to one embodiment of the present invention, a phase change memory element including an interface film, a phase change film, and an upper electrode is formed on the first interlayer insulating film. At this time, the interface film includes the entire planar shape of the phase change film and is formed in a planar shape wider than the planar shape of the phase change film.

  According to this embodiment, the interface film 7 is formed in a planar shape that includes the entire planar shape of the phase change film and is wider than the planar shape of the phase change film during patterning to obtain the phase change memory element. Therefore, even if the side wall portion of the interface film is slightly retracted due to subsequent etching or the like, the formation of a recess in the interface film between the phase change film and the first interlayer insulating film is surely avoided. Can do. As a result, it is possible to reliably avoid a leak or short circuit between the phase change film and the first plug, so that it is possible to obtain a phase change memory having a structure in which performance degradation is minimized.

<Embodiment 1>
The first embodiment corresponds to a semiconductor memory device in which the influence of residual Cl and F after anisotropic etching for obtaining a phase change memory element structure is avoided and a manufacturing method thereof.

  1 to 6 are sectional views showing a method of manufacturing a phase change memory according to the first embodiment of the present invention. Hereinafter, the manufacturing method will be described with reference to these drawings.

First, as shown in FIG. 1, the selection transistor Q <b> 1 is formed on the main surface of the semiconductor substrate 11. The selection transistor Q1 can be obtained by the same method as the conventional transistor formation method. Next, after an interlayer insulating film IF1 (first interlayer insulating film) made of SiO ₂ or the like is formed on the entire surface including the selection transistor Q1, the surface of the interlayer insulating film IF1 is flattened by CMP processing or the like. Thereafter, a contact hole 18 penetrating the interlayer insulating film IF1 is selectively formed, and an opening is formed on the silicide region 17 of one source / drain region 14 of the selection transistor Q1.

  Next, as shown in FIG. 2, a film is formed so as to bury W in the contact hole 18. At this time, a barrier metal may be formed before forming W so that Ta, Ti, or a nitride film thereof may be formed between the W film and the source / drain regions 14.

  Thereafter, as shown in FIG. 2, the tungsten film WP1 (first plug) is obtained by polishing the W film by CMP or the like, leaving W only in the contact hole 18. Furthermore, it is characterized by comprising at least one selected from Ti oxide film, Zr oxide film, Hf oxide film, Ta oxide film, Nb oxide film, Cr oxide film, Mo oxide film, W oxide film, and Al oxide film. An interface film 7 having a thickness of 0.5 nm or more and 5 nm or less is formed using the insulating interface film. As the interface film 7, a semiconductor interface film made of amorphous silicon or a conductive metal interface film may be formed instead of the insulating interface film. The interface film 7 having the above composition works effectively as an adhesion film for improving the adhesion between the interlayer insulating film IF1 and the GST film 23.

Further, as shown in FIG. 2, a GST film 23 having a composition such as Ge ₂ Sb ₂ Te _{5 is formed} . Next, the upper electrode 24 is formed on the GST film 23. Next, a resist 26 patterned by photolithography or the like is formed on the upper electrode 24 so as to selectively leave only the upper electrode 24, the GST film 23, and the interface film 7 located immediately above the tungsten plug WP1.

  Thereafter, as shown in FIG. 3, the interface film 7, the GST film 23, and the upper electrode 24 are patterned by performing an anisotropic etching process using an anisotropic etching gas 33 using a resist 26, and the patterning is performed. A phase change memory element M1 (GST pattern) including the interface film 7, the GST film 23, and the upper electrode 24 is obtained. For example, the phase change memory element M1 patterned into a substantially square planar shape having a side of 0.35 μm is obtained.

  The anisotropic etching gas 33 is performed under the condition that the etching rate with respect to the interface film 7 is lower than that of the GST film 23 and the upper electrode 24. As a result, the interface film 7 can be patterned so as to include the entire planar shape of the GST film 23 that is a phase change film and to be wider than the planar shape of the GST film 23. For example, the interface film 7 is patterned so as to protrude about 30 nm from the GST film 23 in plan view.

  During the etching with the anisotropic etching gas 33, residues 29 such as Cl and F remain on the interlayer insulating film IF1 and on the side walls of the upper electrode 24, the GST film 23, and the interface film 27.

  However, in the first embodiment, by finishing the planar shape of the interface film 7 wider than the planar shape of the GST film 23, even if the side wall of the interface film 7 is etched and recedes somewhat in a later process, The dimension is not smaller than the planar shape of the electrode 24, and no dent is generated unlike the conventional manufacturing method.

Next, as shown in FIG. 4, after removing the resist 26, a cleaning process is performed on the residual material 29 such as residual Cl and F using the cleaning material 34, so that Cl and F are contained on the interlayer insulating film IF <b> 1. The concentration is reduced to a concentration of about 10 × ¹¹ to 10 × ⁹ atom / cm ² . That is, the concentration of Cl and F on the interlayer insulating film IF1 before the Cl-based / F-based etching by the anisotropic etching gas 33 is reduced.

  In order to realize the above-described reduction in the Cl and F content concentration, pure water or the like can be considered as the cleaning material 34. That is, it is desirable to perform a cleaning process using a pure water.

Further, as shown in FIG. 5, after an interlayer insulating film IF2 (second interlayer insulating film) made of SiO ₂ or the like is formed on the entire surface, the surface of the interlayer insulating film IF2 is flattened by a CMP process or the like. Next, a contact hole that selectively penetrates the upper layer portion of the interlayer insulating film IF2 is formed, and a part of the upper electrode 24 is opened. Next, a film is formed so as to bury W in the contact hole. At this time, a barrier metal (not shown) may be formed between Ta and Ti or a nitride film thereof between W and the upper electrode 24. Next, the W film is polished by CMP or the like, leaving W only in the contact hole, and obtaining the tungsten plug WP2.

Next, as shown in FIG. 6, using an Al—Cu mixture or the like, the bit line BL1 is formed on the interlayer insulating film IF2, and is electrically connected to the tungsten plug WP2. After that, the second wiring may be used for wiring such as a peripheral circuit. Next, a plasma SiN film or a SiO ₂ film is formed as the passivation film PF1.

  Next, although not shown in the drawing, only the portions where the passivation film is to be removed, such as bonding pads and dicing lines, are opened by photolithography and dry etching. Thereafter, a polyimide film or the like may be formed.

  As described above, the interface film 7 of the phase change memory according to the first embodiment includes the entire planar shape of the GST film 23 in the patterning for obtaining the phase change memory element M1, and more than the planar shape of the phase change film. Since it is formed in a wide planar shape, a dent of the interface film 7 is formed between the GST film 23 and the interlayer insulating film IF1 even if the side wall portion of the interface film 7 is somewhat receded by etching or the like in a later process. Can be reliably avoided. As a result, it is possible to avoid a leak or a short circuit between the GST film 23 and the first W plug, so that it is possible to obtain a phase change memory having a structure in which performance degradation is minimized.

  Further, by the cleaning process using the cleaning material 34 according to the method of manufacturing the phase change memory of the first embodiment, the surface of the interlayer insulating film IF1 directly under the GST film 23, the residual F, Cl, etc. in the GST film 23 / interface film 7 By effectively removing the residual material 29, it is possible to improve the adhesion of the interface film 7 and the GST film 23 to the base, and to stabilize the device characteristics.

  In addition, by selecting a water washing process or the like as a cleaning material for the residue 29 such as residual F and Cl, Cl and F on the interlayer insulating film IF1 before the Cl-based / F-based etching by the anisotropic etching gas 33 is performed. Therefore, the device characteristics can be further stabilized.

More specifically, the concentration of Cl and F on the interlayer insulating film IF1 is reduced to a concentration of about 10 × ¹¹ to 10 × ⁹ atoms / cm ^2, so that the device characteristics can be stabilized with high accuracy. be able to.

<Embodiment 2>
In the method of manufacturing the phase change memory according to the second embodiment, the tungsten plug, the GST film, and the interface film are directly connected to each other even when an overlay shift occurs during the formation of the tungsten plug pattern for connecting the upper electrode of the phase change memory element. A semiconductor memory device having a structure that is not short-circuited and a method for manufacturing the same.

  7 to 12 are sectional views showing a method of manufacturing a phase change memory according to the second embodiment of the present invention. Hereinafter, the manufacturing method of the second embodiment will be described with reference to these drawings.

  First, as shown in FIG. 7, as in FIG. 1 of the first embodiment, the select transistor Q1, the interlayer insulating film IF1, and the contact hole 18 are formed in the main surface of the semiconductor substrate 11.

  Next, as shown in FIG. 8, a film is formed so as to bury W in the contact hole 18 as in FIG. 2 of the first embodiment. Thereafter, the W film is polished by CMP or the like to leave the W only in the contact hole 18 to obtain the tungsten plug WP1.

Furthermore, it is characterized by comprising at least one selected from Ti oxide film, Zr oxide film, Hf oxide film, Ta oxide film, Nb oxide film, Cr oxide film, Mo oxide film, W oxide film, and Al oxide film. An interface film 27 having a thickness of 0.5 nm or more and 5 nm or less is formed using the insulating interface film. As the interface film 7, a semiconductor interface film made of amorphous silicon or a conductive metal interface film may be formed instead of the insulating interface film. Thereafter, a GST film 23 having a composition such as Ge ₂ Sb ₂ Te _{5 is formed} . Next, the upper electrode 24 is formed on the GST film 23. Next, a resist 26 patterned by photolithography or the like is formed on the upper electrode 24 so as to selectively leave only the upper electrode 24, the GST film 23, and the interface film 27 located immediately above the tungsten plug WP1.

  Thereafter, as shown in FIG. 9, by performing anisotropic etching using a resist 26, the interface film 27, the GST film 23, and the upper electrode 24 are patterned, and the patterned interface film 27, GST film 23, and A phase change memory element M2 (GST pattern) composed of the upper electrode 24 is obtained. At this time, a residue 29 is generated as in the first embodiment (see FIG. 3), but the illustration is omitted.

  Further, as shown in FIG. 9, a silicon nitride film 3 such as a plasma SiN film is formed on the entire surface. Although not shown in FIG. 9, it is desirable to remove the residue 29 by washing with a cleaning material 34 before the formation of the silicon nitride film 3 as in the step shown in FIG. 4 of the first embodiment.

  Next, as shown in FIG. 10, the entire surface of the silicon nitride film 3 is etched back using an anisotropic etching gas 35, whereby the phase change memory element M <b> 2 (upper electrode 24, GST film 23, interface film 27). Side walls 4 are formed on the side wall portions.

Next, as shown in FIG. 11, after an interlayer insulating film IF2 made of SiO ₂ or the like is formed on the entire surface, the surface of the interlayer insulating film IF2 is flattened by CMP processing or the like. Next, a contact hole that selectively penetrates the upper layer portion of the interlayer insulating film IF2 is formed by etching, and a part on the upper electrode 24 is opened.

At this time, considering that the sidewall 4 is made of SiN and is made of SiO ₂ which is a material for forming the interlayer insulating film IF2, the selection ratio of SiO ₂ to SiN satisfies about 10 to 10 ^4. By performing the etching process to be performed, it is possible to reliably avoid the side wall 4 from being removed by etching when the interlayer insulating film IF2 is penetrated.

  Next, as shown in FIG. 11, a film is formed so as to bury W in the contact hole. At this time, a barrier metal (not shown) may be formed between Ta and Ti or a nitride film thereof between W and the upper electrode 24. Next, the W film is polished by CMP or the like, leaving W only in the contact hole, and obtaining the tungsten plug WP2.

Next, as shown in FIG. 12, using an Al—Cu mixture or the like, the bit line BL1 is formed on the interlayer insulating film IF2, and is electrically connected to the tungsten plug WP2. After that, the second wiring may be used for wiring such as a peripheral circuit. Next, a plasma SiN film or a SiO ₂ film is formed as the passivation film PF1.

  Next, although not shown in the drawing, only the portions where the passivation film is to be removed, such as bonding pads and dicing lines, are opened by photolithography and dry etching. Thereafter, a polyimide film or the like may be formed.

  As described above, in the method of manufacturing the phase change memory according to the second embodiment, the sidewall 4 is formed on the sidewall of the phase change memory element M2 (upper electrode 24, GST film 23, interface film 27).

  For this reason, even when a misalignment occurs at the time of pattern formation of the tungsten plug WP2 formed for electrical connection with the upper electrode 24, the sidewall 4 causes the side surface of the tungsten plug WP2 on the side of the GST film 23 / interface film 27. Never formed. As a result, the tungsten plug WP2 is electrically connected to the GST film 23 and the interface film 27, thereby reliably avoiding deterioration of the quality of the GST film 23 and the interface film 27 and occurrence of a rewrite failure in the phase change memory element M2. The effect which can be done is produced. As a result, it is possible to obtain a phase change memory having a structure in which performance degradation is minimized.

Further, the process of penetrating the interlayer insulating film IF2 for the tungsten plug WP2 is an etching process in which the selection ratio of the interlayer insulating film IF2 to the sidewall 4 satisfies about 10 to 10 ⁴ as described above. For this reason, it is possible to reliably avoid etching away the sidewalls 4 when penetrating through the interlayer insulating film IF2, so that the problems associated with electrical connection to the GST film 23 and the interface film 27 of the tungsten plug WP2 described above can be avoided. It can be avoided reliably.

It is sectional drawing which shows the manufacturing method of the phase change memory which is Embodiment 1 of this invention. FIG. 6 is a cross-sectional view showing the method for manufacturing the phase change memory according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the phase change memory according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the phase change memory according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the phase change memory according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the phase change memory according to the first embodiment. It is sectional drawing which shows the manufacturing method of the phase change memory which is Embodiment 2 of this invention. FIG. 11 is a cross-sectional view showing the method for manufacturing the phase change memory according to the second embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the phase change memory according to the second embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the phase change memory according to the second embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the phase change memory according to the second embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the phase change memory according to the second embodiment. It is sectional drawing which shows the manufacturing method of the conventional phase change memory. It is sectional drawing which shows the manufacturing method of the conventional phase change memory. It is sectional drawing which shows the manufacturing method of the conventional phase change memory. It is sectional drawing which shows the structure of the phase change memory which is Embodiment 2 of this invention. FIG. 17 is a plan view showing a planar structure of the phase change memory shown in FIG. 16.

Explanation of symbols

  4 sidewalls, 7, 27 interface film, 23 GST film, 24 upper electrode, 34 cleaning material, IF1, IF2 interlayer insulating film, M1, M2 phase change memory element, WP1, WP2 tungsten plug.

Claims (9)

A first interlayer insulating film formed on an upper layer of the semiconductor substrate;
A first plug having one end and the other end and selectively provided through the first interlayer insulating film;
An interface film directly formed on the one end of the plug;
A phase change film formed on the interface film without contacting the plug;
An upper electrode formed on the phase change film, and the phase change memory element is configured by the interface film, the phase change film, and the upper electrode,
The interface film includes the entire planar shape of the phase change film, and is formed in a planar shape wider than the planar shape of the phase change film,
Semiconductor memory device. A first interlayer insulating film formed on an upper layer of the semiconductor substrate;
A first plug having one end and the other end and selectively provided through the first interlayer insulating film;
An interface film directly formed on the one end of the plug;
A phase change film formed on the interface film without contacting the plug;
An upper electrode formed on the phase change film, and the interface film, the phase change film and the upper electrode constitute a phase change memory element,
A sidewall formed on a side surface of the phase change memory element;
A second interlayer insulating film formed on the first interlayer insulating film including the phase change memory element and the sidewall;
A second plug selectively passing through the second interlayer insulating film and electrically connected to the upper electrode;
Semiconductor memory device. The semiconductor memory device according to claim 2,
The second interlayer insulating film is formed of a silicon oxide film, and the sidewalls are formed of a silicon nitride film;
Semiconductor memory device. (a) forming a first interlayer insulating film on an upper layer of the semiconductor substrate;
(b) selectively forming a first plug having one end and the other end through the first interlayer insulating film;
(c) forming a layered structure including an interface film, a phase change film and an upper electrode on the first interlayer insulating film, and then performing anisotropic etching to perform patterning to form a phase change memory element; The interface film in the phase change memory is electrically connected to one end of the first plug, includes the entire planar shape of the phase change film, and has a planar shape wider than the planar shape of the phase change film. Formed,
(d) Immediately after the step (c), the surface of the first interlayer insulating film, the surface and the side surface of the phase change memory element are washed with water, and are generated by the anisotropic etching process. Further comprising removing the residue,
Manufacturing method of semiconductor memory device. A method of manufacturing a semiconductor memory device according to claim 4,
The cleaning process in the step (d) is performed so that the concentration of the residue on the first interlayer insulating film is approximately the same as that before the step (c) is performed.
Manufacturing method of semiconductor memory device. A method of manufacturing a semiconductor memory device according to claim 4 or 5,
The anisotropic etching process in the step (c) includes an etching process using at least one of chlorine and fluorine as an etching gas, and the residue includes a residue of the etching gas,
The cleaning process in the step (d) is performed such that the concentration of the residue on the first interlayer insulating film is about 10 × ¹¹ to 10 × ⁹ atom / cm ² .
Manufacturing method of semiconductor memory device. (a) forming a first interlayer insulating film on an upper layer of the semiconductor substrate;
(b) selectively forming a first plug having one end and the other end through the first interlayer insulating film;
(c) forming a layered structure including an interface film, a phase change film and an upper electrode on the first interlayer insulating film, and then performing anisotropic etching to perform patterning to form a phase change memory element; ,
(d) forming a sidewall on a side surface of the phase change memory element;
(e) forming a second interlayer insulating film on the first interlayer insulating film including the phase change memory element and the sidewall;
(f) forming a second plug that is selectively provided through the second interlayer insulating film and is electrically connected to the upper electrode; A method of manufacturing a semiconductor memory device according to claim 7,
The process of penetrating the second interlayer insulating film in the step (f) includes an etching process with a selectivity with respect to the sidewall of about 10 to 10 ⁴ .
Manufacturing method of semiconductor memory device. A method of manufacturing a semiconductor memory device according to claim 8, comprising:
The sidewall is formed of a silicon nitride film, and the second interlayer insulating film is formed of a silicon oxide film;
Manufacturing method of semiconductor memory device.

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