JP2008288292A5 - - Google Patents
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- JP2008288292A5 JP2008288292A5 JP2007130071A JP2007130071A JP2008288292A5 JP 2008288292 A5 JP2008288292 A5 JP 2008288292A5 JP 2007130071 A JP2007130071 A JP 2007130071A JP 2007130071 A JP2007130071 A JP 2007130071A JP 2008288292 A5 JP2008288292 A5 JP 2008288292A5
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- film
- interlayer insulating
- insulating film
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Claims (9)
一端及び他端を有し、前記第１の層間絶縁膜を貫通して選択的に設けられるプラグと、
前記プラグの前記一端上に形成される界面膜と、
前記界面膜上に形成されるカルコゲナイド膜と、
前記カルコゲナイド膜上に形成された上部電極とを備え、前記界面膜、前記カルコゲナイド膜及び前記上部電極によりメモリ素子が構成され、
前記界面膜は、前記カルコゲナイド膜の平面形状全体を含み、かつ前記カルコゲナイド膜の平面形状より広い平面形状で形成されることを特徴とする、
半導体装置。 A first interlayer insulating film formed on the semiconductor base plate,
Has one end and the other end, said first interlayer insulating film pulp lug selectively provided through the,
And interface film made form on the one end of the plug,
A chalcogenide film formed on the front Symbol interfacial film,
Wherein an upper electrode formed on the chalcogenide film, the interfacial layer, wherein the chalcogenide film and Increment memory element by the said upper electrode is formed,
The interfacial film, said comprises the entire plane shape of the chalcogenide film, and characterized in that it is formed in a wide planar shape than the planar shape of the chalcogenide film,
Semiconductor KaradaSo location.
一端及び他端を有し、前記第１の層間絶縁膜を貫通して選択的に設けられる第１のプラグと、
前記第１のプラグの前記一端上に形成される界面膜と、
前記界面膜上に形成されるカルコゲナイド膜と、
前記カルコゲナイド膜上に形成された上部電極とを備え、前記界面膜、前記カルコゲナイド膜及び前記上部電極によりメモリ素子が構成され、
前記メモリ素子の側面に形成されるサイドウォールと、
前記メモリ素子及びサイドウォールを含む第１の層間絶縁膜上に形成される第２の層間絶縁膜と、
前記第２の層間絶縁膜を貫通して選択的に設けられ、前記上部電極と電気的に接続される第２のプラグとをさらに備える、
半導体装置。 A first interlayer insulating film formed on the semiconductor substrate ;
A first plug having one end and the other end and selectively provided through the first interlayer insulating film;
And interface film made form on the one end of the first plug,
A chalcogenide film formed on the front Symbol interfacial film,
An upper electrode formed on the chalcogenide film, a memory element is constituted by the interface film, the chalcogenide film and the upper electrode,
A sidewall formed on the side surface of the front texture memory element,
A second interlayer insulating film formed before the first interlayer insulating film including a texture memory element and the side walls,
A second plug selectively passing through the second interlayer insulating film and electrically connected to the upper electrode;
Semiconductor KaradaSo location.
前記第２の層間絶縁膜はシリコン酸化膜より形成され、前記サイドウォールはシリコン窒化膜により形成される、
半導体装置。 A semiconductor KaradaSo location according to claim 2,
The second interlayer insulating film is formed of a silicon oxide film, and the sidewalls are formed of a silicon nitride film;
Semiconductor KaradaSo location.
(b) 前記第１の層間絶縁膜を貫通して、一端及び他端を有するプラグを選択的に形成するステップと、
(c) 前記第１の層間絶縁膜上に、界面膜、カルコゲナイド膜及び上部電極からなる積層構造を形成するステップと、
(d) 前記積層膜に異方性エッチング処理を行うことにより、前記界面膜が、前記カルコゲナイド膜に対し平面視で突出し、かつ、前記プラグの一端に電気的に接続されるように、パターニングしてメモリ素子を形成するステップとを備える、
半導体装置の製造方法。 (a) forming a first interlayer insulating film on an upper layer of the semiconductor substrate;
(b) through said first interlayer insulating film, a step of selectively forming a pulp lug having a one end and the other end,
(c) forming a laminated structure comprising an interface film, a chalcogenide film and an upper electrode on the first interlayer insulating film;
(d) By performing anisotropic etching treatment on the laminated film, the interface film is patterned so as to protrude in a plan view with respect to the chalcogenide film and electrically connected to one end of the plug. And forming a memory element.
Method of manufacturing a semiconductor KaradaSo location.
(e) 前記ステップ(d) 直後に実行され、前記第１の層間絶縁膜の表面、前記メモリ素子の表面及び側面を水洗により洗浄処理を実行し、前記異方性エッチング処理により生じた残留物を除去するステップをさらに備え、
前記ステップ(e) における前記洗浄処理は、前記第１の層間絶縁膜上の前記残留物の濃度が前記ステップ(d) 実行前と同程度になるように実行される、
半導体装置の製造方法。 A method of manufacturing a semiconductor KaradaSo location according to claim 4,
(e) Residues generated immediately after the step (d), wherein the surface of the first interlayer insulating film, the surface and the side surfaces of the memory element are washed with water, and the anisotropic etching process is performed. Further comprising the step of removing
The cleaning process in the step (e) is performed such that the concentration of the residue on the first interlayer insulating film is approximately the same as that before the step (d) is performed.
Method of manufacturing a semiconductor KaradaSo location.
前記ステップ(d) における前記異方性エッチング処理は塩素及びフッ素のうち少なくとも一方をエッチングガスとしたエッチング処理を含み、前記残留物は前記エッチングガスの残留物を含み、
前記ステップ(e) における前記洗浄処理は、前記第１の層間絶縁膜上の前記残留物の濃度が１０×11〜１０×9 atom/ｃｍ2程度の濃度になるように実行される、
半導体装置の製造方法。 A claim 4 or method of manufacturing a semiconductor KaradaSo location according to claim 5,
The anisotropic etching process in the step (d) includes an etching process using at least one of chlorine and fluorine as an etching gas, and the residue includes a residue of the etching gas,
The cleaning process in the step (e) is performed such that the concentration of the residue on the first interlayer insulating film is about 10 × 11 to 10 × 9 atom / cm 2 .
Method of manufacturing a semiconductor KaradaSo location.
(b) 前記第１の層間絶縁膜を貫通して、一端及び他端を有する第１のプラグを選択的に形成するステップと、
(c) 前記第１の層間絶縁膜上に、界面膜、カルコゲナイド膜及び上部電極からなる積層構造を形成した後、異方性エッチング処理を行いパターニングしてメモリ素子を形成するステップと、
(d) 前記メモリ素子の側面にサイドウォールを形成するステップと、
(e) 前記メモリ素子及びサイドウォールを含む第１の層間絶縁膜上に第２の層間絶縁膜を形成するステップと、
(f) 前記第２の層間絶縁膜を貫通して選択的に設けられ、前記上部電極と電気的に接続される第２のプラグを形成するステップとを備える、
半導体装置の製造方法。 (a) forming a first interlayer insulating film on an upper layer of the semiconductor substrate;
(b) selectively forming a first plug having one end and the other end through the first interlayer insulating film;
(c) on the first interlayer insulating film, after forming a laminated structure composed of interfacial membranes, chalcogenide layer and an upper electrode, and forming a memory element is patterned by anisotropic etching process,
forming a sidewall on a side face of (d) before texture memory element,
forming a second interlayer insulating film on the first interlayer insulating film comprising (e) before texture memory element and the side walls,
(f) forming a second plug selectively provided through the second interlayer insulating film and electrically connected to the upper electrode ;
Method of manufacturing a semiconductor KaradaSo location.
前記ステップ(f) の前記第２の層間絶縁膜を貫通する処理は、前記サイドウォールとの選択比が１０〜１０4程度のエッチング処理を含む、
半導体装置の製造方法。 A method of manufacturing a semiconductor KaradaSo location according to claim 7,
The process of penetrating the second interlayer insulating film in the step (f) includes an etching process with a selectivity with respect to the sidewall of about 10 to 10 4 .
Method of manufacturing a semiconductor KaradaSo location.
前記サイドウォールはシリコン窒化膜により形成され、前記第２の層間絶縁膜はシリコン酸化膜により形成される、
半導体装置の製造方法。 A method of manufacturing a semiconductor KaradaSo location according to claim 8,
The sidewall is formed of a silicon nitride film, and the second interlayer insulating film is formed of a silicon oxide film;
Method of manufacturing a semiconductor KaradaSo location.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007130071A JP2008288292A (en) | 2007-05-16 | 2007-05-16 | Semiconductor storage device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007130071A JP2008288292A (en) | 2007-05-16 | 2007-05-16 | Semiconductor storage device and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008288292A JP2008288292A (en) | 2008-11-27 |
| JP2008288292A5 true JP2008288292A5 (en) | 2010-04-08 |
Family
ID=40147754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007130071A Pending JP2008288292A (en) | 2007-05-16 | 2007-05-16 | Semiconductor storage device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2008288292A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000004010A (en) * | 1999-04-28 | 2000-01-07 | Matsushita Electron Corp | Manufacture of capacitor elements |
| KR100653701B1 (en) * | 2004-08-20 | 2006-12-04 | 삼성전자주식회사 | Method of forming a small via structure in a semiconductor device and method of fabricating phase change memory device using the same |
| JP2006352082A (en) * | 2005-05-19 | 2006-12-28 | Renesas Technology Corp | Semiconductor memory device and its manufacturing method |
| JP2007042804A (en) * | 2005-08-02 | 2007-02-15 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
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2007
- 2007-05-16 JP JP2007130071A patent/JP2008288292A/en active Pending
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