JP2007027571A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a structure robust against misalignment in photolithography. <P>SOLUTION: The semiconductor integrated circuit device comprises a signal electrode line BL arranged periodically, and a signal electrode line contact 13 arranged in a line at the same cycle with the signal electrode line BL in the ward line direction. The side surface of the signal electrode line BL contacts a first insulating material 14 and a second insulating material 15 laminated on the first insulating material 14. In the cross section in the word line direction, the diameter Dbtm at the part of the signal electrode line BL that contacts the signal electrode line contact 13 is smaller than the diameter Dtop at the top surface of the signal electrode line BL. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a periodic contact such as a bit line contact.

  Needless to say, it is important to shorten the cycle of bit lines as signal input lines and word lines as drive signal lines of memory cells in order to arrange memory cells at high density. In particular, in a flash memory that is representative of a high-density, large-capacity memory, the bit line cycle is the same as the memory cell cycle. A bit line contact is used to connect the bit line to the memory cell. The bit line contact is arranged in a horizontal row in the word line direction intersecting the bit line direction at the same cycle as the bit line cycle. The diameter of the bit line contact is basically wider than the width of the diffusion layer of the memory cell. This is because the optical resolution of the hole pattern is inferior to that of the line pattern, so that it is necessary to resolve the diameter wider.

  Under such circumstances, although the bit line contacts are arranged at the same cycle as the bit line, the space between the contacts is narrower than the space between the bit lines. This indicates that the withstand voltage between contacts is stricter than the withstand voltage between bit lines. Further, it is shown that a defect due to leakage is more likely to occur between the contacts than between the bit lines.

  In addition, the bit line is pattern-transferred using a photolithographic technique, but it must be devised so as not to cause misalignment with the bit line contact. When a large misalignment occurs, the bit lines are formed so as to be shifted between the bit line contacts. This indicates that the distance between the bit line and the bit line contact adjacent thereto is narrower than the distance between the bit line contacts. That is, a large misalignment increases the possibility of causing a breakdown voltage failure and a leakage failure. Such misalignment is becoming a non-negligible situation as cell miniaturization progresses. This is particularly noticeable in flash memories such as NAND flash and NOR flash where bit line contacts are arranged in a horizontal row and the density of memory cells is extremely high.

Patent Document 1 is a known example that discloses a bit line contact.
JP 2002-151665 A

  The present invention provides a semiconductor integrated circuit device having a structure strong against misalignment in photolithography.

  The semiconductor integrated circuit device according to one aspect of the present invention is configured such that the signal electrode lines periodically arranged and the signal electrodes arranged in a line in the direction intersecting the signal electrode line direction in the same cycle as the signal electrode lines. A signal electrode line contact connected to the electrode line, and a side surface of the signal electrode line is in contact with a first insulating material and a second insulating material laminated on the first insulating material, In the cross section in the direction intersecting with the signal electrode line direction, the diameter of the portion of the signal electrode line in contact with the signal electrode line contact is smaller than the diameter of the uppermost surface of the signal electrode line.

  According to the present invention, a semiconductor integrated circuit device having a structure strong against misalignment in photolithography can be provided.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. In this example, a NAND flash memory is shown. However, the present embodiment is applied to an electrically rewritable nonvolatile semiconductor memory device other than the NAND flash memory, and also to a semiconductor memory device other than the nonvolatile semiconductor memory device. It can also be applied to.

  FIG. 1 is a plan view showing a planar pattern example of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line 2-2 in FIG. 1 and 2 show the structure of bit lines and bit line contacts of a NAND flash memory as an example of a semiconductor integrated circuit device.

  As shown in FIGS. 1 and 2, the signal electrode lines, for example, the bit lines BL extend in the bit line direction and intersect with the bit line direction, for example, in a row with the bit line period BLp along the orthogonal word line direction. Placed in. The lower surface of the bit line BL is connected to the signal electrode line contact, for example, the upper surface of the bit line contact 13.

  The bit line contacts 13 are arranged in a line along the word line direction with the same cycle BLCp as the bit line cycle BLp. The lower surface of the bit line contact 13 is connected to the drain diffusion layer 11 of the drain side block select transistor STD. The drain diffusion layer 11 is formed in the active area AA of the semiconductor substrate, for example, the silicon substrate 10. The active area AA is separated from the substrate 10 by the element isolation region STI. The bit line contact 13 is formed by forming a hole-like opening in the interlayer insulating film 12 and embedding a low-resistance conductive material in the opening. An example of the material of the bit line contact 13 is conductive polycrystalline silicon (poly-Si). However, the present invention is not limited to this, and a metal material can be used. One example is tungsten. Moreover, when using a metal material, you may make it cover the side surface and lower surface of a metal material with a barrier metal film. As the material of the barrier metal film, a material having good adhesion to the interlayer insulating film 12, for example, adhesion to silicon dioxide is selected. In addition, since the bit line contact 13 is in contact with the substrate 10, a material excellent in alloying property with the substrate 10, for example, alloying property with silicon is selected. An example of such a material is a titanium nitride film or a laminated film of titanium and titanium nitride. In the cross section along the word line direction, the diameter Dblc of the bit line contact 13 is wider than the uppermost surface diameter Dtop of the bit line BL or the lowermost surface diameter Dbtm in the same cross section.

  The bit line BL of this example is formed by forming a line-shaped groove 21 from the interlayer insulating film 15 to the interlayer insulating film 14 and embedding a low resistance material in the groove 21. The interlayer insulating film 14 is formed on the upper surface of the interlayer insulating film 12 and the upper surface of the bit line contact 13, and the interlayer insulating film 15 is formed on the interlayer insulating film 14.

  In this example, the material of the interlayer insulating film 14 is different from the material of the interlayer insulating film 15. As a result, when the trench 21 is formed, the etching selectivity with respect to the interlayer insulating film 15 can be taken when the interlayer insulating film 14 is etched, and conversely, when the interlayer insulating film 14 is etched, the interlayer insulating film 14 is etched. It becomes possible to take an etching selection ratio with respect to the insulating film 14. As an example of the material, the interlayer insulating film 14 is silicon dioxide, and the interlayer insulating film 15 is silicon nitride. Further, in this example, the thickness t14 of the interlayer insulating film 14 is thinner than the thickness t15 of the interlayer insulating film 15. According to this, for example, when the surface of the bit line contact 13 is cleaned, the insulating film exposed to the side wall of the trench 21 in the insulating film near the bit line contact 13 can be hardly affected by the cleaning agent. The advantage that can be obtained. That is, inadvertent expansion of the groove 21 can be suppressed during cleaning. Further, when the trench 21 is formed, there is an advantage that the etching time for the interlayer insulating film 14 can be made shorter than the etching time for the interlayer insulating film 15.

  The cross-sectional shape of the groove 21 in this example is a shape having a wide frontage and a narrow depth. Specifically, in the cross section along the word line direction, when the diameter of the upper portion of the groove 21, for example, the upper surface of the bit line BL is “Dtop”, the lower portion of the groove 21, for example, the bit line The diameter Dbtm (lowermost surface diameter) on the lower surface of the BL is narrower than the diameter Dtop. That is, in the cross section of the bit line BL along the word line direction, the diameter of the portion in contact with the bit line contact is smaller than the diameter of the uppermost surface of the bit line BL. It can also be said that the diameter of the portion in contact with the interlayer insulating film 14 in the cross section of the bit line BL along the word line direction is narrower than the diameter of the uppermost surface of the bit line BL.

  As the material of the bit line BL, a low resistance conductive material is selected similarly to the bit line contact 13. In this example, a metal material is selected. One example is tungsten. In this example, the metal material film, for example, the side surface and the lower surface of the tungsten film 20 is covered with the barrier metal film 19. As the material of the barrier metal film 19, a material having good adhesion to the interlayer insulating film 12, for example, adhesion to silicon dioxide, is selected as in the bit line contact 13. One example is a titanium nitride film or a laminated film of titanium and titanium nitride.

  The upper surface of the bit line BL is flattened. An interlayer insulating film 22 is formed on the flattened upper surface of the bit line BL and on the upper surface of the interlayer insulating film 15 as in the known NAND flash memory. A wiring formed above the bit line BL and an interlayer insulating film are also formed on the interlayer insulating film 22. These are omitted in this specification.

  Next, an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment will be described.

  3 to 7 are sectional views showing an example of a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention in the order of main steps.

  First, the interlayer insulating film 12 and the bit line contact 13 are formed according to a known manufacturing method. For example, according to a known manufacturing method, the element isolation region STI, the floating gate, the word line WL, the block selection line SG, the memory cell transistor, and the source and drain diffusion layers of the block selection transistor are formed. Next, these are covered with an interlayer insulating film 12. Next, a hole-like opening reaching the drain diffusion layer 11 of the drain side block selection transistor STD is formed in the interlayer insulating film 12. Next, the hole-like opening is filled with a low-resistance conductive material, for example, conductive polycrystalline silicon, and the conductive polycrystalline silicon is etched back or CMP to be flattened. Thereby, the bit line contact 13 is formed.

  Next, as shown in FIG. 3, for example, silicon dioxide is deposited on the upper surface of the interlayer insulating film 12 and the upper surface of the bit line contact 13 to form the interlayer insulating film 14.

  Next, as shown in FIG. 4, for example, silicon nitride is deposited on the interlayer insulating film 14 to form the interlayer insulating film 15. In this example, the interlayer insulating film 15 is formed thicker than the interlayer insulating film 14. Next, a photoresist is applied on the interlayer insulating film 15 to form a photoresist film 30. Next, a line-shaped pattern 31 corresponding to the bit line layout is formed on the photoresist film 30 by using a photolithography technique.

  Next, as shown in FIG. 5, using the photoresist film 30 as a mask, the interlayer insulating film 15 is etched until it reaches the interlayer insulating film 14, thereby forming a line-shaped groove 16 in the interlayer insulating film 15. For example, the RIE method is used for this etching, and the etching conditions are such that the interlayer insulating film 15 is easily etched and the interlayer insulating film 14 is difficult to etch.

  Next, as shown in FIG. 6, after removing the photoresist film 30, for example, silicon nitride is deposited on the upper surface of the interlayer insulating film 15 and on the interlayer insulating film 14 exposed at the bottom of the groove 16, and then nitrided. A silicon film is formed. Next, the silicon nitride film is etched back by using, for example, the RIE method, and a spacer, in this example, a silicon nitride spacer 17 is formed on the side wall of the groove 16.

  Next, as shown in FIG. 7, using the interlayer insulating film (silicon nitride) 15 and the silicon nitride spacer 17 as a mask, the interlayer insulating film (silicon dioxide) 14 is etched until the bit line contact 13 is reached. A groove 18 is formed in the insulating film 14. As a result, a line-shaped groove 21 corresponding to the bit line layout is formed. Next, wet or dry cleaning is performed on the upper surface of the bit line contact 13 exposed at the bottom of the groove 21 to clean the upper surface of the bit line contact 13. This is cleaning of the bit line contact 13. An example of the cleaning agent is hydrofluoric acid (HF). Note that hydrofluoric acid has a property of etching the interlayer insulating film 14 and the interlayer insulating film 15. For this reason, at the time of cleaning, the diameter of the groove 21 may be inadvertently enlarged. Moreover, the etching rate of hydrofluoric acid for silicon dioxide is higher than the etching rate for silicon nitride. For this reason, the diameter of the portion of the groove 21 that is in contact with the bit line contact 13 tends to increase carelessly. In this respect, in this example, by making the interlayer insulating film (silicon dioxide) 14 thinner than the thickness of the interlayer insulating film (silicon nitride) 15, it is difficult to increase the diameter of the portion of the groove 21 that contacts the bit line contact 13. is doing. For example, by making the interlayer insulating film 14 thinner, the cleaning agent is prevented from penetrating or reaching the interlayer insulating film 14. Further, with respect to the withstand voltage characteristics, the interlayer insulating film (silicon nitride) 15 is superior to the interlayer insulating film (silicon dioxide) 14. Therefore, the breakdown voltage characteristics between the bit lines BL can be improved by making the interlayer insulating film 14 thinner and the interlayer insulating film 15 thicker.

  Note that the width of the silicon nitride spacer 17 along the word line direction is not limited to the difference between the bit line width at the time of photolithography and the bit line width that is finally required, and the processing conversion such as the receding amount at the time of cleaning. It may be determined in consideration of the difference.

  Next, as shown in FIG. 2, a barrier metal material such as titanium nitride or the like is formed on the interlayer insulating film 15, the silicon nitride spacer 17, the side surface of the interlayer insulating film 14, and the upper surface of the bit line contact 13. Titanium and titanium nitride are deposited to form a barrier metal film 19. Next, a bit line material, for example, tungsten is deposited on the barrier metal film 19 to form a tungsten film 20. Next, the tungsten film 20 and the barrier metal film 19 are planarized using a CMP method, and these films are embedded in the line-shaped grooves 21. As a result, the bit line BL embedded in the groove 21 is formed.

  Subsequent steps may follow a well-known manufacturing method. Therefore, it is omitted in this specification.

  According to the semiconductor integrated circuit device according to the embodiment, the interlayer insulating film 15 is formed with the groove 16 having a wide cross-sectional diameter along the word line direction, and the diameter is once narrowed by the silicon nitride spacer 17. A groove 18 is formed in the interlayer insulating film 14. For this reason, the line-shaped pattern corresponding to the bit line layout, in this example, the groove 21 can be formed with a dimension having a margin in photolithography. On the other hand, the size of the lower portion of the bit line BL adjacent to the bit line contact 13 can be reduced. For this reason, even when misalignment occurs, the distance between the bit line BL and the adjacent bit line contact 13 can be sufficiently separated, and the deterioration of breakdown voltage and leakage can be suppressed. It becomes.

  Thus, according to one embodiment, a semiconductor integrated circuit device having a structure strong against misalignment in photolithography can be obtained.

  Moreover, since the groove | channel 21 can be formed in the dimension which has allowances in photolithography, it also becomes possible to make it go to the tendency to ease on the contrary from the tendency to make a matching standard severe. According to this, it is possible to reduce lithography frequency due to misalignment during the manufacturing process, for example, to reduce the frequency of photomask position correction, and to improve the throughput of a semiconductor integrated circuit device such as a NAND flash memory. Can also be obtained. By improving the throughput, it is possible to suppress an increase in manufacturing cost of a semiconductor integrated circuit device, for example, a NAND flash memory, and thus an increase in chip cost.

  As mentioned above, although this invention was demonstrated by one Embodiment, the said one Embodiment is not the only embodiments of this invention. Various modifications can be made without departing from the spirit of the invention.

  Further, the above-described embodiment includes inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiment.

  The embodiment has been described based on an example in which the present invention is applied to a NAND flash memory. However, the present invention is not limited to the NAND flash memory, and the flash memory other than the NAND type may further include a DRAM. , SRAM, MRAM, FeRAM, and other memories other than flash memory can also be applied. Furthermore, a semiconductor integrated circuit device incorporating these memories, for example, a processor, a system LSI, etc. is also within the scope of the present invention.

FIG. 1 is a plan view showing a plane pattern example of a semiconductor integrated circuit device according to an embodiment of the present invention. 2 is a sectional view taken along line 2-2 in FIG. FIG. 3 is a sectional view showing one manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 4 is a sectional view showing one manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 5 is a sectional view showing one manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 6 is a sectional view showing one manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 7 is a sectional view showing one manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 13 ... Bit line contact, BL ... Bit line, 14 ... Interlayer insulation film (silicon dioxide), 15 ... Interlayer insulation film (silicon nitride), 17 ... Spacer.

Claims (5)

Periodically arranged signal electrode wires;
A signal electrode line contact connected to the signal electrode line, arranged in a line with the same period as the signal electrode line in a direction intersecting with the signal electrode line direction,
The side surface of the signal electrode line is in contact with the first insulating material and the second insulating material laminated on the first insulating material,
In a cross section in a direction intersecting with the signal electrode line direction, a diameter of a portion of the signal electrode line in contact with the signal electrode line contact is narrower than a diameter of an uppermost surface of the signal electrode line. Circuit device.   2. The semiconductor integrated circuit device according to claim 1, wherein a diameter of a portion of the signal electrode line in contact with the first insulating material is narrower than a diameter of an uppermost surface of the signal electrode line.   3. The semiconductor integrated circuit according to claim 1, wherein the signal electrode line has a laminated structure of a conductive film and a barrier film covering a side surface and a lower surface of the conductive film. apparatus.   4. The semiconductor integrated circuit device according to claim 3, wherein the hydrofluoric acid etching rate of the first insulating material is higher than the hydrofluoric acid etching rate of the second insulating material.   5. The semiconductor integrated circuit device according to claim 3, wherein a thickness of the first insulating material is thinner than a thickness of the second insulating material.

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