JP2008288231A - Light-emitting device - Google Patents

Light-emitting device Download PDF

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JP2008288231A
JP2008288231A JP2007128779A JP2007128779A JP2008288231A JP 2008288231 A JP2008288231 A JP 2008288231A JP 2007128779 A JP2007128779 A JP 2007128779A JP 2007128779 A JP2007128779 A JP 2007128779A JP 2008288231 A JP2008288231 A JP 2008288231A
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emitting diode
light emitting
light
current
diode chip
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JP5066390B2 (en
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Sohiko Betsuda
惣彦 別田
Sadato Imai
貞人 今井
Koichi Fukazawa
孝一 深沢
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Citizen Electronics Co Ltd
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Citizen Electronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable light-emitting device having favorable balance in current by configuring a light-emitting diode package in such a way that various kinds of light-emitting diode chips are connected in parallel while suppressing variations in VF characteristics of the diode chips which have not been covered by a prior art. <P>SOLUTION: The light-emitting diode package is configured so that the light-emitting diode chips are connected in parallel while using two characteristic conditions crossing through three points A, B and C as a selection reference in forward voltage-forward current characteristics. The current at the point B is set at 1/2 of a rated current, and thus, the current of each light-emitting diode chip in the light-emitting diode package satisfies the current value of ≥50% of the rated current. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は複数個の発光ダイオードを並列接続して強い発光量を得る発光装置に関する。   The present invention relates to a light emitting device that obtains a strong light emission amount by connecting a plurality of light emitting diodes in parallel.

近年発光ダイオードの大容量化が進み、単体の発光ダイオードでも強い発光量が得られるが、大きな発光量を得るには、複数の発光ダイオードを直列接続、または並列接続する。直列接続は、直列接続する発光ダイオードの数に応じて駆動電圧を高くしなければならない。また、並列接続は、並列接続する各発光ダイオードに電流制限抵抗を付加するか、順方向電圧特性を揃えなければならない。更に、大きな発光量を得るには、発光ダイオードを直列接続、および並列接続を組み合わせるのである。   In recent years, the capacity of light emitting diodes has increased, and even a single light emitting diode can obtain a strong light emission amount. However, in order to obtain a large light emission amount, a plurality of light emitting diodes are connected in series or in parallel. In series connection, the drive voltage must be increased according to the number of light emitting diodes connected in series. In parallel connection, a current limiting resistor must be added to each light emitting diode connected in parallel, or forward voltage characteristics must be aligned. Furthermore, in order to obtain a large amount of light emission, the light emitting diodes are combined in series connection and parallel connection.

上に述べたように、従来は、複数の発光ダイオードを並列接続し、電流制限抵抗を極力少なくするために、発光ダイオードの順方向電圧特性を選別し、特性の揃った発光ダイオードを並列接続してひとつのパッケージを形成する方法があった。（例えば、特許文献１）   As described above, conventionally, in order to connect a plurality of light emitting diodes in parallel and reduce the current limiting resistance as much as possible, the forward voltage characteristics of the light emitting diodes are selected and light emitting diodes with uniform characteristics are connected in parallel. There was a way to form a single package. (For example, Patent Document 1)

以下、図面を用いて従来技術における複数個の発光ダイオードを並列接続した構造について説明する。図６は、従来の複数の発光ダイオードチップを並列接続した発光ダイオードパッケージの回路図である。６０は発光ダイオードパッケージ、６３ａ、６３ｂ、６３ｃ、６３ｎは発光ダイオードチップ、６１は発光ダイオードパッケージ６０のアノード、６２は発光ダイオードパッケージ６０のカソードを示す。   Hereinafter, a structure in which a plurality of light emitting diodes in the related art are connected in parallel will be described with reference to the drawings. FIG. 6 is a circuit diagram of a light emitting diode package in which a plurality of conventional light emitting diode chips are connected in parallel. Reference numeral 60 denotes a light emitting diode package, 63a, 63b, 63c and 63n denote light emitting diode chips, 61 denotes an anode of the light emitting diode package 60, and 62 denotes a cathode of the light emitting diode package 60.

発光ダイオードパッケージ６０を構成するには、並列接続する発光ダイオードチップ６３ａ、６３ｂ、６３ｃ、６３ｎの特性、例えば、順電圧ＶＦ５が揃っている必要がある。仮に、順電圧ＶＦ５にバラツキがあると、最も順電圧が低い発光ダイオードチップに過大な電流が流れ、他の並列発光ダイオードチップの電流は少なくなり、電流バランスが悪く発光効率の悪い発光ダイオードパッケージとなる。
従って、同一発光ダイオードパッケージ６０に搭載し、並列接続する発光ダイオードチップ６３ａ、６３ｂ、６３ｃ、６３ｎの特性を揃えることが必要となる。 In order to configure the light emitting diode package 60, the characteristics of the light emitting diode chips 63a, 63b, 63c, and 63n connected in parallel, for example, the forward voltage VF5 must be aligned. If the forward voltage VF5 varies, an excessive current flows through the light emitting diode chip having the lowest forward voltage, and the current of the other parallel light emitting diode chips is reduced. Become.
Therefore, it is necessary to align the characteristics of the light emitting diode chips 63a, 63b, 63c, and 63n that are mounted on the same light emitting diode package 60 and connected in parallel.

図７は、一般的な発光ダイオードチップの順方向電圧と順方向電流の特性図である。７０は従来の発光ダイオードチップの電圧と電流特性で、Ｘ軸は順方向電圧ＶＦ、Ｙ軸は順方向電流ＩＦで示す。７１は複数の発光ダイオードチップの順方向電圧と順方向電流のＶＦ−ＩＦ特性を示す。このようにバラツキのある発光ダイオードチップの特性を揃える方法として、一定の順方向電流を各発光ダイオードチップに印加し、そのときの順方向電圧を一定のランク毎に選択するのである。   FIG. 7 is a characteristic diagram of forward voltage and forward current of a general light emitting diode chip. Reference numeral 70 denotes a voltage and current characteristic of a conventional light emitting diode chip, where the X axis is a forward voltage VF and the Y axis is a forward current IF. Reference numeral 71 denotes VF-IF characteristics of forward voltage and forward current of a plurality of light emitting diode chips. As a method of aligning the characteristics of the light-emitting diode chips having such variations, a constant forward current is applied to each light-emitting diode chip, and the forward voltage at that time is selected for each constant rank.

つまり、従来の発光ダイオードチップのランク分けは、符号７２で示す一定の順方向電流を各発光ダイオードチップに印加し、このときの順方向電圧を７３、７４、７５で示す各順方向の電圧巾で選別するのである。従来例では、順方向電圧のバラツキ巾を０．１Ｖ以下で選別すれば実用上並列接続に供することができ、並列接続に必要とされていた各発光ダイオードチップの電流制限抵抗を削減し、信頼性の高い発光装置が得られるとしている。   That is, according to the ranking of the conventional light-emitting diode chips, a constant forward current indicated by reference numeral 72 is applied to each light-emitting diode chip, and the forward voltage at this time is indicated by 73, 74, 75 in the forward voltage width. Sort by. In the conventional example, if the variation width of the forward voltage is selected to be 0.1 V or less, it can be practically used for parallel connection, and the current limiting resistance of each light-emitting diode chip required for parallel connection can be reduced and It is said that a highly efficient light-emitting device can be obtained.

特開２００６−２２２４１２号Japanese Patent Laid-Open No. 2006-222412

しかしながら、複数の発光ダイオードチップを先行技術でランク分けして並列接続し、発光ダイオードパッケージを構成しても、各発光ダイオードチップのわずかな順方向電圧の違いで、並列接続した各発光ダイオードチップを流れる順方向電流値には差異を生じる。環境温度が変化して、例えば、温度が上昇すれば同一電流でも順方向電圧値は低下し、順方向電圧と順方向電流特性が各々違った変化をして電流バランスが崩れる場合がある。殊に、異なるウェーハーからの多品種発光ダイオードチップをランク分けした場合は、カバーしきれない電流のアンバランスを生じるという問題もあった。   However, even if a plurality of light emitting diode chips are ranked in parallel according to the prior art and connected in parallel to form a light emitting diode package, each light emitting diode chip connected in parallel is separated by a slight difference in forward voltage of each light emitting diode chip. There is a difference in the flowing forward current value. When the environmental temperature changes, for example, when the temperature rises, the forward voltage value decreases even with the same current, and the forward voltage and the forward current characteristic may change differently, resulting in a loss of current balance. In particular, when various types of light emitting diode chips from different wafers are ranked, there is a problem in that an unbalance of current that cannot be covered occurs.

すなわち、本発明の目的は、先行技術でカバーしきれないような、多品種発光ダイオードチップの順方向電圧特性のバラツキを押さえて並列接続することで発光ダイオードパッケージを構成し、電流バランスの良い、信頼性の高い発光装置を提供することにある。   That is, the object of the present invention is to form a light emitting diode package by connecting in parallel while suppressing variations in forward voltage characteristics of a variety of light emitting diode chips that cannot be covered by the prior art, and has a good current balance. An object is to provide a light-emitting device with high reliability.

上記目的を達成するための本発明の発光装置は、基本的には下記記載の構成要件を採用するものである。
順方向電圧−順方向電流特性を選択的に揃えた複数の発光ダイオードチップを並列接続して発光ダイオードパッケージを構成する発光装置において、一定電圧ＶＦにおける発光ダイオードチップの定格電流点をＡ、前記一定電圧ＶＦにおける発光ダイオードチップの定格電流の１／Ｎ点をＢ、前記一定電圧ＶＦ＋ΔＶにおける発光ダイオードチップの定格電流点をＣとし、被選択発光ダイオードチップの選択第１特性条件は、前記被選択発光ダイオードチップの順方向電圧−順方向電流特性がＡ−Ｂの線分と交わり、第２特性条件は、前記被選択発光ダイオードチップの順方向電圧−順方向電流特性がＡ−Ｃの線分と交わる、ふたつの特性条件を選択基準にして発光ダイオードパッケージを構成したことを特徴とする。 In order to achieve the above object, the light emitting device of the present invention basically employs the following constituent elements.
In a light-emitting device in which a light-emitting diode package is configured by connecting in parallel a plurality of light-emitting diode chips having a selective forward voltage-forward current characteristic, A is a rated current point of the light-emitting diode chip at a constant voltage VF. The 1 / N point of the rated current of the light emitting diode chip at the voltage VF is B, the rated current point of the light emitting diode chip at the constant voltage VF + ΔV is C, and the selected first characteristic condition of the selected light emitting diode chip is the selected light emission. The forward voltage-forward current characteristic of the diode chip intersects with the line segment AB, and the second characteristic condition is that the forward voltage-forward current characteristic of the selected light emitting diode chip is the line segment AC. A light-emitting diode package is configured based on two characteristic conditions that meet each other as a selection criterion.

前記発光ダイオードチップの定格電流の１／Ｎは、Ｎ＝２であることを特徴とする。また、前記ΔＶは０．４Ｖ以下であることを特徴とする。   1 / N of the rated current of the light emitting diode chip is N = 2. Further, the ΔV is 0.4V or less.

また、複数の発光ダイオードチップを直列接続した発光ダイオードパッケージを複数個並列接続して構成する発光装置において、前記発光装置を構成する複数の発光ダイオードパッケージは、順方向電圧−順方向電流特性の前記第１、および第２のふたつの特性条件により、あらかじめ順方向電圧を選択的に揃えたことを特徴とする。   Further, in the light emitting device configured by connecting a plurality of light emitting diode packages in which a plurality of light emitting diode chips are connected in series, the plurality of light emitting diode packages constituting the light emitting device have a forward voltage-forward current characteristic. The forward voltage is selectively aligned in advance according to the first and second characteristic conditions.

つまり、本発明によれば、順方向電圧−順方向電流特性において、Ａ、Ｂ、Ｃの３点を通る前述のふたつの特性条件を選択基準にして、発光ダイオードチップを並列接続することで発光ダイオードパッケージを構成するため、印加する順方向電圧が多少変動しても、発光ダイオードパッケージ内の発光ダイオードチップのバラツキが少なく、かつ、Ｂ点の電流を定格電流の１／２とすることで、発光ダイオードパッケージ内の発光ダイオードチップの電流は定格の５０％以上の電流値を満足する発光装置を提供できる。   That is, according to the present invention, in forward voltage-forward current characteristics, light emission is achieved by connecting light emitting diode chips in parallel with the above-mentioned two characteristic conditions passing through three points A, B, and C as selection criteria. Since the diode package is configured, even if the applied forward voltage varies somewhat, the variation of the light-emitting diode chip in the light-emitting diode package is small, and the current at the point B is ½ of the rated current, It is possible to provide a light emitting device that satisfies the current value of 50% or more of the rated current of the light emitting diode chip in the light emitting diode package.

以下、本発明の実施形態について図面に基づいて説明する。まず、本発明による発光装置の構成、構造の詳細を説明する。
図１ａは、本発明による発光装置の回路図であり、図１ｂは、本発明による発光装置の平面図であり、図１ｃは、本発明による発光装置の斜視図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, details of the configuration and structure of the light emitting device according to the present invention will be described.
1a is a circuit diagram of a light emitting device according to the present invention, FIG. 1b is a plan view of the light emitting device according to the present invention, and FIG. 1c is a perspective view of the light emitting device according to the present invention.

図１ａ、図１ｂ、および図１ｃにおいて、１０は発光ダイオードパッケージ、１１ａ、１１ｂ、１１ｃは発光ダイオードチップ、１２は発光ダイオードパッケージ１０のアノード電極、１３は発光ダイオードパッケージ１０のカソード電極、１４は発光ダイオードパッケージ１０の基板である。また、図１ａにおいて、１５は発光ダイオードパッケージ１０を発光装置として使用する際の電流制限抵抗である。   1a, 1b, and 1c, 10 is a light emitting diode package, 11a, 11b, and 11c are light emitting diode chips, 12 is an anode electrode of the light emitting diode package 10, 13 is a cathode electrode of the light emitting diode package 10, and 14 is light emitting. This is a substrate of the diode package 10. In FIG. 1a, reference numeral 15 denotes a current limiting resistor when the light emitting diode package 10 is used as a light emitting device.

発光ダイオードパッケージ１０を構成する複数の発光ダイオードチップ１１ａ、１１ｂ、１１ｃは、後述する選択基準により組み合わせて、図１ａに示すように並列接続する。   A plurality of light emitting diode chips 11a, 11b, and 11c constituting the light emitting diode package 10 are combined in accordance with a selection criterion described later and connected in parallel as shown in FIG. 1a.

また、発光ダイオードチップ１１ａ、１１ｂ、１１ｃは、図１ｂ、および図１ｃに示すように、発光ダイオードパッケージ１０を形成する基板１４上のカソード電極１３と導通する電極１３ａにダイボンディングで導通固定し、各発光ダイオードチップのアノードはアノード電極１２と導通する電極１２ａにワイヤボンディングで導通する。図示していないが、各発光ダイオードチップ、およびボンディング部は、光透過樹脂でモールドする。   The light emitting diode chips 11a, 11b, and 11c are conductively fixed by die bonding to the electrode 13a that is electrically connected to the cathode electrode 13 on the substrate 14 forming the light emitting diode package 10, as shown in FIGS. 1b and 1c. The anode of each light emitting diode chip is electrically connected to an electrode 12a electrically connected to the anode electrode 12 by wire bonding. Although not shown, each light emitting diode chip and the bonding portion are molded with a light transmitting resin.

次に示す図２ａ、図２ｂは、発光ダイオードチップの電極構造が異なる形状の本発明による発光装置例である。図２ａは、本発明による発光装置の他の回路図であり、図２ｂは、本発明による発光装置の他の平面図である。   2a and 2b shown below are examples of the light emitting device according to the present invention in which the electrode structure of the light emitting diode chip is different. FIG. 2a is another circuit diagram of the light emitting device according to the present invention, and FIG. 2b is another plan view of the light emitting device according to the present invention.

図２ａ、図２ｂにおいて、２０は発光ダイオードパッケージ、２１ａ、２１ｂ、２１ｃ、２１ｎは発光ダイオードチップ、２２は発光ダイオードパッケージ２０のアノード電極、２３は発光ダイオードパッケージ２０のカソード電極、２４は発光ダイオードパッケージ２０の基板である。また、図２ａにおいて、２５は発光ダイオードパッケージ２０を発光装置として使用する際の電流制限抵抗である。   2a and 2b, 20 is a light emitting diode package, 21a, 21b, 21c and 21n are light emitting diode chips, 22 is an anode electrode of the light emitting diode package 20, 23 is a cathode electrode of the light emitting diode package 20, and 24 is a light emitting diode package. 20 substrates. In FIG. 2a, reference numeral 25 denotes a current limiting resistor when the light emitting diode package 20 is used as a light emitting device.

つまり、複数の発光ダイオードチップ２１ａ、２１ｂ、２１ｃ、２１ｎのアノードおよびカソードの双方は発光ダイオードチップの上面に露呈している。従って、発光ダイオードチップ２１ａ、２１ｂ、２１ｃ、２１ｎは発光ダイオードパッケージ２０の基板２４に接着等で固定した後、各アノードは発光ダイオードパッケージ２０のアノード電極２２とワイヤボンディングで導通し、各カソードは発光ダイオードパッケージ２０のカソード電極２３とワイヤボンディングで導通する。   That is, both the anode and the cathode of the plurality of light emitting diode chips 21a, 21b, 21c, and 21n are exposed on the upper surface of the light emitting diode chip. Therefore, after the light emitting diode chips 21a, 21b, 21c, and 21n are fixed to the substrate 24 of the light emitting diode package 20 by bonding or the like, each anode is electrically connected to the anode electrode 22 of the light emitting diode package 20 by wire bonding, and each cathode emits light. The diode package 20 is electrically connected to the cathode electrode 23 by wire bonding.

ワイヤボンディング後の発光ダイオードパッケージ２０は、図１ａ〜図１ｃで説明したように、各発光ダイオードチップ、およびボンディング部を、光透過樹脂でモールドする。   In the light-emitting diode package 20 after wire bonding, as described with reference to FIGS. 1a to 1c, each light-emitting diode chip and the bonding portion are molded with a light transmitting resin.

次に、本発明による発光装置の構成要件の詳細を説明する。以下は、発光ダイオードチップのアノードおよびカソードの配置にかかわらず同じ構成要件である。
図３は、本発明による発光ダイオードチップ選択基準の特性図である。図３において、３０は複数の発光ダイオードチップの順方向電圧−順方向電流特性でＸ軸は順方向電圧、Ｙ軸は順方向電流を示す。符号Ａ、Ｂ、Ｃは発光ダイオードチップの選択基準点である。 Next, details of the configuration requirements of the light emitting device according to the present invention will be described. The following are the same components regardless of the arrangement of the anode and cathode of the light emitting diode chip.
FIG. 3 is a characteristic diagram of a light-emitting diode chip selection criterion according to the present invention. In FIG. 3, 30 is a forward voltage-forward current characteristic of a plurality of light emitting diode chips, where the X axis indicates the forward voltage and the Y axis indicates the forward current. Reference signs A, B, and C are selection reference points for the light-emitting diode chip.

まず、符号Ａ点は、一定電圧ＶＦにおける発光ダイオードチップの定格電流点である。符号Ｂ点は、前記一定電圧ＶＦにおける発光ダイオードチップの定格電流の１／Ｎ点である。符号Ｃ点は、前記一定電圧ＶＦ＋ΔＶにおける発光ダイオードチップの定格電流点である。ここで一定電圧ＶＦは、発光ダイオードチップの一般的な動作順方向電圧範囲の任意の電圧である。ΔＶは、前述の一定電圧ＶＦより高い電圧の差分であって、この差分電圧ΔＶの大きさは、発光ダイオードチップの選択基準値のひとつである。一定電圧ＶＦと差分電圧ΔＶについては、具体的な数値例と併せて後に詳述する。   First, the point A is a rated current point of the light emitting diode chip at a constant voltage VF. The point B is a 1 / N point of the rated current of the light emitting diode chip at the constant voltage VF. The point C is a rated current point of the light emitting diode chip at the constant voltage VF + ΔV. Here, the constant voltage VF is an arbitrary voltage in a general operation forward voltage range of the light-emitting diode chip. ΔV is a voltage difference higher than the aforementioned constant voltage VF, and the magnitude of the difference voltage ΔV is one of the selection reference values of the light emitting diode chip. The constant voltage VF and the differential voltage ΔV will be described in detail later together with specific numerical examples.

つまり、本発明による発光ダイオードパッケージ内に並列接続する発光ダイオードチップの選択基準は、発光ダイオードチップの順方向電圧−順方向電流特性が、前述のＡ、Ｂ、Ｃの３点を通る以下のふたつの条件を満たすことである。
第１特性条件は、発光ダイオードチップの順方向電圧−順方向電流特性がＡ点とＢ点の線分間を横切ること。第２特性条件は、発光ダイオードチップの順方向電圧−順方向電流特性がＡ点とＣ点の線分間を横切ることである。 That is, the selection criteria for the light emitting diode chips connected in parallel in the light emitting diode package according to the present invention are the following two types in which the forward voltage-forward current characteristics of the light emitting diode chips pass through the three points A, B and C described above. It is to satisfy the conditions.
The first characteristic condition is that the forward voltage-forward current characteristic of the light emitting diode chip crosses the line segment between point A and point B. The second characteristic condition is that the forward voltage-forward current characteristic of the light emitting diode chip crosses the line segment between the points A and C.

さらに、具体的な数値例を挙げて説明する。Ａ点、Ｂ点の電圧ＶＦを３Ｖ、また、Ａ点の電流は、発光ダイオードチップの定格電流値１５０ｍＡとする。Ｂ点はＮ＝２として、定格電流値の１／２、つまり７５ｍＡとする。また、ΔＶ＝０．４とする。従って、Ｃ点の電圧は３．４Ｖである。   Furthermore, a specific numerical example will be given and described. The voltage VF at point A and point B is 3 V, and the current at point A is the rated current value 150 mA of the light-emitting diode chip. Point B is N = 2 and is half the rated current value, that is, 75 mA. Further, ΔV = 0.4. Accordingly, the voltage at point C is 3.4V.

この結果、符号３１、３２、３３、３４で示す発光ダイオードチップの順方向電圧−順方向電流特性のうち、３１および３３は第１特性条件と第２特性条件を満たすので選択基準内である。３２は第１特性条件を満たすが、第２特性条件は満たしていない。３４は両方を満たしていない。   As a result, among the forward voltage-forward current characteristics of the light-emitting diode chips indicated by reference numerals 31, 32, 33, and 34, 31 and 33 satisfy the first characteristic condition and the second characteristic condition, and thus are within the selection criteria. 32 satisfies the first characteristic condition, but does not satisfy the second characteristic condition. 34 does not satisfy both.

すなわち、本発明による発光ダイオードパッケージ内に並列接続する発光ダイオードチップの選択基準は、前述のように、Ａ点（３Ｖ、１５０ｍＡ）、Ｂ点（３Ｖ、７５ｍＡ）、Ｃ点（３．４Ｖ、１５０ｍＡ）の３点を定義し、第１特性条件と第２特性条件を満たすことである。   That is, the selection criteria of the light emitting diode chips connected in parallel in the light emitting diode package according to the present invention are point A (3 V, 150 mA), point B (3 V, 75 mA), point C (3.4 V, 150 mA) as described above. ), And satisfy the first characteristic condition and the second characteristic condition.

なお、実際に並列接続の可否を選択するための発光ダイオードチップの測定は、各発光ダイオードチップに定格電流（１５０ｍＡ）と定格電流の１／Ｎの電流、ここでは、定格電流値の１／２（７５ｍＡ）を流し、このときの定格電流の順方向電圧ＶＦＳ、１／２定格電流の順方向電圧ＶＦＨを記録する。このＶＦＨ記録データを基準にＶＦＳがＶＦＨ＋ΔＶ、ここでは、ＶＦＨ＋０．４Ｖ以内の発光ダイオードチップを並列接続可能なランクとするのである。   In addition, the measurement of the light-emitting diode chip for actually selecting whether or not to connect in parallel is performed by measuring each light-emitting diode chip with a rated current (150 mA) and a current that is 1 / N of the rated current, here, 1/2 of the rated current value. (75 mA) is applied, and the forward voltage VFS of the rated current at this time and the forward voltage VFH of the ½ rated current are recorded. Based on this VFH recording data, VFS is VFH + ΔV, in this case, a rank in which light emitting diode chips within VFH + 0.4V can be connected in parallel.

図３にもとづく本発明による発光装置の構成要件をさらに詳細に説明する。
図４は、本発明による複数の発光ダイオードチップ選択基準の特性図である。図４において、４０は複数の発光ダイオードチップの順方向電圧−順方向電流特性で、Ｘ軸は順方向電圧、Ｙ軸は順方向電流を示す。符号４１ａで示す線は発光ダイオードチップの定格電流値、４１ｂで示す線は発光ダイオードチップの１／２定格電流値である。４２、４３、４４、４５、４６、４７、４８は各発光ダイオードチップの順方向電圧−順方向電流特性を示す。 The components of the light emitting device according to the present invention based on FIG. 3 will be described in more detail.
FIG. 4 is a characteristic diagram of a plurality of light emitting diode chip selection criteria according to the present invention. In FIG. 4, reference numeral 40 denotes forward voltage-forward current characteristics of a plurality of light emitting diode chips, where the X axis indicates the forward voltage and the Y axis indicates the forward current. The line denoted by reference numeral 41a is the rated current value of the light emitting diode chip, and the line denoted by 41b is the 1/2 rated current value of the light emitting diode chip. Reference numerals 42, 43, 44, 45, 46, 47, and 48 denote forward voltage-forward current characteristics of the respective light emitting diode chips.

ここで、特性４２と４４は、１／２定格電流値４１ａと交点４２ａ、４４ａで交差し、
定格電流値４１ｂと交点４２ｂ、４４ｂで交差している。また、順方向電圧ＶＦ３において、１／２定格電流値４１ａと定格電流値４１ｂとの間で交差し、かつ、定格電流値４１ｂの順方向電圧ＶＦ３とＶＦ３に差分電圧ΔＶＦ３を加えたＶＦ３＋ΔＶＦ３との間で交差し、先の第１条件と第２条件を満たしているので、同一ランクとなる。 Here, the characteristics 42 and 44 intersect the half rated current value 41a at the intersections 42a and 44a,
It intersects the rated current value 41b at intersections 42b and 44b. In addition, in the forward voltage VF3, the VF3 + ΔVF3 intersects between the ½ rated current value 41a and the rated current value 41b and is obtained by adding the differential voltage ΔVF3 to the forward voltage VF3 and VF3 of the rated current value 41b. Since they intersect each other and satisfy the first condition and the second condition, they have the same rank.

また、特性４７と４８は、１／２定格電流値４１ａと交点４７ａ、４８ａで交差し、定格電流値４１ｂと交点４７ｂ、４８ｂで交差している。また、順方向電圧ＶＦ４において、１／２定格電流値４１ａと定格電流値４１ｂとの間で交差し、かつ、定格電流値４１ｂの順方向電圧ＶＦ４とＶＦ４に差分電圧ΔＶＦ４を加えたＶＦ４＋ΔＶＦ４との間で交差し、先の第１条件と第２条件を満たしているので、同一ランクとなる。   The characteristics 47 and 48 intersect with the half rated current value 41a at the intersections 47a and 48a, and intersect with the rated current value 41b at the intersections 47b and 48b. Further, in the forward voltage VF4, it intersects between the ½ rated current value 41a and the rated current value 41b, and VF4 + ΔVF4 obtained by adding the differential voltage ΔVF4 to the forward voltages VF4 and VF4 of the rated current value 41b. Since they intersect each other and satisfy the first condition and the second condition, they have the same rank.

特性４３、４５、４６は上記条件を満たさないが、ＶＦの基準電圧をずらすことで、基準条件を満たす別なランクに組み入れられる。   The characteristics 43, 45, and 46 do not satisfy the above condition, but are incorporated into another rank that satisfies the reference condition by shifting the reference voltage of VF.

つまり、先に図３にもとづいて述べたＡ点、Ｂ点の順方向電圧ＶＦは、はじめから定義しているのではなく、定格電流印加時の順方向電圧ＶＦＳと１／２定格電流印加時の順方向電圧ＶＦＨを測定後に導かれる数値である。ΔＶは、狭めれば発光ダイオードパッケージ内の電流バラツキは少なくなるが、ランク分けの数が増加する。一例として挙げた０．４Ｖは実用的な値である。   That is, the forward voltage VF at the points A and B described above with reference to FIG. 3 is not defined from the beginning, but the forward voltage VFS when the rated current is applied and when the 1/2 rated current is applied. Is a numerical value derived after measurement of the forward voltage VFH. If ΔV is narrowed, the current variation in the light emitting diode package is reduced, but the number of ranks is increased. As an example, 0.4 V is a practical value.

また、Ｂ点の電流は、一例として挙げたＮ＝２、つまり定格電流の１／２は、この条件で選択し、並列接続した発光ダイオードパッケージ内の各発光ダイオードチップは、上記２条件を満足することにより、定格電流の５０％以上の順方向電流値が流れることを意味する。   In addition, the current at point B is N = 2 as an example, that is, half of the rated current is selected under this condition, and each light emitting diode chip in the light emitting diode package connected in parallel satisfies the above two conditions. This means that a forward current value of 50% or more of the rated current flows.

以上に述べたように、本発明によれば、順方向電圧−順方向電流特性において、Ａ、Ｂ、Ｃの３点を通るふたつの特性条件を選択基準にして、発光ダイオードチップを並列接続することで発光ダイオードパッケージを構成するため、発光ダイオードパッケージ内の発光ダイオードチップのバラツキが少なく、かつ、Ｂ点の電流を定格電流の１／２とすることで、発光ダイオードパッケージ内の発光ダイオードチップの電流は定格の５０％以上の電流値を満足する発光装置を提供できるのである。   As described above, according to the present invention, in the forward voltage-forward current characteristics, the light emitting diode chips are connected in parallel based on the two characteristic conditions passing through the three points A, B, and C as selection criteria. In this way, the light emitting diode package is configured so that the variation of the light emitting diode chips in the light emitting diode package is small and the current at the point B is ½ of the rated current. A light emitting device that satisfies a current value of 50% or more of the rated current can be provided.

次に、本発明の第２の実施形態について図面に基づいて説明する。図５は、本発明による複数の発光ダイオードの直並列回路図である。
図５において、５０は発光ダイオードパッケージ、５１ａ、５１ｂ、５１ｃ、５１ｎは直列発光ダイオード、５２は発光ダイオードパッケージ５０のアノード電極、５３は発光ダイオードパッケージ５０のカソード電極である。 Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a series-parallel circuit diagram of a plurality of light emitting diodes according to the present invention.
In FIG. 5, 50 is a light emitting diode package, 51 a, 51 b, 51 c and 51 n are series light emitting diodes, 52 is an anode electrode of the light emitting diode package 50, and 53 is a cathode electrode of the light emitting diode package 50.

つまり、直列発光ダイオード５１ａ、５１ｂ、５１ｃ、５１ｎの各々は、複数の発光ダイオードチップを基板等の上に直列接続した複合体である。この直列発光ダイオード５１ａ、５１ｂ、５１ｃ、５１ｎも前述の発光ダイオードチップを並列接続して発光ダイオードパッケージを構成する手法と同様な選択基準で直列発光ダイオードの各複合体をランク分けして、ひとつの発光ダイオードパッケージ５０を構成するのである。   That is, each of the series light emitting diodes 51a, 51b, 51c, and 51n is a complex in which a plurality of light emitting diode chips are connected in series on a substrate or the like. The series light emitting diodes 51a, 51b, 51c, and 51n are also ranked according to the same selection criteria as the above-described method of forming the light emitting diode package by connecting the light emitting diode chips in parallel. The light emitting diode package 50 is configured.

すなわち、第２の実施形態においては、直列発光ダイオードを並列接続してひとつの発光ダイオードパッケージを構成するので、発光強度が強く、電流バランスの良い、信頼性の高い発光装置を提供できるのである。   That is, in the second embodiment, since a single light emitting diode package is configured by connecting serial light emitting diodes in parallel, a light emitting device having high emission intensity, good current balance, and high reliability can be provided.

本発明による発光装置の回路図である。1 is a circuit diagram of a light emitting device according to the present invention. 本発明による発光装置の平面図である。It is a top view of the light-emitting device by this invention. 本発明による発光装置の斜視図である。1 is a perspective view of a light emitting device according to the present invention. 本発明による発光装置の他の回路図である。It is another circuit diagram of the light-emitting device by this invention. 本発明による発光装置の他の平面図である。It is another top view of the light-emitting device by this invention. 本発明による発光ダイオードチップ選択基準の特性図である。FIG. 6 is a characteristic diagram of a light emitting diode chip selection criterion according to the present invention. 本発明による複数の発光ダイオードチップ選択基準の特性図である。FIG. 6 is a characteristic diagram of a plurality of light emitting diode chip selection criteria according to the present invention. 本発明による複数の発光ダイオードの直並列回路図である。FIG. 3 is a series-parallel circuit diagram of a plurality of light emitting diodes according to the present invention. 従来の複数の発光ダイオードチップを並列接続した発光ダイオードパッケージの回路図であるIt is a circuit diagram of a light emitting diode package in which a plurality of conventional light emitting diode chips are connected in parallel. 一般的な発光ダイオードチップの順方向電圧と順方向電流の特性図である。FIG. 6 is a characteristic diagram of forward voltage and forward current of a general light emitting diode chip.

符号の説明Explanation of symbols

１０、５０ 発光ダイオードパッケージ
１１ａ、１１ｂ、１１ｃ、２１ａ、２１ｂ、２１ｃ、２１ｎ 発光ダイオードチップ
１２、２２、５２ アノード電極
１３、２３、５３ カソード電極
１４、２４ 基板
１５、２５ 電流制限抵抗
３０、４０ 順方向電圧−順方向電流特性
４１ａ 定格電流値
４１ｂ １／２定格電流値
５１ａ、５１ｂ、５１ｃ、５１ｎ 直列発光ダイオード
Ａ、Ｂ、Ｃ 選択基準点
ＶＦ、ＶＦ３、ＶＦ４ 順方向電圧
ΔＶ、ΔＶＦ３、ΔＶＦ４ 差分電圧 10, 50 Light emitting diode package 11a, 11b, 11c, 21a, 21b, 21c, 21n Light emitting diode chip 12, 22, 52 Anode electrode 13, 23, 53 Cathode electrode 14, 24 Substrate 15, 25 Current limiting resistor 30, 40 Directional voltage-forward current characteristic 41a Rated current value 41b 1/2 Rated current value 51a, 51b, 51c, 51n Series light emitting diodes A, B, C Selection reference points VF, VF3, VF4 Forward voltage ΔV, ΔVF3, ΔVF4 Difference Voltage

Claims (4)

順方向電圧−順方向電流特性を選択的に揃えた複数の発光ダイオードチップを並列接続して発光ダイオードパッケージを構成する発光装置において、一定電圧ＶＦにおける発光ダイオードチップの定格電流点をＡ、前記一定電圧ＶＦにおける発光ダイオードチップの定格電流の１／Ｎ点をＢ、前記一定電圧ＶＦ＋ΔＶにおける発光ダイオードチップの定格電流点をＣとし、被選択発光ダイオードチップの選択第１特性条件は、前記被選択発光ダイオードチップの順方向電圧−順方向電流特性がＡ−Ｂの線分と交わり、第２特性条件は、前記被選択発光ダイオードチップの順方向電圧−順方向電流特性がＡ−Ｃの線分と交わる、ふたつの特性条件を選択基準にして発光ダイオードパッケージを構成したことを特徴とする発光装置。   In a light-emitting device in which a light-emitting diode package is configured by connecting in parallel a plurality of light-emitting diode chips having a selective forward voltage-forward current characteristic, A is a rated current point of the light-emitting diode chip at a constant voltage VF. The 1 / N point of the rated current of the light emitting diode chip at the voltage VF is B, the rated current point of the light emitting diode chip at the constant voltage VF + ΔV is C, and the selected first characteristic condition of the selected light emitting diode chip is the selected light emission. The forward voltage-forward current characteristic of the diode chip intersects with the line segment AB, and the second characteristic condition is that the forward voltage-forward current characteristic of the selected light emitting diode chip is the line segment AC. A light-emitting device comprising a light-emitting diode package based on selection of two intersecting characteristic conditions. 前記発光ダイオードチップの定格電流の１／Ｎは、Ｎ＝２であることを特徴とする請求項１に記載の発光装置。   The light emitting device according to claim 1, wherein 1 / N of the rated current of the light emitting diode chip is N = 2. 前記ΔＶは０．４Ｖ以下であることを特徴とする請求項１、および請求項２に記載の発光装置。   The light emitting device according to claim 1, wherein the ΔV is 0.4 V or less. 複数の発光ダイオードチップを直列接続した発光ダイオードパッケージを複数個並列接続して構成する発光装置において、前記発光装置を構成する複数の発光ダイオードパッケージは、順方向電圧−順方向電流特性の前記第１、および第２のふたつの特性条件により、あらかじめ順方向電圧を選択的に揃えたことを特徴とする発光装置。   In the light emitting device configured by connecting a plurality of light emitting diode packages in which a plurality of light emitting diode chips are connected in series, the plurality of light emitting diode packages constituting the light emitting device have the forward voltage-forward current characteristics. And a light emitting device in which forward voltages are selectively arranged in advance according to the second two characteristic conditions.
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