JP2008270256A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the generation of cracks in a wiring layer of a multilayer wiring while reducing a wiring resistance in a power element in the multilayer wiring when an electrode of a semiconductor device is extended to the uppermost layer by the multilayer wiring in a composite semiconductor device consisting of the power element and other semiconductor devices. <P>SOLUTION: A source electrode 32 and a drain electrode 31 of a power MOS transistor in a first region 11 of a stacked wiring 20 are each formed as a single electrode without using a plurality of minute via holes on wiring layers 23-25 upper than a second wiring layer 22 of the stacked wiring 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a multilayer wiring and a manufacturing method thereof.

  Conventionally, for example, Patent Document 1 proposes a power composite integrated semiconductor device in which a power element and a control circuit are formed on a surface layer portion of one silicon substrate. In such a semiconductor device, a large number of wiring layers made of insulating films are stacked on a silicon substrate. In each wiring layer, a minute via hole is provided in the insulating film, and a wiring is formed in the via hole, so that the lower wiring layer and the upper wiring layer can be electrically connected. Yes.

A plurality of wiring layers are stacked on the power element and the control circuit, so that the power element electrode and the control circuit electrode are respectively stretched from the surface layer portion of the silicon substrate to the uppermost layer of the wiring layer. Such multilayer wiring on the power element and multilayer wiring on the control circuit are formed in the same process. Thus, the electrode extended to the uppermost layer is connected to an electric circuit or the like.
JP 2006-5325 A

  However, in the above conventional technique, a large number of minute via holes are formed in each wiring layer of the multilayer wiring, and the wiring is formed in each via hole. Therefore, the resistance of the wiring in the via hole is increased. In particular, since the power element handles a large current, the loss of the semiconductor device itself increases as the wiring resistance increases.

  Therefore, as a means for reducing the wiring resistance of the power element, there is a method of increasing the film thickness of the upper layer wiring that does not affect the miniaturization of the control circuit. However, if the passivation protection film is formed after the thick film wiring is formed in the uppermost layer of the wiring layers, there arises a problem that a crack is generated in the passivation protection film due to a stress difference between the passivation protection film and the thick film wiring.

  As another means for reducing the wiring resistance of the power element, there is a method of directly forming a wire bond on the upper part of the cell of the power element. However, there is a problem that cracks occur in the insulating film constituting the wiring layer at the time of wire bonding.

  In view of the above points, the present invention reduces the wiring resistance of a power element in the multilayer wiring when the electrode of the semiconductor device is extended to the uppermost layer by the multilayer wiring in a composite semiconductor device of a power element and another semiconductor device. However, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent cracks from being generated in the wiring layer of the multilayer wiring.

  In order to achieve the above object, according to the present invention, a power element is formed in a first region (11) of a semiconductor substrate (1), and a semiconductor device different from the power element is formed in a place other than the first region (11). In this composite semiconductor device, on the semiconductor substrate (1), a plurality of wiring layers (21 to 25) and an uppermost wiring layer (of the plurality of wiring layers (21 to 25)) ( 25) A laminated wiring (20) constituted by the passivation protection film (26) formed thereon is formed, and the first and second layers from the semiconductor substrate (1) side among the plurality of wiring layers (21 to 25) are formed. The upper wiring layers (21, 22) are used to lead the power element and the electrode of the semiconductor device different from the power element to the upper wiring layers (23 to 25), respectively. Of (20) In the first region (11), at least two wiring layers (23 to 25) and a passivation protective film (26) above the second wiring layer (22) among the plurality of wiring layers (21 to 25) are opened. In addition, a drain electrode (31) and a source electrode (32) of the power element are formed in each opening, respectively.

  Thereby, since the drain electrode (31) and the source electrode (32) can be provided as one wiring over each wiring layer (23-25), each wiring resistance of the drain electrode (31) and the source electrode (32) is reduced. Can be small.

  Further, since the drain electrode (31) and the source electrode (32) are formed at the location where the passivation protection film (26) is opened, the passivation protection film (26), the drain electrode (31) and the source electrode (32) are formed. And the stress from the drain electrode (31) and the source electrode (32) applied to the passivation protective film (26) can be reduced. Therefore, the generation of cracks in the passivation protective film (26) can be suppressed.

  Furthermore, since the drain electrode (31) and the source electrode (32) are formed in a thick film over the number of wiring layers (23 to 25), a wire is connected to the drain electrode (31) and the source electrode (32). Even if it bonds, it can suppress that a crack generate | occur | produces in the wiring layer (21, 22) of a 1st area | region (11).

  In such a case, the drain electrode pad (22c) and the source electrode pad (22d) are formed on the second wiring layer (22), and the drain electrode (31) is formed as the drain electrode pad (22c). The source electrode (32) can be formed on the source electrode pad (22d).

  Moreover, it can form so that the upper end surface of a drain electrode (31) and a source electrode (32) may not protrude from the uppermost wiring layer (25) among several wiring layers (21-25). Accordingly, the drain electrode (31) and the source electrode (32) can be prevented from coming into contact with the passivation protection film (26), and the passivation protection film (26) is caused by a stress difference between each electrode and the passivation protection film (26). ) Can be prevented from generating cracks.

  Furthermore, the upper end surfaces of the drain electrode (31) and the source electrode (32) can be formed so as to protrude from the passivation protective film (26) constituting the multilayer wiring (20). Thereby, the heat dissipation of a power element can be improved via a drain electrode (31) and a source electrode (32).

  In manufacturing the semiconductor device as described above, a step of preparing a power element and a semiconductor device different from the power element on the semiconductor substrate (1), and a plurality of wiring layers (21 on the semiconductor substrate (1) are prepared. 25) and a passivation wiring film (26) formed by the passivation protection film (26), and in the multilayer wiring (20), the second wiring layer among the plurality of wiring layers (21-25) At least two wiring layers (23 to 25) and a passivation protection film (26) above (22) are opened, and a drain electrode (31) and a source electrode (32) of the power element are formed in each opening. Process.

  In this case, in the step of opening at least two wiring layers (23 to 25) and the passivation protection film (26) above the second wiring layer (22), a resist (50) is formed on the passivation protection film (26). After forming the drain electrode (31) and the source electrode (32), the passivation protection film (26) is patterned using the resist (50) as a mask, and then the patterned passivation protection film (26) is formed. ) As a mask, the wiring layers (23 to 25) above the second wiring layer (22) among the plurality of wiring layers (21 to 25) can be opened.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention. As shown in this figure, in the semiconductor device, for example, three semiconductor devices are provided on an SOI substrate 1. In this embodiment, a power MOS transistor such as an LDMOS is formed in the first region 11 of the SOI substrate 1, a CMOS transistor is formed in the second region 12, and a BIP (bipolar) transistor is formed in the third region 13. Yes. The SOI substrate 1 corresponds to a semiconductor substrate of the present invention. The power MOS transistor corresponds to the power element of the present invention.

  Each semiconductor device is element-isolated by a trench 2 provided in the SOI substrate 1 and a LOCOS oxide film 3 formed on the trench 2. That is, the semiconductor device shown in FIG. 1 is a composite type in which a plurality of types of transistors are formed on one SOI substrate 1.

  The power MOS transistor formed in the first region 11 has a drain region 11a and a source region 11b on the surface layer portion of the SOI substrate 1, and a gate electrode 11c on the source region 11b. The CMOS transistor formed in the second region 12 has an nMOS region 12 a and a pMOS region 12 b in the surface layer portion of the SOI substrate 1. In addition, the BIP transistor formed in the third region 13 has a source region and a drain region that constitute the BIP transistor.

  In such a semiconductor device, a laminated wiring 20 for electrically connecting each semiconductor device is provided on the SOI substrate 1. In the present embodiment, the laminated wiring 20 is composed of five wiring layers 21 to 25 and an uppermost passivation protection film 26. Note that the five layers are examples, and the number of wiring layers varies depending on the design.

Each of the wiring layers 21 to 25 is made of an insulating film such as SiO ₂ . The passivation protection film 26 is made of a material such as SiN.

  Via holes 21a are provided in the first wiring layer 21 of the multilayer wiring 20 over the regions 11 to 13 so as to be connected to the contacts of the semiconductor devices. The wiring in each via hole 21 a is connected to a pad 21 b provided on the surface of the wiring layer 21.

  In the second wiring layer 22, via holes 22a and pads 22b are formed over the regions 11 to 13, and the wiring in each via hole 21a of the first wiring layer 21 is electrically connected to the second pad 22b. Connected. In the present embodiment, in order to extend the electrode of the semiconductor device to the upper layer, the via hole and the pad of at least the first wiring layer 21 and the second wiring layer 22 are necessary.

  As for the layer above the third wiring layer 23, no via hole or the like is formed in the first region 11, and the passivation protection film 26 and the wiring layers 23 to 25 are formed on the second wiring layer 22. The electrode pad 22c is opened at the bottom, and the drain electrode 31 is formed in the opening. Similarly, the passivation protection film 26 and the wiring layers 23 to 25 are opened with the source electrode pad 22d formed on the second wiring layer 22 as a bottom, and the source electrode 32 is formed in the opening.

  On the other hand, in the second and third regions 12 and 13, the layer above the third wiring layer 23 has a structure in which the electrode is extended to the upper layer by via holes and pads as in the first and second layers. ing. A part of the uppermost passivation protection film 26 is opened, and pads 40 for the CMOS transistor and the BIP transistor are provided. The above is the overall configuration of the semiconductor device according to the present embodiment.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. First, an SOI substrate 1 is prepared, and an element isolation trench 2 and a LOCOS oxide film 3 are formed on the SOI substrate 1. And what formed the semiconductor device in each area | region 11-13 is prepared.

  Next, in the step shown in FIG. 2A, a first wiring layer 21 is formed, and via holes 21a are formed in the wiring layer 21 so as to be able to contact each semiconductor device in each region 11-13. Wiring is provided in the via hole 21a. Then, a pad 21b is formed on the wiring layer 21 so as to be connected to each via hole 21a.

  Similarly, a second wiring layer 22 is formed in each of the regions 11 to 13, and a via hole 22 a and a pad 22 b connected to the pad 21 b on the first wiring layer 21 are formed. In this case, in the first region 11 of the second wiring layer 22, a drain electrode pad 22c connected to the drain region 11a of the power MOS transistor and a source electrode pad 22d connected to the source region 11b are respectively provided. Form.

  In the step shown in FIG. 2B, a layer above the third wiring layer 23 is formed. In this embodiment, the wiring layers 23 to 25 are formed, and the passivation protection film 26 is formed on the fifth wiring layer 25. In this case, in the first region 11, only a via hole is formed above the third wiring layer 23 in order to extend the gate electrode 11 c to the upper layer. On the other hand, in the second and third regions 12 and 13, via holes and the like are formed in the same manner as the first and second layers.

  Then, after forming up to the uppermost wiring layer 25, a passivation protection film 26 is formed. In this state, as shown in FIG. 2B, no via hole or the like is formed in the first region 11 and is formed only in the second and third regions 12 and 13.

  In the step shown in FIG. 2C, the drain electrode 31 and the source electrode 32 are formed in the first region 11. Specifically, a resist (not shown) is formed on the passivation protection film 26, and a location facing the drain electrode pad 22c and the source electrode pad 22d is opened. Then, the passivation protection film 26 and the wiring layers 23 to 25 are respectively opened by etching the third to fifth wiring layers 23 to 25. Subsequently, the drain electrode 31 is formed on the drain electrode pad 22c in each opening by plating or CVD, and the source electrode 32 is formed on the source electrode pad 22d.

  Then, a part of the passivation protection film 26 in the third region 13 is opened to provide a pad 40 for the CMOS transistor and the BIP transistor. Thus, the semiconductor device shown in FIG. 1 is completed.

  In such a semiconductor device, the source electrode 32 and the drain electrode 31 of the power MOS transistor in the stacked wiring 20 are not used in the wiring layers 23 to 25 above the second wiring layer 22 without using a plurality of fine via holes. One electrode is used. Thereby, each wiring resistance of the drain electrode 31 and the source electrode 32 can be made small.

  In addition, since the passivation protective film 26 is formed and then the passivation protective film 26 is opened to form the drain electrode 31 and the source electrode 32, the area where the drain region 11a and the source electrode 32 and the passivation protective film 26 are in contact with each other can be reduced. can do. Thereby, the stress from the drain electrode 31 and the source electrode 32 concerning the passivation protective film 26 can be reduced, and the generation | occurrence | production of the crack of the passivation protective film 26 can be suppressed by extension.

  Furthermore, since the drain electrode 31 and the source electrode 32 are formed in a thick film, even if wire bonding is performed on the power MOS transistor, the occurrence of cracks in the wiring layers 21 and 22 in the first region 11 can be suppressed.

(Second Embodiment)
In the present embodiment, only different parts from the first embodiment will be described. This embodiment is characterized in that the drain electrode pad 22c and the source electrode pad 22d shown in FIG. 1 are eliminated.

  FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. As shown in this figure, in the semiconductor device according to this embodiment, the drain electrode 31 and the source electrode 32 are formed on the second wiring layer 22 in the first region 11.

  In the present embodiment, since the drain electrode pad 22c and the source electrode pad 22d are not formed on the second wiring layer 22, as described above, the drain electrode 31 and the source electrode 32 are formed in the second layer. It is formed even in a via hole 22 a provided in the wiring layer 22. In other words, the drain electrode 31 and the source electrode 32 are directly connected to the pad 21 b provided on the first wiring layer 21.

  Next, a method for manufacturing the semiconductor device shown in FIG. 3 will be described with reference to FIG. FIG. 4 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. First, an SOI substrate 1 on which each semiconductor device is formed is prepared. In the step shown in FIG. 4A, the first wiring layer 21 is formed on the SOI substrate 1. A via hole 21 a that contacts each semiconductor device is formed in the wiring layer 21, and a pad 21 b is formed on the wiring layer 21.

  Subsequently, in the step shown in FIG. 4B, via holes and the like are formed in the wiring layers 22 to 25 above the second layer only in the second and third regions 12 and 13, and the regions 11 to 13 are formed. The wiring layers 22 to 25 and the passivation protection film 26 that are higher than the second layer are formed. As a result, as shown in FIG. 4B, no via hole or the like is formed in the first region 11 of the wiring layers 22 to 25.

  In the step shown in FIG. 4C, the formation positions of the drain electrode 31 and the source electrode 32 in the first region 11 in the laminated passivation protective film 26 and the third to fifth wiring layers 23 to 25 are determined. A via hole 22a is formed in the second wiring layer 22 so as to reach the first pad 21b. Thereafter, the drain electrode 31 and the source electrode 32 are formed in the via hole 22 a and in the openings of the wiring layers 23 to 25 and the passivation protection film 26. Thus, the drain electrode 31 and the source electrode 32 can be directly connected to the pad 21b provided on the first wiring layer 21.

  Then, a part of the passivation protection film 26 in the third region 13 is opened, and a pad 40 of a CMOS transistor and a BIP transistor is provided, thereby completing the semiconductor device shown in FIG.

  As described above, in the first region 11, only the via hole 22a is formed in the second wiring layer 22, and the drain electrode 31 and the source electrode 32 are directly formed in the via hole 22a. The wiring resistance of the source electrode 32 can be further reduced.

(Third embodiment)
In the present embodiment, only different parts from the second embodiment will be described. The present embodiment is characterized in that a via hole 22a is formed in the second wiring layer 22, and a wiring is formed in the via hole 22a.

  FIG. 5 is a schematic cross-sectional view of a semiconductor device according to the third embodiment of the present invention. As shown in this figure, in the semiconductor device according to the present embodiment, in the first region 11, the via hole 22a is formed in the second wiring layer 22, and the wiring is formed in the via hole 22a. ing. The drain electrode 31 and the source electrode 32 formed above the third wiring layer 23 are connected to the wiring in the via hole 22a provided in the second wiring layer 22.

  Next, a method for manufacturing the semiconductor device shown in FIG. 5 will be described with reference to FIG. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. First, an SOI substrate 1 on which each semiconductor device is formed is prepared.

  Next, in the step shown in FIG. 6A, the first wiring layer 21 and the second wiring layer 22 are formed. In this case, for the second wiring layer 22, a via hole 22a is formed and a wiring is formed in the via hole 22a.

  In the step shown in FIG. 6B, an upper layer than the third wiring layer 23 is formed. In this case, for the second and third regions 12 and 13, a pad 22b is formed on the second wiring layer 22 so as to be electrically connected to an upper via hole or the like. For the first region 11, only an insulating film is formed without forming a via hole or the like, as in the above embodiments.

  In the step shown in FIG. 6C, the drain electrode 31 and the source connected to the via hole 22 a of the second wiring layer 22 by opening an upper layer from the third wiring layer 23 in the first region 11. The electrode 32 is formed. Thereafter, a part of the passivation protection film 26 in the third region 13 is opened to complete the semiconductor device shown in FIG.

  As described above, in the first region 11, the via hole 22 a is formed in the second wiring layer 22 and the wiring is formed in the via hole 22 a, and the drain electrode 31 and the source electrode are formed above the third wiring layer 23. 32 can be provided.

(Fourth embodiment)
In the present embodiment, only different portions from the above embodiments will be described. In each of the above embodiments, when the drain electrode 31 and the source electrode 32 are formed in the first region 11, a resist is formed and opened on the passivation protection film 26, and the resist is used as a mask from the third wiring layer 23. Although the upper layer is opened, the present embodiment is characterized in that the passivation protection film 26 is used as a mask.

  FIG. 7 is a view showing a manufacturing process of the semiconductor device according to the present embodiment. First, what completed the process of FIG.2 (b) is prepared. In the step shown in FIG. 7A, a resist 50 is formed on the passivation protection film 26, and is patterned so that the locations where the drain electrode 31 and the source electrode 32 are to be formed are opened.

  Subsequently, in the step shown in FIG. 7B, the passivation protective film 26 is patterned using the resist 50 formed in the step shown in FIG. 7A as a mask.

  In the step shown in FIG. 7C, the wiring layers 23 to 25 are opened by etching or the like using the passivation protective film 26 patterned in the step shown in FIG. 7B as a mask.

  Thereafter, the drain electrode 31 and the source electrode 32 can be formed in the first region 11 by performing the process shown in FIG. Thus, an opening can be formed in the first region 11 using the passivation protection film 26 as a mask.

(Fifth embodiment)
In the present embodiment, only different portions from the above embodiments will be described. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention. As shown in this figure, the upper end surfaces of the drain electrode 31 and the source electrode 32 are formed below the passivation protection film 26. In other words, each upper end surface of the drain electrode 31 and the source electrode 32 is formed only up to the fifth wiring layer 25. According to this, the drain electrode 31 and the source electrode 32 have a structure that is not in contact with the passivation protection film 26.

  That is, for example, the drain electrode 31 such as Al or the source electrode 32 and the passivation protection film 26 such as SiN have a large stress difference. Therefore, by forming the semiconductor device so as not to contact each other as described above, It is possible to prevent the passivation protective film 26 from cracking.

(Sixth embodiment)
In the present embodiment, only different portions from the above embodiments will be described. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the sixth embodiment of the present invention. As shown in this figure, in this embodiment, the upper end surfaces of the drain electrode 31 and the source electrode 32 protrude from the passivation protection film 26. Thereby, the heat dissipation of the power MOS transistor can be improved. Thus, the drain electrode 31 and the source electrode 32 can be thickened.

(Other embodiments)
The source electrode 32 and the drain electrode 31 are not limited to two places as in the above embodiment. For example, two source electrodes 32 and three drain electrodes 31 may be provided in accordance with the layout.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 1. It is a schematic sectional drawing of the semiconductor device which concerns on 2nd Embodiment of this invention. FIG. 4 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 3. It is a schematic sectional drawing of the semiconductor device which concerns on 3rd Embodiment of this invention. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 5. It is the figure which showed the manufacturing process of the semiconductor device which concerns on 4th Embodiment of this invention. It is a schematic sectional drawing of the semiconductor device which concerns on 5th Embodiment of this invention. It is a schematic sectional drawing of the semiconductor device which concerns on 6th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... SOI substrate, 11 ... 1st area | region, 12 ... 2nd area | region, 13 ... 3rd area | region, 20 ... Laminated wiring, 21-25 ... Wiring layer, 26 ... Passivation protective film, 22c ... Pad for drain electrodes, 22d ... Source electrode pad, 31... Drain electrode, 32... Source electrode, 50.

Claims (6)

A composite semiconductor device in which a power element is formed in a first region (11) of a semiconductor substrate (1), and a semiconductor device different from the power element is formed in a place other than the first region (11). There,
On the semiconductor substrate (1), a plurality of wiring layers (21-25) and a passivation protective film (26) formed on the uppermost wiring layer (25) among the plurality of wiring layers (21-25). ), And the first and second wiring layers (21, 22) from the semiconductor substrate (1) side among the plurality of wiring layers (21-25). Is used to lead the power element and the electrode of the semiconductor device different from the power element to the upper wiring layers (23 to 25),
Of the stacked wiring (20), in the first region (11), the wiring layers (23-25) above the second wiring layer (22) of the plurality of wiring layers (21-25). The passivation protection film (26) has at least two openings, and the drain electrode (31) and the source electrode (32) of the power element are formed in each opening. A drain electrode pad (22c) and a source electrode pad (22d) are respectively formed on the second wiring layer (22), and the drain electrode (31) is the drain electrode pad (22). The semiconductor device according to claim 1, wherein the source electrode (32) is formed on the source electrode pad (22d). The upper end surfaces of the drain electrode (31) and the source electrode (32) are formed so as not to protrude from the uppermost wiring layer (25) of the plurality of wiring layers (21 to 25). The semiconductor device according to claim 1 or 2. The upper end surfaces of the drain electrode (31) and the source electrode (32) are formed so as to protrude from the passivation protection film (26) constituting the multilayer wiring (20). 3. The semiconductor device according to 1 or 2. A method of manufacturing a semiconductor device according to any one of claims 1 to 4,
Preparing a semiconductor device different from the power element and the power element on the semiconductor substrate (1);
Forming the laminated wiring (20) constituted by the plurality of wiring layers (21 to 25) and the passivation protection film (26) on the semiconductor substrate (1);
In the laminated wiring (20), at least the wiring layers (23-25) above the second wiring layer (22) of the plurality of wiring layers (21-25) and the passivation protection film (26) are provided. A method for manufacturing a semiconductor device, comprising: two openings, and the step of forming the drain electrode (31) and the source electrode (32) of the power element in each opening. In the step of opening at least two wiring layers (23 to 25) and the passivation protection film (26) above the second wiring layer (22), a resist (50) is formed on the passivation protection film (26). The formation of the drain electrode (31) and the source electrode (32) is opened, and the passivation protective film (26) is patterned using the resist (50) as a mask. Using the passivation protective film (26) as a mask, the wiring layers (23-25) above the second wiring layer (22) among the plurality of wiring layers (21-25) are opened. A method for manufacturing a semiconductor device according to claim 5.

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