JP2008263072A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus wherein capacity coupling of signal lines provided in adjacent columns with each other is reduced even when pixel and column signal output circuit is refined and the degradation of image characteristics is suppressed. <P>SOLUTION: The first signal line VLA1 and second signal line VLB1 of the first column are respectively connected to capacitance electrodes CTA1 and CLA1. The interval of the second signal line VLB1 of the first column and the first signal line VLA2 of the second column is set such that an interval D2 between a second wiring part WP2 and the first signal line VLA2 is larger than an interval D1 between a first wiring part WP1 and the first signal line VLA2. By this configuration, parasitic capacitance CcA1 between the second signal line VLB1 of the first column and the first signal line VLA2 of the second column is reduced and interference between respective column signals is suppressed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device used for a digital still camera, a digital video camera, or the like.

  In recent years, various signal readout methods for CMOS image sensors have been proposed. Among them, as a general method, a “column parallel output method” is known in which pixels for one row are selected from the pixel array, and signals generated by the selected pixels for one row are simultaneously read in the column direction. Yes.

  Furthermore, there are various variations in the column parallel output method depending on the configuration of the signal output circuit included in the CMOS image sensor. The pixel output is sampled with a switched capacitor, and the pixel signal is provided for each column. A method using an amplifier and a method using an AD converter provided for each column are known. For example, Patent Document 1 describes a solid-state imaging device having an amplifier (single-end amplifier) for each column.

  In recent years, the pixel size of CMOS image sensors has been continually miniaturized. As the pixel size becomes finer, the pixel output level obtained from each pixel also becomes smaller. Therefore, it is necessary to increase the gain of an amplifier that amplifies the pixel output in order to prevent a reduction in photographing sensitivity. For example, Patent Document 1 discloses a solid-state imaging device that amplifies pixel output using a column amplifier provided for each column and an output amplifier in order to amplify the pixel output.

  Hereinafter, the conventional solid-state imaging device described in Patent Document 1 will be briefly described with reference to the drawings.

  FIG. 9 is a diagram illustrating a schematic configuration of a conventional solid-state imaging device described in Patent Document 1. In FIG.

  The solid-state imaging device shown in FIG. 9 includes a pixel array 91, a timing generator 92, a vertical scanning circuit 93, a column reading unit 95, an output circuit 94, and a horizontal scanning circuit 96.

  The pixel array 91 is a CMOS sensor array in which a plurality of pixels GS made of CMOS sensors are arranged in the column direction. Light from a subject condensed by a lens system (not shown) is incident on the pixel array 91.

  The vertical scanning circuit 93 scans the pixel array 91 based on the address signal and control signal supplied from the timing generator 92. In the example of FIG. 9, the vertical scanning circuit 93 drives the horizontal signal lines L1 to Ln to read out the pixel signals for one row from the pixels arranged in the effective area according to the column parallel method. Select in order.

  More specifically, first, the vertical scanning circuit 93 controls a supply pulse to the horizontal signal line of the selected row, and outputs a reset level signal from each pixel GS to each of the vertical signal lines VL1 to VLm. (So-called P-phase reading). Next, the vertical scanning circuit 93 controls the supply pulse to the horizontal signal line and outputs pixel signals corresponding to the accumulated charges of the photodiodes to the vertical signal lines VL1 to VLm (so-called D-phase reading). The vertical scanning circuit 93 sequentially performs the same readout process for each row of the pixel array 91.

  Note that pixel signals are read from the selected pixels GS for one row during a horizontal blanking period within one horizontal period. That is, in each horizontal blanking period, pixel signals are output in parallel from the pixels GS in each row selected by the vertical scanning circuit 93 to the vertical signal lines VL1 to VLm.

  Signals output from the pixels GS for one row are output to the column readout unit 95 via the vertical signal lines VL1 to VLm.

  The column reading unit 95 includes a plurality of amplifiers AP, limiters LM, and switches SW provided corresponding to the vertical signal lines VL1 to VLm. The amplifier AP is, for example, a charge integration amplifier including a capacitive element, a switch element, and a single end amplifier. The amplifier AP functions as a CDS (Correlated Double Sampling) circuit and samples a pixel signal. Specifically, the amplifier AP samples the difference between the P-phase read level (reset level) and the D-phase read level (data level) as a pixel signal, and outputs the sampled pixel signal. The output voltage of the amplifier AP is controlled to a predetermined level by the limiter LM.

  In the horizontal transfer period within the horizontal period, when the horizontal scanning circuit 96 sequentially selects the switch SW, the pixel signals for one row sampled by the column reading unit 95 are the horizontal signal lines HL1 to HL3 multiplexed by the multiplexer MPX. Are sequentially output to the output circuit 4 through any one of these.

  The three horizontal signal lines HL1 to HL3 are provided because the three horizontal signal lines HL1 to HL3 are used in order even when the driving capability of the amplifier AP arranged for each column is relatively small. Therefore, the pixel signals can be horizontally transferred in parallel.

  The output circuit 4 performs an AGC process, a clamp process, or the like on the signal output from the column reading unit 95 to generate a serial image signal for one row, or outputs an A / A signal to the signal output from the column reading unit 95. D conversion or the like is performed to generate a digital image signal. The output circuit 94 may perform digital gain processing, white balance processing, and the like as digital signal processing.

In the solid-state imaging device shown in FIG. 9, the vertical scanning circuit 93, the horizontal scanning circuit 96, the column reading unit 95, and the output circuit 94 operate as described above in accordance with the signal supplied from the timing generator 92. As a result, the captured image signal is output to the subsequent circuit.
JP 2005-252529 A

  As described above, the pixel size of the CMOS image sensor is rapidly miniaturized due to the demand for higher image quality and reduced device size. However, unlike semiconductor devices for other applications, as a requirement unique to the solid-state imaging device, it is necessary to reduce the size of the column circuit provided for each pixel column in accordance with the reduction rate of the pixel size. Hereinafter, this point will be specifically described.

  FIG. 10 is a configuration example of the “Y” portion shown in FIG. 9 and shows a layout when the unit cell width XH1 of the column circuit is larger than the unit cell width XP of the pixel. In FIG. 10, the horizontal signal lines HL <b> 1 to HL <b> 3 are shown as a single line for ease of explanation.

  When the unit cell width XH1 of the column circuit becomes larger than the unit cell width XP of the pixel as a result of reducing only the pixel size, as shown in FIG. 10, the wiring lengths of the vertical signal lines VL1 and VL2 are different, and FPN (Fixed (Pattern Noise: fixed pattern noise).

  FIG. 11 is a diagram illustrating another layout example of the “Y” portion shown in FIG. 9 and showing a layout when the unit cell width XH2 of the column circuit is equal to or smaller than the unit cell width XP of the pixel.

  As described above, it is not preferable in terms of image quality of the solid-state imaging device to reduce only the unit cell width XP of the pixel GS without changing the unit cell width XH1 of the column circuit. Therefore, as shown in FIG. 11, it is necessary to reduce the unit cell width XH2 of the column circuit in accordance with the reduction ratio of the pixel GS. If the unit cell width XH2 of the column circuit is equal to or smaller than the unit cell width XP of the pixel GS, the wiring lengths of the vertical signal lines VL1 and VL2 can be made the same.

  However, when the element constants of the elements included in the column circuit are constant, if the unit cell width XH2 of the column circuit is simply reduced, the layout of the column circuit inevitably extends in the column direction (L2> L1). . Then, as the unit cell width XH2 of the column circuit is reduced, not only the interval between the adjacent vertical signal lines VL1 and VL2 is narrowed, but also the distance in which the adjacent vertical signal lines VL1 and VL2 run in parallel is increased. As a result, due to capacitive coupling between adjacent vertical signal lines, a pixel signal in a certain column receives interference from a pixel signal in the adjacent column, leading to degradation of image characteristics.

  Therefore, an object of the present invention is to provide a solid-state imaging device having excellent image characteristics even when pixels and column circuits are miniaturized.

  A solid-state imaging device according to the present invention includes a plurality of pixels arranged in a matrix, a plurality of column signal output circuits provided for each pixel column, and a plurality of first elements connected to circuit elements included in the column signal output circuit. A plurality of second signal lines including one signal line, a first wiring portion connected to a circuit element in the same column, and a second wiring portion extending along the first signal line in the adjacent column. The distance between the first signal line and the second wiring part adjacent to each other across the boundary of the column signal output circuit is larger than the distance between the first signal line and the first wiring part adjacent to each other across the boundary. Have

  The first and second wiring portions may extend in parallel with the first signal line, and the second signal line may further include a connection portion that connects the first and second wiring portions.

  Each circuit element may include a pair of electrodes. In this case, the first signal line is connected to one of the electrodes via a contact, and the first wiring portion included in the second signal line is separated from the connection point with one of the first signal line and the electrode by a predetermined distance. In position, it may be connected to the other of the electrodes via a contact.

  The first and second wiring portions and the connection portion may be formed in the same wiring layer as the first signal line.

  Alternatively, the first and second wiring portions and the connection portion may be formed in a wiring layer different from the first signal line.

  In this case, the first and second wiring portions and the connection portion may be formed in a wiring layer one above the wiring layer in which the first signal line is formed.

  The first and second wiring portions and the connection portion may be formed in a wiring layer two above the wiring layer in which the first signal line is formed.

  The circuit element may be a capacitor.

  A plurality of color filters provided for each pixel may be further provided.

  The color filter array may be a Bayer array in which three colors of red, blue, and green are arranged in a checkered pattern.

  According to the present invention, since the capacitive coupling between the first signal line and the second signal line adjacent to each other across the boundary of the column signal output circuit is reduced, the size of the pixel and the column signal output circuit is reduced, and It is possible to realize a solid-state imaging device in which deterioration of image characteristics is suppressed.

(Configuration common to each embodiment)
FIG. 1 is a diagram illustrating an example of a schematic configuration of a solid-state imaging device according to each embodiment of the present invention.

  A solid-state imaging device 10 illustrated in FIG. 1 includes a pixel array 1 including a plurality of pixels PX arranged in a row direction and a column direction, a plurality of column signal output circuits S1 to Sm provided for each pixel column, and a pixel column A plurality of first signal lines VLA1 to VLAm provided for each, and a plurality of second signal lines VLB1 to VLBm electrically connected to each of the first signal lines VLA1 to VLAm.

  Further, the solid-state imaging device 10 includes a vertical scanning circuit 3 that sequentially selects a plurality of pixel rows in the pixel array 1, a horizontal scanning circuit 8 that sequentially selects column signal output circuits S1 to Sm, and a horizontal scanning circuit 8. The horizontal signal line HL connected to the output signal, the signal output to the horizontal signal line HL is subjected to amplification processing, etc., and output to the subsequent circuit, the vertical scanning circuit 3, the horizontal scanning circuit 8, and the output circuit 4 A timing generator for supplying control pulses to the pixel and a plurality of color filters (not shown) provided for each pixel. The functions of the vertical scanning circuit 3, the horizontal scanning circuit 8, the output circuit 4, and the timing generator 2 are the same as those in the prior art, and thus description thereof is omitted here.

  FIG. 2 is a diagram showing a configuration example of the “X” portion shown in FIG.

  As shown in FIG. 2, the column signal output circuit S <b> 1 includes a column amplifier 5 that amplifies the pixel signal, a noise cancellation unit 6 that performs noise removal processing on the signal amplified by the column amplifier 5, and a horizontal scanning circuit 8. And a horizontal readout unit 7 for sequentially outputting signals processed by the noise canceling unit 6 to the horizontal signal line HL. In FIG. 2, only representative circuit elements included in the column amplifier 5, the noise canceling unit 6, and the signal reading unit 7 are shown for convenience of explanation, but various configurations can be applied to these circuits. .

  The first signal line VLA1 provided in the first column is electrically connected to each of the pixels PX aligned in the first column, and is connected to the capacitor CA1 included in the column signal output circuit S1 in the first column. Yes. The second signal line VLB1 provided in the first column is connected to the capacitor CA1 and the noise cancellation unit 6 included in the column signal output circuit S1 in the same column.

  The configuration of the column signal output circuits S2 to Sm, the first signal lines VLA2 to VLAm, and the second signal lines VLB2_2 to VLBm provided in the other columns is the same as that provided in the first column, so that Description is omitted.

  The color filter array of the solid-state imaging device 10 according to the present embodiment is a Bayer array in which filters of three colors of red, blue, and green are arranged in a checkered pattern. In the following, for ease of explanation, pixels having red, blue, and green filters are referred to as “R pixel”, “B pixel”, and “G pixel”, respectively, and are particularly sandwiched between R pixels in the row direction. A pixel that is sandwiched between B pixels in the row direction is referred to as a Gb pixel.

(Comparative example)
Here, in order to facilitate understanding of the present invention, a wiring layout of a solid-state imaging device that is generally considered will be described prior to detailed description of each embodiment.

  FIG. 3 is a schematic diagram showing a wiring structure of a solid-state imaging device according to a comparative example. Capacitors CA1 and CA2 shown in FIG. 2, and first signal lines VLA1 and VLA2 and second signal lines VLB1 connected thereto. And VLB2 are shown. In FIG. 3, the boundary between the column signal output circuits S1 and S2 is indicated by a two-dot chain line for explanation.

  The capacitor CA1 included in the first column signal output circuit S1 has a pair of capacitance electrodes CTA1 and CLA1. One capacitive electrode CTA1 is formed so as to leave a portion along the boundary with the adjacent column signal processing circuit S2 on the surface of the capacitive electrode CLA1, and partially cover the surface of the other capacitive electrode CLA1. Yes.

  The first signal line VLA1 in the first column extends in the column direction from the pixel array 1 to the column signal output circuit S1, and is connected to the capacitor electrode CTA1 via the contact CWA1. On the other hand, the second signal line VLB1 in the first column is connected to the capacitor electrode CLA1 through the contact CWB1 and extends in the column direction along the boundary between the column signal output circuits S1 and S2.

  The capacitor CA2 provided in the second column, the first signal line VLA2, and the second signal line VLB2 have the same configuration as that provided in the first column. That is, the first signal line VLA2 in the second column extends in the column direction along the column signal output circuit S2, is connected to one capacitance electrode CTA2 of the capacitor CA2, and the second signal line VLB2 is connected to the other of the capacitor CA2. It is connected to the capacitor electrode CLA2 and extends in the column direction along the boundary between the column signal output circuit S2 and the third column signal output circuit (not shown).

  When the first signal lines VLA1 and VLA2 and the second signal lines VLB1 and VLB2 are configured as described above, a pair of signal lines arranged with the boundary between the column signal output circuits S1 and S2 in between are partially adjacent to each other. Arranged. That is, a part of the second signal line VLB1 in the first column (part connected to the capacitor CA1 through the contact CWA2) and a part of the first signal line VLA2 in the second column (the capacitor CA2 through the contact CWA2). Are connected in parallel in the column direction across the boundary between the column signal output circuits S1 and S2.

  Accordingly, in the parallel running portion, capacitive coupling is likely to occur between the column signals via the parasitic capacitance CcAr between the second signal line VLB1 in the first column and the first signal line VLA2 in the second column.

  As described above, when the unit cell width XP of each pixel is miniaturized, it is necessary to reduce the unit cell width XH of the column signal output circuits S1 to Sm in accordance with the reduction rate of the unit cell width XP. When the element constants of the circuit elements included in the column signal output circuits S1 to Sm are not changed, the layout of the column signal output circuits S1 to Sm extends in the column direction, so that the parallel running distance between adjacent signal lines is long. Thus, capacitive coupling between adjacent column signal lines is remarkably generated.

  As shown in FIG. 2, when the noise canceling unit 6 includes capacitors CB1 and CB2, the same problem may occur for the signal lines connected to the capacitors CB1 and CB2. That is, the signal lines (VLC1, VLC2, VLD1, VLD2) connected to the capacitors (CB1, CB2) in the noise cancellation unit 6 are the same as the first signal line VLA1 and the second signal line VLB1 shown in FIG. If configured, capacitive coupling is likely to occur between the signal line VLD1 connected to the capacitor CB1 in the first column and the signal line VLC2 connected to the capacitor CB2 in the second column via the parasitic capacitance CcB.

  FIG. 4 is a diagram illustrating a shift in spectral sensitivity characteristics caused by capacitive coupling between adjacent wirings in the wiring configuration according to the comparative example.

  When a commonly used Bayer array is employed as the color filter of the solid-state imaging device, the spectral sensitivity characteristic of the Gr pixel adjacent to the R pixel in the row direction and the spectral sensitivity of the Gb pixel adjacent to the B pixel in the same direction Ideally, the characteristics should match.

  However, when the capacitive coupling between the column signals as described above occurs, the output signal of the Gr pixel receives interference from the output signal of the R pixel of the adjacent column, and the output signal of the Gb pixel is Interference from the output signal of the B pixel is received. As a result, as shown in FIG. 4, the output signal of the Gr pixel and the output signal of the Gb pixel have different spectral sensitivity characteristics. If the spectral sensitivity is different between the Gr pixel and the Gb pixel, it is difficult to adjust the white balance on the camera system, and the color reproducibility deteriorates.

  Hereinafter, features of the solid-state imaging device according to each embodiment of the present invention will be described in detail, taking into consideration the wiring structure according to the comparative example and problems caused by the wiring structure.

(First embodiment)
FIG. 5 is a schematic diagram showing a wiring structure of the solid-state imaging device according to the first embodiment of the present invention. Capacitors CA1 and CA2 shown in FIG. 2 and first signal lines VLA1 and VLA2 connected thereto are shown. The second signal lines VLB1 and VLB2 are also shown. In FIG. 5, the boundary between the column signal output circuits S1 and S2 is indicated by a two-dot chain line for explanation.

  The capacitor CA1 included in the first column signal output circuit S1 has a pair of capacitance electrodes CTA1 and CLA1. One capacitive electrode CTA1 is formed so as to leave a portion along the boundary with the adjacent column signal processing circuit S2 on the surface of the capacitive electrode CLA1, and partially cover the surface of the other capacitive electrode CLA1. Yes. Similarly, the capacitor CA2 in the second column has a pair of capacitive electrodes CTA2 and CLA2.

  The first signal line VLA1 in the first column extends in the column direction from the pixel array to the column signal output circuit S1, and is connected to the capacitor electrode CTA1 via the contact CWA1.

  On the other hand, the second signal line VLB1 in the first column includes a first wiring part WP1, a second wiring part WP2, and a connection part CP connecting them. The first wiring portion WP1 is connected to the capacitance electrode CLA1 of the capacitor CA1 in the first column via the contact CWB1, and is formed to extend in the column direction along the first signal line VLA2 in the second column. . The second wiring portion WP2 is formed so that a part thereof extends in the column direction along the first signal line VLA2 of the second column. In the present embodiment, the first wiring part WP1, the connection part CP, and the second wiring part WP2 are formed in the same wiring layer as the first signal line VLA1.

  Note that the structure of the first signal line VLA2 and the second signal line VLB2 in the second column is the same as that of the first signal line VLA1 and the second signal line VLB1 in the first column, and thus the repeated description is omitted.

  The distance between the pair of signal lines adjacent to each other across the boundary between the column signal output circuits S1 and S2, that is, the second signal line VLB1 in the first column and the first signal line VLA2 in the second column is the first wiring section. The distance D2 between the second wiring portion WP2 and the first signal line VLA2 is set to be larger than the distance D1 between the WP1 and the first signal line VLA2. In other words, the second signal line VLB2 passes through a position closer to the first signal line VLA1 in the same column except for a portion (first wiring portion WP1) connected to the capacitor electrode CLA1 through the contact CWB1. Wired.

  According to such a wiring structure, the value of the parasitic capacitance CcA1 between the adjacent first signal line VLA2 and second signal line VLB1 can be made smaller than the parasitic capacitance CcAr according to the comparative example of FIG. Therefore, according to the present embodiment, it is possible to realize a solid-state imaging device in which interference between column signals due to capacitive coupling is suppressed even when the sizes of the pixel and the column signal output circuit are miniaturized.

  In addition, when interference between pixel signals between adjacent columns is suppressed, the spectral sensitivity characteristics of the Gr pixels and the Gb pixels in the Bayer array can be matched. Therefore, according to the present embodiment, even when the size of the pixel and the column signal output circuit is miniaturized, the solid-state imaging excellent in color reproducibility without changing the element constants of the elements included in the column signal output circuit An apparatus can be realized.

  In general, the wiring is laid out in a straight line in consideration of ease of design and the like unless otherwise required. In a solid-state imaging device having a conventional pixel pitch (for example, up to 2.2 μm cell), even if the column wiring is formed in a straight line as in the comparative example (FIG. 3), capacitive coupling between adjacent column wirings is It did not adversely affect the spectral characteristics of the Gr and Gb pixels (so-called spectral cracking). Therefore, in a conventional solid-state imaging device configured with a pixel pitch, there is no need to consider the adverse effect on image quality due to capacitive coupling between adjacent column wirings.

  However, as a result of actually reducing the pixel pitch compared to the conventional case (for example, 1.75 μm cell), as shown in FIG. 4, the spectral characteristic deterioration (spectral cracking) of the Gr pixel and the Gb pixel is remarkable. The problem that occurred.

  As a result of analyzing the cause of the spectral crack that occurred when the pixel pitch was made fine, the cause as already described in the problem and the comparative example was found. Therefore, when the first and second signal lines were configured as in the present invention, it was confirmed in simulations and actual devices that the layout according to the present invention is effective in improving spectral cracking.

  In addition, the layout of the first and second signal lines according to the present invention does not require a wiring layout change on the pixel array. Therefore, even if the first and second signal lines are laid out as in the present invention, the opening area on the light receiving portion is not reduced at all by the wiring layout, so that the amount of light reaching the light receiving portion is not reduced. That is, according to the present invention, it is possible to realize a solid-state imaging device that is excellent not only in color reproducibility but also in terms of (absolute) sensitivity characteristics.

(Second Embodiment)
FIG. 6 is a schematic diagram showing a wiring structure of a solid-state imaging device according to the second embodiment of the present invention. Capacitors CA1 and CA2 shown in FIG. 2 and first signal lines VLA1 and VLA2 connected thereto are shown. The second signal lines VLB1 and VLB2 are also shown.

  Since the wiring structure of the solid-state imaging device according to the present embodiment is the same as that according to the first embodiment, the following description focuses on the differences between the present embodiment and the first embodiment.

  The solid-state imaging device according to the present embodiment includes diffusion capacitors CA1 and CA2 as capacitors included in the column signal output circuit. The first signal line VLA1 in the first column is connected to the diffusion capacitor electrode CTA1 through the contact CWA1, and the first wiring portion WP1 in the first column is connected to the diffusion capacitor electrode CLA2 in the same column through the contact CWB1. ing.

  According to the present embodiment, even when the column signal output circuits S1 and S2 of the solid-state imaging device include the diffusion capacitors CA1 and CA2, as in the first embodiment, the adjacent first signal line VLA2 and the second signal are adjacent to each other. The value of the parasitic capacitance CcA2 between the lines VLB1 can be made smaller than the parasitic capacitance CcAr according to the comparative example of FIG. Therefore, interference between the column signals due to capacitive coupling is suppressed, and a solid-state imaging device excellent in color reproducibility can be realized.

(Third embodiment)
FIG. 7 is a schematic diagram showing a wiring structure of a solid-state imaging device according to the third embodiment of the present invention. Capacitors CA1 and CA2 shown in FIG. 2 and first signal lines VLA1 and VLA2 connected thereto are shown. The second signal lines VLB1 and VLB2 are also shown.

  Since the basic wiring structure of the solid-state imaging device according to the present embodiment is the same as that according to the first embodiment, the following description will focus on the differences between the present embodiment and the first embodiment. .

  In the solid-state imaging device according to the present embodiment, the first wiring portion WP1, the second wiring portion WP2, and the connection portion CP are formed in a wiring layer that is one layer above the first signal line VLA1. It is different from the embodiment. The first wiring portion WP1 is connected to the capacitor electrode CLA1 via the first layer contact CWB1_1, the wiring portion WP3 formed in the same wiring layer as the first signal line VLA1_1, and the second layer contact CWB1_2. ing.

  As shown in FIG. 7, the distance between the second signal line VLB1 in the first column and the first signal line VLA2 in the second column that run in parallel across the boundary between the column signal output circuits S1 and S2 (the main surface of the substrate). The interval in the direction parallel to the direction is set so as to satisfy the relationship of D2> D1, as in the first embodiment. Therefore, also in the present embodiment, as in the first embodiment, the value of the parasitic capacitance CcA3 between the adjacent first signal line VLA2 and second signal line VLB1 is calculated from the parasitic capacitance CcAr according to the comparative example of FIG. It can be made smaller.

  Further, in the present embodiment, the first signal lines VLA1 to VLAm and the second signal lines VLB1 to VLB2 are formed over two wiring layers, so that the first signals adjacent to each other are compared with the first embodiment. Capacitive coupling between the line and the second signal line can be further suppressed.

  Therefore, according to this embodiment, even when the size of the pixel and column signal output circuit is miniaturized, interference between the column signals due to capacitive coupling is suppressed, and the solid-state imaging device excellent in color reproducibility Can be realized.

(Fourth embodiment)
FIG. 8 is a schematic diagram showing a wiring structure of a solid-state imaging device according to the third embodiment of the present invention. Capacitors CA1 and CA2 shown in FIG. 2 and first signal lines VLA1 and VLA2 connected thereto are shown. The second signal lines VLB1 and VLB2 are also shown.

  Since the basic wiring structure of the solid-state imaging device according to the present embodiment is the same as that according to the third embodiment, the following description will focus on the differences between the present embodiment and the third embodiment. .

  In the solid-state imaging device according to the present embodiment, the first wiring part WP1, the second wiring part WP2, and the connection part CP are formed in a wiring layer two above the first signal line VLA1. It is different from the embodiment. The first wiring portion WP1 includes two layers formed in a wiring layer one layer above the first signal line VLA1 and the first layer wiring portion WP3_1, the second layer contact CWB1_2, and the first signal line VLA1. It is connected to the capacitor electrode CLA1 through the wiring part WP3_2 of the eye and the contact CWB1_3 of the third layer. In the present embodiment, the distance between the first signal line VLA2 and the second signal line VLB1 that run in parallel across the boundary between the column signal output circuits S1 and S2 (the distance in the direction parallel to the main surface direction of the substrate). Is set so as to satisfy the relationship of D2> D1, as in the first embodiment.

  By forming the first wiring part WP1, the second wiring part WP2, and the connection part CP in a wiring layer above the wiring layer in which the first signal lines VLA1 and VLA2 are formed, the boundary of the column signal output circuit is sandwiched between them. The interval between the adjacent first signal line VLA2 and second signal line VLB1 can be increased. Therefore, also in the present embodiment, as in the first embodiment, the value of the parasitic capacitance CcA4 between the adjacent first signal line VLA2 and the second signal line VLB1 is obtained from the parasitic capacitance CcAr according to the comparative example of FIG. It can be made smaller.

  Furthermore, in the present embodiment, the second signal lines VLB1 to VLBm are formed in the wiring layer two above the wiring layer in which the first signal lines VLA1 to VLAm are formed. In comparison, capacitive coupling between the adjacent first signal line and second signal line can be further suppressed.

  Therefore, according to this embodiment, even when the size of the pixel and column signal output circuit is miniaturized, interference between the column signals due to capacitive coupling is suppressed, and the solid-state imaging device excellent in color reproducibility Can be realized.

  In each of the above embodiments, an example in which the circuit element to which the first and second signal lines are connected is a capacitor has been described. However, the first and second signal lines are connected via an element other than the capacitor. Even in this case, the present invention can be similarly applied.

  In each of the above embodiments, the connection portion of the second signal line is formed to extend in a direction perpendicular to the extending direction of the first and second wiring portions. As long as it connects, the direction in which a connection part is extended is not specifically limited.

  Furthermore, the structure and layout of the first and second signal lines according to the above embodiments can be similarly applied to the signal lines VLC1 and VLD1 shown in FIG. In addition to the first and second signal lines, if the configuration of the present invention is applied to each of a pair of signal lines that run in parallel across a boundary portion between adjacent column signal output circuits, the parasitic capacitance between the signal lines ( For example, since CcB) in FIG. 2 can be reduced, interference between column signals can be further suppressed. In particular, in a solid-state imaging device including a color filter, the deviation from the ideal value of the spectral sensitivity characteristics of each color can be further reduced, and color reproducibility can be further improved.

  Furthermore, in each of the above-described embodiments, an example in which the color filter array is a Bayer array has been described. However, the present invention can be similarly applied to a solid-state imaging device having a color filter other than the Bayer array, such as a complementary color filter. Even in this case, the capacitive coupling between the signal lines in adjacent columns can be reduced as in the above embodiments, so that a solid-state imaging device in which interference between pixel signals is suppressed can be realized.

  Furthermore, in each of the above-described embodiments, the example in which the present invention is applied to a solid-state imaging device including a color filter has been described. Even in this case, interference between image signals can be suppressed by reducing capacitive coupling between adjacent signal lines, so that a solid-state imaging device having excellent image characteristics can be applied.

  Further, in the second and third embodiments described above, two or three of the second signal lines (first and second wiring portions, connection portions) are two or three from the wiring layer in which the first signal lines are formed. Although an example of forming in the upper wiring layer has been described, a part of the second signal line may be formed in four or more wiring layers above the wiring layer in which the first signal line is formed.

  The present invention can be used as a solid-state imaging device used for a digital still camera, a digital video camera, or the like.

The figure which shows an example of schematic structure of the solid-state imaging device which concerns on each embodiment of this invention The figure which shows the structural example of X part shown by FIG. Schematic diagram showing the wiring structure of a solid-state imaging device according to a comparative example The figure which shows the shift | offset | difference of the spectral sensitivity characteristic resulting from the capacitive coupling between adjacent wiring in the structure of the wiring which concerns on a comparative example 1 is a schematic diagram showing a wiring structure of a solid-state imaging device according to a first embodiment of the present invention. Schematic diagram showing a wiring structure of a solid-state imaging device according to a second embodiment of the present invention Schematic diagram showing a wiring structure of a solid-state imaging device according to a third embodiment of the present invention Schematic diagram showing the wiring structure of a solid-state imaging device according to the fourth embodiment of the present invention The figure which shows schematic structure of the conventional solid-state imaging device The figure which shows the structural example of the "Y" part shown by FIG. The figure which shows the other structural example of the "Y" part shown by FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel array 10 Solid-state imaging device PX Pixel S1-Sm Column signal output circuit VLA1-VLAm 1st signal line VLB1-VLBm 2nd signal line CA1, CA2 Capacitor CTA1, CTA2, CLA1, CLA2 Electrode (capacitance electrode, diffusion capacity electrode)
CWA1, CWA2, CWB1, CWB2 Contact WP1 First wiring portion WP2 Second wiring portion CP Connection portion

Claims (10)

A solid-state imaging device,
A plurality of pixels arranged in a matrix;
A plurality of column signal output circuits provided for each pixel column;
A plurality of first signal lines connected to circuit elements included in the column signal output circuit;
A plurality of second signal lines including a first wiring portion connected to the circuit element in the same column and a second wiring portion extending along the first signal line in an adjacent column;
An interval between the first signal line and the second wiring portion adjacent to each other across the boundary of the column signal output circuit is larger than an interval between the first signal line and the first wiring portion adjacent to each other across the boundary. A solid-state imaging device. The first and second wiring portions extend in parallel with the first signal line,
The solid-state imaging device according to claim 1, wherein the second signal line further includes a connection unit that connects the first and second wiring units. Each of the circuit elements includes a pair of electrodes,
The first signal line is connected to one of the electrodes via a contact;
The first wiring portion included in the second signal line is connected to the other of the electrodes through a contact at a position away from a connection point between the first signal line and one of the electrodes. The solid-state imaging device according to claim 2, wherein:   4. The solid-state imaging device according to claim 2, wherein the first and second wiring parts and the connection part are formed in the same wiring layer as the first signal line. 5.   4. The solid-state imaging device according to claim 2, wherein the first and second wiring parts and the connection part are formed in a wiring layer different from the first signal line. 5.   6. The solid according to claim 5, wherein the first and second wiring parts and the connection part are formed in a wiring layer that is one layer above the wiring layer in which the first signal line is formed. Imaging device.   6. The solid according to claim 5, wherein the first and second wiring parts and the connection part are formed in a wiring layer two above the wiring layer in which the first signal line is formed. Imaging device.   The solid-state imaging device according to claim 1, wherein the circuit element is a capacitor.   The solid-state imaging device according to claim 1, further comprising a plurality of color filters provided for each pixel.   The solid-state imaging device according to claim 9, wherein the color filter array is a Bayer array in which three colors of red, blue, and green are arranged in a checkered pattern.

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