JP2008258635A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which comprises an MOS type element in which a variation in element characteristic is controlled. <P>SOLUTION: The semiconductor devices is provided with an element isolation insulating film which is embedded in a semiconductor region of a substrate; a semiconductor layer of the semiconductor region in which elements are separated by the element isolation insulating film, and an upper portion of the semiconductor layer projects above the surface of the element isolation insulating film; an MOS type element in which a source-drain region, a gate insulating film and a gate electrode are formed in the semiconductor layer, and the gate electrode is formed on the element isolation insulating film in the section of a surface parallel to the direction of the width of a channel. The position of the upper surface of the semiconductor layer under the gate electrodes 20 nm or more higher than the position of the upper surface of the element isolation insulating film under the gate electrode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device characterized by an element isolation structure.

  In recent years, large-scale integrated circuits (LSIs) formed by integrating a large number of transistors, resistors, and the like so as to achieve an electric circuit and integrating them on a single chip are often used in important parts of computers and communication devices. ing. For this reason, the performance of the entire device is greatly linked to the performance of the LSI alone. The improvement of the performance of a single LSI can be realized by increasing the degree of integration, that is, by miniaturizing elements.

  For example, in the case of a MOS transistor, element miniaturization can be realized by shortening the gate length and thinning the source / drain diffusion layer.

  As a method for forming a shallow source / drain diffusion layer, a low acceleration ion implantation method is widely used. By this method, a shallow source / drain diffusion layer of 0.1 μm or less can be formed.

  However, since the source / drain diffusion layer formed by the low acceleration ion implantation method has a high sheet resistance of 100Ω / □ or more, high acceleration due to miniaturization cannot be expected as it is.

  Therefore, in devices that require high speed, such as logic LSIs, salicide technology that forms silicide films on the surfaces of source / drain diffusion layers and gate electrodes (polycrystalline silicon films doped with impurities) in a self-aligned manner. Is used.

  Dual-gate MOS transistor (n-channel and p-channel MOS transistors formed on the same substrate, a polycrystalline silicon film doped with n-type impurities as the gate electrode of the n-channel MOS transistor, the gate of the p-channel MOS transistor When a p-type impurity doped polycrystalline silicon film is used as an electrode, the salicide technique can not only simply make the gate electrode resistive, but also reduce the number of processes. .

  This is because the gate electrode (polycrystalline silicon film) can be doped with impurities of a predetermined conductivity type in the ion implantation process for forming the source / drain diffusion layers.

  On the other hand, when a dual gate MOS transistor is formed using a polycide gate electrode (a gate electrode in which a metal silicide film such as a W silicide film is laminated on a polycrystalline silicon film doped with impurities). In the ion implantation process for forming the source / drain diffusion layers, since the polycrystalline silicon film is masked with the metal silicide film, the polycrystalline silicon film cannot be doped with an impurity of a predetermined conductivity type.

  Therefore, before forming the source / drain diffusion layer, it is necessary to dope the polycrystalline silicon film with an impurity of a predetermined conductivity type in advance. That is, the ion implantation process for forming the source / drain diffusion layers and the ion implantation process for doping the polycrystalline silicon film with impurities of a predetermined conductivity type are separate processes, and the number of processes increases.

  Specifically, the photolithography process is increased twice, the ion implantation process is increased twice, and the resist removal process is increased twice as compared with the salicide technique.

  On the other hand, it is indispensable to adopt a SAC (Self-Aligned Contact) structure in a device such as a memory LSI such as a DRAM that requires integrated formation of elements at a high density.

  In the step of forming the SAC structure, an interlayer insulating film on one source / drain diffusion layer (usually used as a source) is etched by the RIE method, and a contact hole for the source / drain diffusion layer is formed. There is a step of forming.

  At this time, it is necessary to prevent the surface of the gate electrode (polycrystalline silicon film) from being exposed even if misalignment occurs in the contact hole. For this purpose, a silicon nitride film is formed in advance as an etching stopper film on the gate electrode.

  When such a silicon nitride film is present, impurities are not implanted into the gate electrode in the ion implantation step when forming the source / drain diffusion layers. Therefore, the salicide technology used in the logic LSI cannot be used for the memory LSI.

  By the way, in memory LSI, conventionally, a gate electrode (polycrystalline silicon gate electrode) made of a polycrystalline silicon film doped with impurities has been widely used, and a polycide gate electrode has also been used because of the necessity of low resistance. Yes.

  In the case where a low resistance gate electrode is required, a polymetal gate electrode formed by sequentially laminating metal films such as a polycrystalline silicon film doped with impurities, a barrier metal film, and a W film is used. Since the polymetal gate electrode has a lower resistance than the polycide gate electrode, a desired sheet resistance can be realized with a thinner film thickness.

  However, the polymetal gate electrode has the following problems. The logic LSI uses the dual gate structure described above. Therefore, as in the case of the polycide gate electrode, when a polymetal gate electrode is used in the logic LSI, a process of ion-implanting impurities into the polycrystalline silicon film of the polymetal gate electrode and a source / drain diffusion layer are formed. In addition, it is necessary to perform the step of ion-implanting impurities into the silicon substrate in separate steps. Therefore, the number of processes increases and the production cost increases.

  By the way, in an LSI in which a logic IC and a DRAM are mixedly mounted, if a silicide film is formed on the surface of the source / drain diffusion layer of the DRAM, the pn junction leakage current of the memory cell increases and the data retention characteristics deteriorate. In addition, since the DRAM requires a SAC structure as described above, a W polycide electrode is used.

On the other hand, in the logic IC, the threshold voltage of the MOS transistor needs to be lowered in order to pass as much current as possible at a low voltage. For this purpose, the polycrystalline silicon film of the gate electrode of the n-channel MOS transistor is doped with an n-type impurity such as P or As to make it n ⁻ -type, and the p-channel MOS transistor is doped with a p-type impurity such as BF _2. It is necessary to dope to make P ⁺ type.

  In order to improve the performance of a transistor, it is not sufficient to reduce the resistance of the source, drain, and gate. It is also very important to reduce variations in transistor characteristics. One of the major causes of characteristic variation is threshold voltage variation.

When the threshold voltage of the MOS transistor is measured with respect to the gate processing dimension (gate length), the threshold voltage is greatly reduced in the short channel region. For example, substrate impurity concentration: 5 × 10 ¹⁷ cm ⁻³ , gate oxide film thickness: 4.0 nm, gate width (w): 10 μm, source / drain diffusion layer impurity concentration: 5 × 10 ¹⁷ cm ⁻³ , source / drain Junction depth (x _j ) of drain diffusion layer: n-channel MOS transistor of 0.15 μm was examined for channel length dependence of threshold voltage. When the channel length was 0.2 μm or less, the threshold voltage Was found to drop sharply.

  Since the conductance of the channel is higher as the gate length is shorter, it is desirable to employ a MOS transistor having a shorter gate length in the LSI circuit. However, since the threshold voltage changes by 50 mV or more just by changing the gate length by 10 to 15 nm, if such a short gate length MOS transistor is employed, variations in processing dimensions, variations in gate oxide film thickness, Variations in threshold voltage are likely to occur due to the influence of variations in the impurity concentration distribution of the source / drain diffusion layers. This is a major cause of LSI yield reduction.

  The shape of the element isolation insulating film at the end portion of the element region has the greatest influence on the variation of the threshold voltage next to the variation in the processing dimension. In a highly integrated circuit in which isolation between elements is about 0.3 μm or less, a trench (element isolation groove) is dug to a depth of 0.2 to 0.3 μm in a silicon substrate, and an oxide film is embedded so as to fill the trench. Generally, STI (Shallow Trench Isolation) is used, which is deposited on the entire surface of the substrate using CVD, and removes excess oxide film outside the trench by chemical mechanical polishing (CMP). It has been.

Conventionally, a TEOS / ozone-based CVD-SiO ₂ film has been embedded, and as shown in FIG. 24A, the aspect ratio of the trench (element isolation groove) formed in the silicon substrate 91 is 1-1. In the case of about 5, it is possible to fill the trench with the oxide film 92 without incurring voids.

  However, if the aspect ratio of the trench becomes higher than 1.5 with the miniaturization of the element, it becomes difficult to fill the trench with an oxide film without a gap, and as shown in FIG. A void 93 is generated at the center, resulting in an incomplete embedding shape.

  When the void 93 is generated, moisture is easily absorbed in the gap, so that the hygroscopicity is increased and the device characteristics are deteriorated. Furthermore, since there are variations in how the voids 93 are formed and the degree of moisture absorption, the voids 93 cause variations in element characteristics.

  In order to solve this, embedding using HDP plasma TEOS has been proposed. However, when the aspect ratio exceeds 2 to 2.5, the oxide film is not completely embedded, and in this case, a void 93 as shown in FIG.

  When the oxide film 92 is formed while the substrate bias is applied and the deposited oxide film is etched, the embedded shape of the oxide film 92 is improved. However, as shown in FIG. As a result, device characteristics deteriorate. Further, since the degree of the crystal defect 94 varies, the crystal defect 94 causes variations in device characteristics.

  In the case of the STI described with reference to FIGS. 24 and 25, the etching rate of the oxide film (deposited insulating film) 92 is high, so that the wet process is performed with a plurality of diluted hydrofluoric acids or diluted ammonium fluoride in the LSI manufacturing process. The etching process generates a divot 95 as shown in FIG. 26 at the upper edge of the trench.

  In this case, the gate electrode bites into the divot 95, and a transistor (corner transistor) having an apparently low threshold voltage is formed here. Since the depth and shape of the divot 95 are pattern-dependent, the threshold voltage of the corner transistor varies greatly depending on the gate width, which causes a variation in the threshold voltage of the original MOS transistor. Further, when the corner transistor exists, hump occurs as shown in FIG. 27, and the element characteristics deteriorate. Further, since the depth and shape of the divot 95 are not uniform within the wafer surface, the variation in device characteristics is further increased.

  In order to solve such a problem, as shown in FIG. 28, a method of sandwiching the thermal oxide film 96 at the interface between the element region and the element isolation region is performed, but even when the thermal oxide film 96 is interposed, Although the degree becomes lighter, the etching rate of the oxide film 92 is high, so that the oxide films 92 and 96 are retreated in the upper part of the trench as shown in FIG.

  Also, as shown in FIG. 29, an oxide film 92 is first formed on a silicon substrate 91, then the oxide film 92 in a region corresponding to the element region is removed by etching, and then the substrate surface ( A method has been proposed in which a silicon layer 97 is selectively grown in an element region by epitaxial growth using Si) as a growth nucleus. However, in this method, a facet 98 (oblique crystal plane) is formed, the gate electrode bites into the facet 98, and the same problem as in the structure with the divot 95 shown in FIG. 26 occurs.

  An object of the present invention is to provide a semiconductor device having a MOS type element in which variation in element characteristics is suppressed.

  The semiconductor device according to the present invention includes an element isolation insulating film embedded in a semiconductor region of a substrate and an element isolation by the element isolation insulating film, the upper portion protruding above the surface of the element isolation insulating film, and the semiconductor region A semiconductor layer, a source / drain region, a gate insulating film, and a gate electrode are formed in the semiconductor layer, and the gate electrode is formed on the element isolation insulating film in a cross section of a plane parallel to the channel width direction. The upper surface position of the semiconductor layer under the gate electrode is 20 nm or more higher than the upper surface position of the element isolation insulating film under the gate electrode.

  According to the present invention, the variation in element characteristics can be effectively achieved by setting the difference between the upper surface position of the element isolation insulating film and the upper surface position of the semiconductor layer in which the MOS type element is formed (semiconductor layer in the element region) to a predetermined value. Can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 and 2 are process cross-sectional views illustrating a method for forming an element isolation structure according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, a thermal oxide film 2 as an element isolation insulating film is formed on a single crystal silicon substrate 1. The thermal oxidation for forming the thermal oxide film 2 is performed in an atmosphere of 900 ° C. or higher, usually a water vapor / oxygen atmosphere, whereby the thermal oxide film 2 has a high density and a low etching rate with respect to hydrofluoric acid or ammonium fluoride. Is obtained. The oxide film 2 having a slower etching rate can be obtained by performing thermal oxidation in a high-pressure oxidizing atmosphere of 10 atm or higher.

  Next, as shown in FIG. 1B, the portion of the thermal oxide film 2 corresponding to the element formation region is selectively removed using photolithography and anisotropic etching, and an opening is formed in the thermal oxide film 2. Open.

  Here, for example, KrF or ArF excimer laser is used for the exposure of the photoresist, and for example, reactive ion etching (RIE) is used for the anisotropic etching.

  Next, the contamination layer made of carbon or fluorine on the substrate surface at the bottom of the opening is oxidized, and the natural oxide film on the substrate surface at the bottom of the opening is removed with diluted hydrofluoric acid or ammonium fluoride. Thereafter, the natural oxide film on the substrate surface at the bottom of the opening is further removed by heat treatment in a gas atmosphere containing hydrogen.

  Next, as shown in FIG. 1C, the epitaxial layer 3 is selectively grown on the silicon substrate 1 using the exposed substrate surface as a growth nucleus (seed). The epitaxial layer 3 is thicker than the thermal oxide film 2 and is selectively grown so as to protrude from the thermal oxide film 2.

  The epitaxial layer 3 is a silicon layer, a silicon germanium layer (an alloy film in which germanium is solid-solved in a concentration range of 10 to 90% with respect to silicon), or a germanium layer.

Dichlorosilane is usually used as the source gas for silicon. In the case of using a film forming apparatus having a residual water vapor partial pressure and an oxygen partial pressure of 10 ⁻⁹ Torr or less, monosilane, disilane, or trisilane may be used.

As the germanium source gas, germane (GeH ₄ ) or tetrafluoride germane (GeF ₄ ) is used. The formation of the silicon germanium film can be any combination of source gases, and a combination of monosilane and germane is usually used.

  HCl may be added to ensure selective growth. The epitaxial growth temperature is in the range from 700 ° C. to 1100 ° C., and the film may be formed under desired conditions depending on the type of gas used, the film thickness to be deposited, and the film quality.

  Next, as shown in FIG. 2D, the excess epitaxial layer 3 outside the opening of the thermal oxide film 2 is removed by CMP or mechanical polishing (MP) to planarize the surface.

  Next, as shown in FIG. 2E, the surface of the epitaxial layer 3 remaining in the element formation region is etched by about 10-50 nm, and the crystal formed on the surface of the epitaxial layer 3 in the step of FIG. Remove damaged layer. As a result, the surface of the epitaxial layer 3 is located below the surface of the thermal oxide film 2.

  In the case where the epitaxial layer 3 is a silicon layer and a silicon germanium layer, the etching is wet etching using a solution obtained by diluting, for example, nitric acid with 10% or less hydrofluoric acid with acetic acid or pure water.

  In the case of a germanium layer, wet etching using a solution obtained by diluting nitric acid with 10% or less hydrofluoric acid with acetic acid or pure water, or sulfuric acid (diluting with heating or water if necessary) Thus, the etching rate is controlled.).

Finally, the surface of the epitaxial layer 3 is flattened at the atomic layer level by heat treatment in an atmosphere containing hydrogen, and the strain at the interface between the thermal oxide film 2 and the epitaxial layer 3 is relaxed, and the interface state density is increased. Reduce to about 5 × 10 ¹⁰ cm ⁻² or less. Thereafter, a process of forming a desired semiconductor element, for example, a MOS transistor, in the epitaxial layer 3 is continued as in the prior art.

  As described above, according to the present embodiment, since the opening is filled with the epitaxial layer 3, it is possible to prevent the generation of voids that cause variations, and the epitaxial layer 3 can be further removed from the thermal oxide film 2 outside the opening. Since it is formed so as to protrude above, the occurrence of facets that cause variations can be prevented. Therefore, according to the present embodiment, it is possible to realize an element isolation structure that can effectively suppress variations in element characteristics even when the elements are miniaturized.

  In the present embodiment, the surface of the epitaxial layer 3 is positioned below the surface of the thermal oxide film 2, but conversely, the surface of the thermal oxide film 2 may be lower, or both may have the same height. It may be. In short, if the epitaxial layer 3 is thicker than the thermal oxide film 2 and is selectively grown so as to protrude onto the thermal oxide film 2, the excess epitaxial layer 3 can be removed to cause voids and facets that cause characteristic variations. Therefore, the final element isolation structure may be appropriately selected.

(Second Embodiment)
FIG. 3 is a process cross-sectional view illustrating a method for forming an element isolation structure according to a second embodiment of the present invention. Parts corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals as those in FIGS. 1 and 2, and detailed description thereof is omitted.

  First, the steps shown in FIGS. 1A to 1C are performed.

  Next, as shown in FIG. 3A, a silicon film 4 is formed on the entire surface in order to flatten the surface. Instead of the silicon film 4, a silicon germanium film or a germanium film may be formed.

  Next, as shown in FIG. 3B, the silicon film 4 and the epitaxial layer 3 outside the opening of the thermal oxide film 2 are removed by CMP or MP to flatten the surface. Here, the thickness of the epitaxial layer 3 has a pattern dependency that changes depending on the difference in the size and density of the opening of the thermal oxide film 2, but the surface is flattened by the silicon film 4. The pattern dependency is improved, and the flatness of the surface after CMP or the like becomes sufficiently high. The subsequent steps are the same as those after the step of FIG. 2E of the first embodiment.

(Third embodiment)
4 and 5 are process cross-sectional views illustrating a method for forming an element isolation structure according to the third embodiment of the present invention. This embodiment is an example in which the first embodiment is applied to an SOI substrate.

First, as shown in FIG. 4A, after a single crystal insulating film 12 made of an insulator such as CeO ₂ , YSZ (Yttrium Stabilized Zirconia), CaF ₂ or diamond is formed on a single crystal silicon substrate 11. Then, an oxide film 13 as an element isolation insulating film is formed on the single crystal insulating film 12.

  The oxide film 13 is formed by thermal oxidation in an oxidizing atmosphere at 900 ° C. or higher, or is formed by overheating at 900 ° C. or higher after being deposited. By such a method, the oxide film 13 having a slow etching rate with respect to hydrofluoric acid or ammonium fluoride can be obtained. Further, in order to obtain the oxide film 13 having a slower etching rate, thermal oxidation is preferably performed in a high-pressure oxidizing atmosphere of 10 atm or higher.

  Next, as shown in FIG. 4B, the oxide film 13 in the region corresponding to the element formation region is selectively removed by using photolithography and anisotropic etching, and an opening is opened in the oxide film 13. . For example, KrF or ArF excimer laser is used for exposing the photoresist, and RIE is used for anisotropic etching.

  Next, the contamination layer made of carbon or fluorine on the surface of the single crystal insulating film 12 is oxidized, and the natural oxide film on the surface of the single crystal insulating film 12 on the bottom of the opening is removed with diluted hydrofluoric acid or ammonium fluoride. Subsequently, the natural oxide film on the surface of the single crystal insulating film 12 on the bottom of the opening is further removed by heat treatment in a gas atmosphere containing hydrogen.

  Next, as shown in FIG. 4C, the epitaxial layer 14 is selectively grown using the exposed surface of the single crystal insulating film 12 as a growth nucleus (seed). The epitaxial layer 14 is thicker than the oxide film 13 and is selectively grown so as to protrude from the oxide film 13.

  The epitaxial layer 14 is a silicon layer, a silicon germanium layer (an alloy film in which germanium is dissolved in a concentration range of 10 to 90% with respect to silicon), or a germanium layer.

Dichlorosilane is usually used as the source gas for silicon. In the case of using a film forming apparatus having a residual water vapor partial pressure and an oxygen partial pressure of 10 ⁻⁹ Torr or less, monosilane, disilane, or trisilane may be used.

As the germanium source gas, germane (GeH ₄ ) or tetrafluoride germane (GeF ₄ ) is used. The formation of the silicon germanium film can be any combination of source gases, and a combination of monosilane and germane is usually used.

  HCl may be added to ensure selective growth. The epitaxial growth temperature is in the range from 700 ° C. to 1100 ° C., and the film may be formed under desired conditions depending on the type of gas used, the film thickness to be deposited, and the film quality.

  Next, as shown in FIG. 5D, the excess epitaxial layer 14 outside the opening of the oxide film 13 is removed by CMP or MP, and the surface is planarized.

  Next, as shown in FIG. 5E, the surface of the epitaxial layer 14 remaining in the element formation region is etched by about 10 to 50 nm, and crystal damage caused on the surface of the epitaxial layer 14 in the step of FIG. Remove the layer. As a result, the surface of the epitaxial layer 14 is positioned below the surface of the oxide film 13.

  In the case where the epitaxial layer 14 is a silicon layer or a silicon germanium layer, the etching is wet etching using a solution obtained by diluting, for example, nitric acid with 10% or less hydrofluoric acid with acetic acid or pure water.

  In the case of germanium, wet etching using a solution obtained by diluting nitric acid with 10% or less hydrofluoric acid with acetic acid or pure water, or sulfuric acid (diluted with heat or water if necessary). Then, the etching rate is controlled.).

Finally, the surface of the epitaxial layer 14 is flattened at the atomic layer level by a heat treatment in an atmosphere containing hydrogen, and strain at the interface between the oxide film 13 and the epitaxial layer 14 is alleviated, so that the interface state density is 5 The element isolation structure is completed by reducing it to about 10 ¹⁰ cm ⁻² or less. This is followed by a step of forming a desired semiconductor element, for example, a MOS transistor in the epitaxial layer 14 as in the conventional case.

  In the step of FIG. 4C, in order to improve the pattern dependency of the thickness of the epitaxial layer 13, a silicon film or the like may be formed on the entire surface as in the second embodiment.

  Similarly to the first embodiment, the present embodiment can prevent the occurrence of voids and facets that cause variations, and therefore element isolation that can effectively suppress variations in element characteristics even if the elements are miniaturized. The structure can be realized. Furthermore, according to the present embodiment, element isolation on the SOI substrate can be performed more easily than before.

(Fourth embodiment)
6 to 9 are process sectional views showing a method of manufacturing a MOS transistor according to the fourth embodiment of the present invention.

First, as shown in FIG. 6A, a thermal oxide film 22 having a thickness of about 200 to 300 nm is formed on a single crystal silicon substrate 21 by thermal oxidation. After thermal oxidation, a region having a depth of at least about 10 to 20 nm from the surface of the thermal oxide film 22 may be changed to a SiNO film or the like using NO, N ₂ O, NH ₃ or nitrogen radicals.

  Next, as shown in FIG. 6A, as in the first embodiment, the thermal oxide film 22 in the region corresponding to the element formation region is selectively removed using photolithography and anisotropic etching. Next, the epitaxial layer 23 is selectively grown so as to be thicker than the thermal oxide film 22 and protrude on the thermal oxide film 22, and then the pattern dependency of the thickness of the epitaxial layer 23 is the same as in the second embodiment. In order to improve the above, a silicon film 24 is formed on the entire surface.

  The epitaxial layer 23 is a silicon layer, a silicon germanium layer, or a germanium layer. Instead of the silicon film 24, a silicon germanium film or a germanium film may be formed.

  Next, as shown in FIG. 6B, the silicon film 24 and the epitaxial layer 23 outside the opening of the thermal oxide film 22 are removed by CMP or MP to flatten the surface.

  Thereafter, in order to improve the crystallinity of the surface of the epitaxial layer 23, heat treatment is performed in a hydrogen atmosphere at a temperature of 800 ° C. or higher, preferably 900 ° C. or higher. By such heat treatment, Si atoms move on the surface and are flattened at the atomic level, and crystallinity is improved.

  When the method described above is used, the element region (epitaxial layer 23) and the element isolation region (thermal oxide film 22) can be easily formed with an isolation width of 0.15 μm or less (the conventional method has a limit of about 0.18 μm).

  Thereafter, the manufacturing process of the MOS transistor is performed. First, as shown in FIG. 6C, a thermal oxide film 25 having a thickness of about 3 to 10 nm is formed on the epitaxial layer 23.

  Next, as shown in FIG. 7D, a dummy gate film 26 having the same pattern as the gate electrode is formed on the thermal oxide film 25. As the dummy gate film 26, a laminated film (SiN / a-Si film) of a silicon nitride film and an amorphous silicon film is used, and the dummy gate film 26 is formed by processing this by anisotropic etching.

  Here, the upper layer film of the dummy gate film 26 is not limited to the silicon nitride film. In the flattening step by polishing the interlayer insulating film 30 in the subsequent step (FIG. 7F), the interlayer insulating film 30 However, a film with a slow polishing rate may be used.

  The film below the dummy gate film 26 is not limited to an amorphous silicon film, and a film having an etching rate higher than that of the thermal oxide film 25 may be used. Specifically, any Si-based film such as a polycrystalline silicon film may be used.

  Next, as shown in FIG. 5D, impurities are introduced into the substrate surface by using an impurity introduction method such as ion implantation, plasma doping, or vapor phase diffusion using the thermal oxide film 25 and the dummy gate film 26 as a mask. Then, an extension region (LDD) 27 of the source / drain region is formed.

  The electrical activation of the impurities is performed by heat treatment at 800 to 1000 ° C. for 30 seconds or less using RTA (Rapid Thermal Annealing) capable of a temperature rising rate of 100 ° C./sec or more.

  Next, as shown in FIG. 7E, a gate side wall insulating film 28 made of a silicon nitride film or a silicon oxynitride film having a thickness of about 5 to 30 nm is formed by so-called left side walls. An oxide film having a thickness of 10 nm or less is interposed between the gate sidewall insulating film 28 and the dummy gate film 26 so that the gate sidewall insulating film 28 does not recede in the lateral direction when the dummy gate film 26 is removed later. It is desirable that

  Next, as shown in FIG. 4E, an impurity is introduced into the substrate surface by using an impurity introduction method such as ion implantation, plasma doping, or vapor phase diffusion to form a deep source / drain region 29. The electrical activation of the impurities is performed by heat treatment at 800 to 900 ° C. for 30 seconds or less using RTA capable of a temperature rising rate of 100 ° C./sec or more.

  In order to increase the concentration of the activated impurity, heat treatment at 1000 ° C. or more and 1 second or less may be performed using an electron beam, a laser having a wavelength in the ultraviolet region, a mercury lamp, or a xeno lamp. The electrical activation of impurities in the step of FIG. 7D may be performed in this step.

Thereafter, as shown in FIG. 4E, an interlayer insulating film 30 thicker than the dummy gate film 26 is deposited on the entire surface by the CVD method. Here, as the interlayer insulating film 30, an SiO ₂ film capable of sufficiently increasing the polishing rate as compared with the silicon nitride film that is an upper film of the dummy gate film 26 is used.

  Next, as shown in FIG. 7F, the interlayer insulating film 30 is polished by CMP until the surface of the dummy gate film 26 is exposed to flatten the surface.

  Next, as shown in FIG. 8G, after removing the dummy gate film 26 by etching combining isotropic etching and anisotropic etching, the thermal oxide film 25 is prevented from forming crystal defects in the epitaxial layer 23. The openings 31 are formed by etching.

  Next, as shown in FIG. 8H, ions 32 of B, Ga, In, P, As, or Sb are implanted into the bottom surface of the opening 51 to form a channel impurity doping layer 33.

  This ion implantation is preferably performed at a low temperature. Specifically, ion implantation is performed while cooling the silicon substrate 21 so that the substrate temperature is −60 ° C. or lower, preferably −100 ° C. or lower.

  When ion implantation is performed at such a low temperature, aggregation of atomic vacancies can be suppressed, so that crystal defects can be completely recovered by heat treatment. The implantation angle is preferably perpendicular to the surface of the silicon substrate 21 or within 5 ° from the perpendicular.

  For the heat treatment for activating the impurities, the heat treatment chamber is once evacuated, or an inert gas such as N or Ar is sufficiently flowed, and oxygen, water vapor, carbon dioxide or other oxidizing agent is mixed in the heat treatment chamber. It is desirable to start the heat treatment in such a state. FIG. 8 (i) shows a cross-sectional view after the heat treatment.

  Thereafter, an oxide film (not shown) having a thickness of 1 nm or less is formed on the surface of the epitaxial layer 3 on the bottom surface of the opening 31 by wet treatment with an aqueous solution containing hydrogen peroxide water and ozone water, or by dry treatment using oxygen radicals or ozone. Form.

Next, as shown in FIG. 4 (j), insulation having a higher relative dielectric constant than SiO ₂ such as Ta ₂ O ₅ , TiO ₂ , BSTO, or CeO ₂ so as to cover the surface (bottom surface and side surface) of the opening 31. A gate insulating film 34 made of a material and having a thickness of about 1 to 20 nm is formed.

  When the film thickness of the gate insulating film 34 exceeds 20 nm, the ratio of the gate insulating film 34 occupying the opening 31 becomes too large, the gate resistance increases, or the channel part carrier is controlled by the gate voltage, that is, It becomes difficult to control the threshold voltage.

When the gate insulating film 34 is formed by the CVD method, in order to prevent non-uniform growth, a surface oxide film such as a natural oxide film or a chemical oxide film is removed before forming the gate insulating film 34, and then oxygen is added. It may be adsorbed for 1-2 atomic layers or a Si—O bond layer may be formed. Thereafter, a gate insulating film 34 made of a high dielectric constant insulator such as Ta ₂ O ₅ , TiO ₂ , BSTO or CeO ₂ is formed by CVD. Further, a SiO _x N _y film having a thickness of about 2 to 3 nm may be deposited, or the surface of the oxide film (not shown) may be nitrided using nitrogen radicals or the like at a temperature of 500 ° C. or lower.

Further, a high dielectric constant insulating film such as Ta ₂ O ₅ or TiO ₂ may be formed on a SiO _x N _y layer of 1 nm or less.

  Next, as shown in FIG. 6J, a conductive thin film having metal conductivity for determining the work function of the gate, for example, a TiN film 35 having a thickness of 10 nm or less is formed on the gate insulating film 34.

  At this time, deposition conditions such as the composition of TiN, deposition temperature, and pressure are set so that the crystal grain size of the TiN film 35 is 30 nm or less. In the present embodiment, a TiN film is formed by a sputtering method by controlling the partial pressure ratio of Ar and N so that the ratio of Ti and N is more than 1: 1 at a temperature of 300 ° C. or less. The TiN film 35 is formed by adding 30% or less of oxygen to the TiN film.

  By changing the concentration of oxygen to be added from 1% to 10%, the crystal grain size of the TiN film 35 can be reduced to 10 nm or less. If the oxygen concentration is further increased, the electrical conductivity is lowered and no metallic conduction is exhibited, so it is necessary to make it lower.

  In addition to oxygen, it is possible to add B (boron) or C (carbon) to the TiN film to make the crystal grain size smaller than that of the additive-free TiN film, and the addition of 10-30% B or C Can be made amorphous.

  B or C is added by using a compound gas containing B or C when sputtering TiN, such as boron hydride or carbon hydride, B fluoride or C fluoride, or Ti containing B or C as a sputtering target. The target can be formed by chemical sputtering in a mixed gas of Ar and N, or a TiN target containing B or C can be sputtered by Ar. By adding impurities such as O, B, and C to TiN and controlling the composition of TiN, the work function can be set to 4.5 eV or less.

Alternatively, a CVD method using TiCl ₄ and NH ₃ may be used to form a film at a temperature of 600 ° C. or less so that the ratio of Ti and N is more than 1: 1. When the temperature is higher than 600 ° C., the unevenness on the surface of the TiN film becomes remarkably large, and a low resistance metal film cannot be uniformly formed thereon.

  Further, microcrystallization may be performed by using a method of adding oxygen of 30% or less, similarly to the TiN film formed by sputtering. The concentration of oxygen to be added is desirably in the range of 1 to 10%, and the crystal grain size can be reduced to 30 nm or less by such an amount of oxygen. If the film thickness is about 10 nm or less, the crystal grain size can be controlled to 10 nm or less.

Further, dimethylaminotitanium (Ti {N (CH ₃ ) ₂ } ₄ and dimethylamino titanium (Ti {N (CH ₃ ) ₂ } ₄ ) are thermally decomposed in an atmosphere containing hydrogen or using TiN film and TiCN film using plasma. May be formed.

  When the specific resistance of the gate electrode may be 50 μΩ · cm or more, the entire gate electrode may be formed of a TiN film. In this case, since it is necessary to form a TiN film having a thickness of 50 nm or more, it is necessary to be a film having an orientation with columnar or needle-like crystals or an amorphous film.

  Examples of electrode materials other than TiN include metal nitrides such as Ta nitride, Nb nitride, Zr nitride, and Hf nitride, or metal carbide, metal boride, metal-Si nitride, metal-Si carbide, metal For example, carbon nitride.

  Desirably, the conductivity is not reduced by 50% or more for the thermal stability between the gate insulating film 34 and the conductive thin film having the metal conductivity that determines the work function of the gate made of these electrode materials. It is effective to add oxygen within the range. These electrode materials are also excellent in thermal stability at the interface with Ta oxide, Ti oxide, Zr oxide, Hf oxide, and Ce oxide.

  Finally, as shown in FIG. 9 (k), the gate electrode 36 is embedded in the opening 36 to complete the MOS transistor. As one method of forming the gate electrode 36, an Al film is formed on the entire surface by sputtering, and the opening 31 is filled with the Al film by reflow, and an excess Al film outside the opening 31, the gate insulating film 34, and There is a method of removing the TiN film 35 by CMP or MP. As another method, a metal film having a low specific resistance such as a W film is deposited on the entire surface so as to fill the opening 31 by a CVD method, and then the excess metal film outside the opening 31, the gate insulating film 34, and There is a method of removing the TiN film 35 by CMP or MP.

When it is necessary to reduce the resistance of the source / drain region, a metal silicide layer such as a CoSi ₂ layer or a TiSi ₂ layer is used as a source between the step of FIG. 7D and the step of FIG. -A step of forming on the surface of the drain region may be added.

  Here, when the depth of the source / drain region 29 is 100 nm or less, an epitaxial layer in which a silicon layer, a silicon germanium layer, or a silicon germanium carbon layer is epitaxially grown on the source / drain region 29 and is eroded by the metal silicide layer. 23 is preferably separated from the interface (pn junction interface) between the source / drain region 29 and the epitaxial layer 23 by 5 nm or more.

  In the present embodiment, a method for manufacturing a damascene gate type MOS transistor has been described. However, in order to manufacture a normal MOS transistor, a normal n type or a normal type transistor is used instead of the dummy gate film 26 in the step of FIG. A gate electrode may be formed of a p-type polysilicon film, a silicide film / metal film laminate film, or a silicide film / n-type or p-type polysilicon film laminate film. A nitride film or the like having a slower etching rate than the oxide film may be stacked on the gate electrode.

FIG. 10 shows the gate length dependence of the threshold voltage _Vth of the MOS transistor formed by the method of the present invention and the conventional method. The MOS transistor formed by the method of the present invention is one in which the element isolation insulating film does not recede at the boundary between the element isolation regions due to facets or the like. Further, the Si surface in the element region is set back 15 nm below the element isolation insulating film surface. The MOS transistor formed by the conventional method has a recession of the element isolation insulating film at the boundary between the element isolation region and the element region due to facet or the like.

From the figure, it can be seen that the variation of the threshold voltage _Vth of the MOS transistor formed by the method of the present invention is small at 30 mV or less, but that of the MOS transistor formed by the conventional method is large at about 50 to 100 mV. The reason why the variation of the threshold voltage V _th becomes large in the conventional method is that the element isolation insulating film retreats in the conventional method, and the amount thereof varies.

(Fifth embodiment)
11 and 12 are process cross-sectional views illustrating a method for forming an element isolation structure according to the fifth embodiment of the present invention.

  First, as shown in FIG. 11A, an oxide film 42 having a thickness of about 200 nm is formed on the surface of a single crystal silicon substrate 41 by thermal oxidation, and then silicon nitride having a thickness of about 50 nm is formed on the oxide film 42. The film 43 is formed by the CVD method. The conductivity type of the silicon substrate 41 is p-type and the plane orientation is (100).

Although the thickness of the oxide film 42 is 200 nm here, it may be 400 nm. In this case, the silicon substrate 41 is oxidized at 1000 ° C., for example. The thickness of the silicon nitride film 43 is 50 nm, but may be 15 nm. In that case, the silicon nitride film 43 is formed by, for example, a low pressure CVD method using SiCl ₂ H ₂ and NH ₃ .

  Next, as shown in FIG. 11B, the silicon nitride film 43 and the oxide film 42 are processed using photolithography and RIE to form an opening 44 reaching the silicon substrate 41 in a region corresponding to the element formation region. To do. Here, the silicon nitride film 43 is etched using a photoresist as a mask, and the oxide film 42 is etched using the silicon nitride film 43 to which the photoresist pattern is transferred as a mask after peeling the photoresist. Note that the silicon nitride film 43 and the oxide film 42 may be etched using a photoresist as a mask.

Next, as a pretreatment for epitaxial growth, the substrate surface is etched by about 10 nm by a CDE (Chemical Dry Etching) method using a mixed gas of CF ₄ and oxygen to remove a damaged layer generated on the substrate surface by RIE. Then, the natural oxide film on the substrate surface is removed by wet treatment using dilute hydrofluoric acid. CDE can be replaced by RIE using O ₂ .

Next, as shown in FIG. 11C, the epitaxial layer 45 is selectively grown using the exposed substrate surface as a growth nucleus (seed). The epitaxial layer 45 is selectively grown so as to fill the opening 44 and protrude on the silicon nitride film 43. The epitaxial layer 45 is a silicon layer, a silicon germanium layer, or a germanium layer, as in the first embodiment. In the case of the silicon layer, for example, a mixed gas of SiH ₄ and H ₂ , a mixed gas of SiH ₂ Cl ₂ and H ₂ , or a gas obtained by adding HCl to these is used.

  Next, as shown in FIG. 12D, the excessive epitaxial layer 45 outside the opening 44 is removed by CMP under a condition where the polishing rate of SiN with respect to Si is sufficiently low, and the surface is flattened. For example, ceria is used for the abrasive grains.

  Next, as shown in FIG. 12E, an oxide layer 46 having a thickness of about 150 nm is formed by thermal oxidation. At this time, the position of the interface between the oxide layer 46 and the epitaxial layer 45 is approximately 75 nm below the position of the surface of the silicon nitride film 43.

  Next, as shown in FIG. 12F, after the oxide layer 46 is selectively removed by RIE, the silicon nitride film 43 is selectively removed by wet etching using a phosphoric acid solution. As a result, the position of the surface of the epitaxial layer 45 in the element formation region is lower by 25 nm than the position of the surface of the oxide film 42 in the element isolation region. Although the oxide layer 46 is removed by RIE here, it may be removed by wet etching using a BHF or DHF solution. Thereafter, a process of forming a desired semiconductor element in the epitaxial layer 45 is continued as in the prior art.

  Also in this embodiment, generation of voids and facets can be prevented as in the first embodiment, and the same effect as in the first embodiment can be obtained.

(Sixth embodiment)
FIG. 13 is a process sectional view showing a method for forming an element isolation structure according to the sixth embodiment of the present invention. 11 and 12 are denoted by the same reference numerals as those in FIGS. 11 and 12, and detailed description thereof is omitted.

  First, the steps shown in FIGS. 11A to 12D of the fifth embodiment are performed.

  Next, as shown in FIG. 13A, an oxide layer 46 having a thickness of about 50 nm is formed by thermal oxidation. At this time, the position of the interface between the oxide film 42 and the silicon nitride film 43 is approximately 25 nm below the position of the interface between the oxide layer 46 and the epitaxial layer 45. When the thickness of the silicon nitride film 43 is 15 nm, for example, thermal oxidation is performed at 900 ° C. to about 10 nm.

  Finally, as shown in FIG. 13B, the oxide layer 46 is selectively removed by RIE to complete the element isolation structure. Thereafter, as in the first embodiment, a heat treatment for planarizing the surface at the atomic level may be performed. The position of the surface of the epitaxial layer 45 in the element formation region is lower by 25 nm than the position of the surface of the silicon nitride film 43 in the element isolation region. In the case of thermal oxidation of about 10 nm, it goes down by about 10 nm.

(Seventh embodiment)
FIG. 14 is a process sectional view showing a method for forming an element isolation structure according to the seventh embodiment of the present invention. 11 and 12 are denoted by the same reference numerals as those in FIGS. 11 and 12, and detailed description thereof is omitted.

  First, the steps (including removal of a damaged layer caused by RIE and removal of a natural oxide film) shown in FIGS. 11A to 11B of the fifth embodiment are performed.

  Next, as shown in FIG. 14A, the epitaxial layer 45 is selectively grown using the exposed substrate surface as a growth nucleus (seed) so as not to protrude on the silicon nitride film 43. Accordingly, facets are generated in the opening 44. Here, selective growth is performed so that the surface of the epitaxial layer 45 is slightly higher than the surface of the silicon oxide film 42.

Next, as shown in FIG. 14B, the epitaxial layer 45 is caused to flow by annealing at 1000 ° C. for about 5 minutes in a reduced-pressure H ₂ atmosphere of about 10 Torr, and the surface of the epitaxial layer 45 is flattened. As a result, the facet disappears. Further, the surface of the epitaxial layer 45 is lower than the surface of the silicon oxide film 42.

  Finally, as shown in FIG. 14C, the silicon nitride film 43 is selectively removed by wet etching with phosphoric acid to complete the element isolation structure.

(Eighth embodiment)
FIG. 15 is a process sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment of the invention. 11 and 12 are denoted by the same reference numerals as those in FIGS. 11 and 12, and detailed description thereof is omitted.

  First, the steps from FIG. 11A to FIG. 12D of the fifth embodiment are performed.

  Next, as shown in FIG. 15A, the silicon nitride film 43 is pulled back by etching such as hot phosphoric acid treatment or glycerol hydrofluoric acid treatment, and the silicon nitride film 43 around the epitaxial layer 45 is removed. An opening 47 is formed.

  Next, as shown in FIG. 15B, a region from the surface of the epitaxial layer 45 to a depth of about 150 nm is thermally oxidized to form an oxide layer 46. As a result, the position of the interface between the oxide layer 46 and the epitaxial layer 45 is approximately 75 nm below the position of the surface of the silicon nitride film 42.

  At this time, the oxidized species diffuse through the opening 47 to the interface between the oxide film 42 and the epitaxial layer 45, and the interface is thermally oxidized, so that good element isolation characteristics can be obtained. Further, the crystallinity of the epitaxial layer 45 deteriorated by CMP is recovered by this thermal oxidation.

  Finally, as shown in FIG. 15C, after the oxide layer 46 is selectively removed by RIE, the silicon nitride film 43 is selectively removed by wet etching using phosphoric acid, thereby completing the element isolation structure. . The position of the surface of the epitaxial layer 45 in the element formation region is lower by 25 nm than the position of the surface of the oxide film 42 in the element isolation region.

(Ninth embodiment)
16 and 17 are process cross-sectional views illustrating a method for forming an element isolation structure according to the ninth embodiment of the present invention. 11 and 12 are denoted by the same reference numerals as those in FIGS. 11 and 12, and detailed description thereof is omitted.

First, as shown in FIG. 16A, as in the fifth embodiment, an oxide film 42 having a thickness of about 200 nm and a silicon nitride film 43 having a thickness of about 10 nm are sequentially formed on a silicon substrate 41. Next, as shown in FIG. 2A, an SiO ₂ film 48 having a thickness of about 50 nm and a silicon nitride film 49 having a thickness of about 50 nm are sequentially formed on the silicon nitride film 43 by a CVD method.

Next, as shown in FIG. 16B, the oxide film 42, the silicon nitride film 43, the SiO ₂ film 48, and the silicon nitride film 49 are processed using photolithography and RIE, and the opening 44 reaching the silicon substrate 41 is obtained. Form.

Next, as a pretreatment for epitaxial growth, a damaged layer generated on the substrate surface by RIE is removed by O ₂ -RIE, and then a natural oxide film on the substrate surface is removed by wet treatment using dilute hydrofluoric acid.

  Next, as shown in FIG. 16C, the epitaxial layer 45 is selectively grown using the exposed substrate surface as a growth nucleus (seed). The epitaxial layer 45 is selectively grown so as to fill the opening 44 and protrude on the silicon nitride film 49.

  Next, as shown in FIG. 16D, the excessive epitaxial layer 45 outside the opening 44 is removed by CMP under a condition in which the polishing rate of SiN with respect to Si is sufficiently slow to flatten the surface.

  Next, as shown in FIG. 17E, a region from the surface of the epitaxial layer 45 to a depth of about 150 nm is thermally oxidized to form an oxide layer 46. At this time, the crystallinity of the epitaxial 45 deteriorated by CMP is recovered.

Next, as shown in FIG. 17F, the silicon nitride film 49 is removed by wet etching using phosphoric acid, and then the oxide layer 46 and the SiO ₂ film 48 are removed by wet etching using hydrofluoric acid.

  Thereafter, the epitaxial layer 43 is thermally oxidized again to modify the interface between the oxide film 42 and the epitaxial layer 45. Thereby, good element isolation characteristics can be obtained. The reason why such interface modification is possible is that the thickness of the silicon nitride film 43 is as thin as about 10 nm.

Finally, as shown in FIG. 17G, the SiO ₂ film and the silicon nitride film 43 (not shown) formed by the re-oxidation are sequentially removed by wet etching to complete the element isolation structure.

(Tenth embodiment)
FIG. 18 is a process sectional view showing a method for forming an element isolation structure according to the tenth embodiment of the present invention.

  First, the steps of FIG. 11A to FIG. 11B of the fifth embodiment are performed.

Next, as shown in FIG. 18A, a silicon nitride film having a thickness of 5 nm is formed on the entire surface by CVD, and then the silicon nitride film is etched back by RIE using CHF ₃ gas. A silicon nitride film 50 is formed on the sidewall.

Next, as a pretreatment for epitaxial growth, the damaged layer generated on the substrate surface by RIE is removed by etching the substrate surface by about 10 nm by the CDE method using a mixed gas of CF ₄ and oxygen. Thereafter, the natural oxide film on the substrate surface is removed by a wet process using dilute hydrofluoric acid.

  Next, as shown in FIG. 18B, the epitaxial layer 45 is embedded in the opening 44. This step is the same as the step of FIG. 11C (selective growth of the epitaxial layer 45) to the step of FIG. 12D (removal of excess epitaxial 45 by CMP) of the fifth embodiment. Here, since the silicon nitride film 50 is formed on the side wall of the opening 44, no facet occurs during the selective growth of the epitaxial layer 45. The subsequent steps are the same as those after the step of FIG. 12E of the fifth embodiment (FIGS. 18C and 18D).

  When a MOS transistor having a gate oxide film thickness of 4 nm was formed on the epitaxial region 43 in the element region thus obtained, and the current-voltage characteristics were examined, no humps were observed and good transistor characteristics were obtained. It was. Further, when 100 MOS transistors were formed on the wafer surface and evaluated, no abnormal leakage current was observed. Furthermore, no crystal defects were observed at the edge of the element isolation region. This seems to be because there is no concentration of stress.

(Eleventh embodiment)
FIG. 19 is a cross-sectional view for explaining a MOS transistor according to the eleventh embodiment of the present invention. This is a cross-sectional view of a plane parallel to the channel width direction.

In the figure, 61 is a silicon layer in the element region (semiconductor layer in the semiconductor region on the substrate surface), 62 is an element isolation insulating film (silicon oxide film), 63 is a gate oxide film, 64 is a gate electrode, and P _Si is a substrate (not shown). The upper surface position of the silicon layer 61 with respect to the figure and _Pins. Indicate the upper surface position of the element isolation insulating film 62 with respect to the substrate. The silicon layer 61 is formed by any one of the methods of the first to tenth embodiments, for example. The substrate may be either a normal silicon substrate or an SOI substrate.

This embodiment is different from the prior art in that the height (step difference) δ of the upper surface position _Pins relative to the upper surface position P _Si. Is 3 times or more and 50 nm or less (3t _ox ) of the film thickness t _ox of the gate oxide film 63. ≦ δ ≦ 50 nm).

The reason why 3t _ox ≦ δ ≦ 50 nm is set is that, as will be described later, the characteristic variation of the device characteristics, in particular, the variation of the threshold voltage V _th can be made smaller than before. This makes it possible to give a margin to the manufacturing process. Further, since the oxide film thickness in the corner portion of the element formation region becomes large, the influence of the variation in the step amount δ on the corner transistor is reduced.

  FIG. 20 shows a MOS transistor obtained by improving the MOS transistor of FIG. In this MOS transistor, an element isolation insulating film 62 is also formed on the silicon layer 61 beyond the element isolation region in order to prevent divots. The dimension 65 in the channel width direction of the element isolation insulating film 62 on the silicon layer 61 is equal to or greater than the thickness of the gate oxide film 63, and the dimension in the channel width direction of the gate electrode 64 is reduced accordingly.

FIG. 21 shows the result of analyzing the relationship between the step amount δ and the threshold voltage V _th using a three-dimensional device simulator. MOS transistor of the step amount [delta] ≦ 0 is different from that of the present embodiment, the upper surface position P _ins. Is of lower type than the same or upper surface position P _Si and the upper surface position P _Si.

FIG. 21 also shows simulation conditions. Other conditions are as follows. That is, the dimension 65 is the same as the film thickness of the gate oxide film 63. Further, the p-type impurity concentration (hereinafter referred to as substrate concentration) of the silicon layer 61 is 6.6 × 10 ¹⁷ cm ⁻³ , the thickness of the gate oxide film 63 is 6 nm, and the gate electrode 64 is 7.0 × 10 ¹⁹ cm. The film thickness (trench depth) of the polysilicon film containing phosphorus having a concentration of ⁻³ and the element isolation insulating film 62 is 300 nm, and the gate oxide film 63 and the element isolation insulating film 62 are TEOS films (relative dielectrics). Rate: 3.9).

From FIG. 21, it can be seen that the variation of the threshold voltage V _th with respect to the step amount δ is small in the region of 20 nm ≦ δ. This is presumably because in this region, it is possible to effectively avoid the influence of lowering of the threshold voltage V _th due to the influence of the corner transistor. When the step amount δ is replaced with the thickness t _ox of the gate oxide film 63, the above inequality becomes 3t _ox ≦ δ.

Further, FIG. 21 shows that the fluctuation of the threshold voltage V _th with respect to the step amount δ is further reduced in the range exceeding 30 nm. However, if the step amount δ is too large, the exposure focus may be blurred, or unnecessary gate polysilicon may remain on the side wall of the opening in the element region, causing a short circuit. From the viewpoint of such a process, the upper limit of the step amount δ is preferably 100 nm, and more preferably 50 nm or less.

  In the case of the structure where the step amount δ ≦ 0, it is preferable that the step amount δ ≦ 50 nm or less as described later.

According to the present embodiment, by selecting a step amount δ of 20 to 30 nm, even if the step amount δ that varies with process variation varies by about 10 nm in σ value, the threshold voltage V _th that is a characteristic of the device is obtained. , That is, variation in threshold voltage V _th can be suppressed to 50 mV or less.

In addition, since the controllability of the threshold voltage V _th can be improved, variations in off-leakage current and saturation current can be improved.

  Moreover, it is not necessary to add a new process in order to realize this element. The only process parameter to be controlled is the step amount δ. More specifically, it is the amount of CMP of the insulating film used for element isolation. Therefore, the process cost can be increased as it is conventionally, and the manufacturing cost can be reduced.

In the present embodiment, although the film thickness of the gate oxide film has been described for the case of 6 nm, even thinner than 6 nm, by setting the step amount δ in the range of 3t _ox up to 50 nm, the threshold voltage V _th The variation of the can be reduced. In the case where there is a large variation such that the standard deviation σ of the step amount δ is larger than 10 nm, in order to compensate for this, the set value of the step amount is shifted by σ so that σ + 3t _ox to σ + 50 nm or the like. good.

  Since the tendency shown in FIG. 21 does not depend on the depth of the element isolation groove, the value of the depth of the element isolation groove is arbitrary.

FIG. 22 shows the results of examining the relationship between the step amount δ and the threshold voltage V _th for MOS transistors having different junction depths X _j . From the figure, it can be seen that the tendency shown in FIG. 21 does not depend on the junction depth X _j . Therefore, the value of the junction depth X _j is arbitrary.

FIG. 23 shows the results of examining the relationship between the step amount δ and the threshold voltage V _th for MOS transistors having different substrate concentrations N _sub . From the figure, it can be seen that the tendency shown in FIG. 21 does not depend on the substrate concentration N _sub . If the value of the substrate concentration is different from that of the present embodiment, or when the substrate concentration is distribution, by setting the step amount δ in the range of 3t _ox up to 50 nm, can reduce variations in the threshold voltage V _th.

Further, from FIG. 23, when the step amount δ ≦ 0 nm, that is, when the upper surface position P _Si is higher than the upper surface position _Pins. , The step amount δ can be achieved by controlling the standard deviation of the step amount δ to about δ / 10. In the range of ≦ 10 nm, the variation of the threshold voltage V _th can be 50 mV or less.

In a structure where the step amount is negative, that is, a structure in which the gate electrode surrounds the device region, the threshold voltage is applied while the gate extending in the vertical direction due to the increase in the step amount contributes to depletion of the corner portion. Although it is observed as a rapid drop in _Vth , if it exceeds a certain value determined by the substrate concentration and the oxide film thickness, it only turns on the vertical transistor and does not affect the corner. It can be seen that the variation of the deviation threshold voltage V _th becomes small. The reason is considered as follows.

  The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where the variation in threshold voltage is suppressed in order to improve the performance of the transistor has been described. However, the technology for suppressing the variation and the technology for reducing the resistance described in the conventional technology are appropriately combined. May be. Thereby, it is possible to further improve the performance of the transistor.

  In addition, various modifications can be made without departing from the scope of the present invention.

Process sectional drawing which shows the formation method of the element isolation structure which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the formation method of the element isolation structure following FIG. Process sectional drawing which shows the formation method of the element isolation structure which concerns on the 2nd Embodiment of this invention Process sectional drawing which shows the formation method of the element isolation structure which concerns on the 3rd Embodiment of this invention Process sectional drawing which shows the formation method of the element isolation structure following FIG. Process sectional drawing which shows the manufacturing method of the MOS transistor which concerns on the 4th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the MOS transistor following FIG. Process sectional drawing which shows the manufacturing method of the MOS transistor following FIG. Process sectional drawing which shows the manufacturing method of the MOS transistor following FIG. The figure which shows the gate length dependence of the threshold voltage _Vth of the MOS transistor formed by the method of this invention, and the conventional method Process sectional drawing which shows the formation method of the element isolation structure which concerns on the 5th Embodiment of this invention Process sectional drawing which shows the formation method of the element isolation structure following FIG. Process sectional drawing which shows the formation method of the element isolation structure which concerns on the 6th Embodiment of this invention Process sectional drawing which shows the formation method of the element isolation structure which concerns on the 7th Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 8th Embodiment of this invention. Process sectional drawing which shows the formation method of the element isolation structure which concerns on the 9th Embodiment of this invention Process sectional drawing which shows the formation method of the element isolation structure following FIG. Process sectional drawing which shows the formation method of the element isolation structure which concerns on 10th Embodiment of invention Sectional drawing for demonstrating the MOS transistor which concerns on the 11th Embodiment of this invention Sectional drawing which shows the MOS transistor which improved the MOS transistor of FIG. The figure which shows the result of having analyzed the relation between level difference amount δ and threshold voltage V _th by a three-dimensional device simulator The figure which shows the result of having investigated the relationship between those step amount (delta) and threshold voltage _Vth about MOS transistor from which junction depth _Xj differs The figure which shows the result of having investigated the relationship between those step amount (delta) and threshold voltage _Vth about MOS transistor from which board _| substrate density _| concentration _Nsub differs. Sectional drawing for demonstrating the problem of the element isolation method by the conventional STI Sectional drawing for demonstrating the problem of the element isolation method by other conventional STI Sectional drawing which shows the divot produced by the conventional element isolation method of FIG. 24, FIG. Characteristic diagram showing the gate voltage dependence of the drain current to explain the problems caused by the divot Sectional drawing for demonstrating the problem of the element isolation method by other conventional STI Sectional drawing for demonstrating the problem of the element isolation method by other conventional STI

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Thermal oxide film, 3 ... Epitaxial layer, 4 ... Silicon film, 11 ... Silicon substrate, 12 ... Single-crystal insulating film, 13 ... Oxide film (element isolation insulating film), 14 ... Epitaxial layer, 21 DESCRIPTION OF SYMBOLS ... Silicon substrate, 22 ... Thermal oxide film, 23 ... Epitaxial layer, 24 ... Silicon film, 25 ... Thermal oxide film, 26 ... Dummy gate film, 27 ... Source / drain region (extension region), 28 ... Gate side wall insulating film, DESCRIPTION OF SYMBOLS 29 ... Source / drain region, 30 ... Interlayer insulating film, 31 ... Opening, 32 ... Ion, 33 ... Channel impurity doping layer, 34 ... Gate insulating film, 35 ... TiN film, 36 ... Gate electrode, 41 ... Silicon substrate, 42 ... thermal oxide film, 43 ... silicon nitride film, 44 ... opening, 45 ... epitaxial layer, 46 ... oxide layer, 47 ... opening, 48 ... SiO ₂ film, 49 50 ... silicon nitride film, 61 ... silicon layer, 62 ... silicon oxide film (isolation insulating film), 63 ... gate oxide film, 64 ... gate electrode.

Claims (1)

An element isolation insulating film embedded in a semiconductor region of the substrate;
The element is isolated by the element isolation insulating film, the upper part protrudes above the surface of the element isolation insulating film, and the semiconductor layer of the semiconductor region,
A MOS type element in which a source / drain region, a gate insulating film and a gate electrode are formed in the semiconductor layer, and the gate electrode is formed on the element isolation insulating film in a cross section of a plane parallel to the channel width direction; Comprising
A semiconductor device, wherein an upper surface position of the semiconductor layer under the gate electrode is 20 nm or more higher than an upper surface position of the element isolation insulating film under the gate electrode.

Images