JP2008251795A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2008251795A
JP2008251795A JP2007090686A JP2007090686A JP2008251795A JP 2008251795 A JP2008251795 A JP 2008251795A JP 2007090686 A JP2007090686 A JP 2007090686A JP 2007090686 A JP2007090686 A JP 2007090686A JP 2008251795 A JP2008251795 A JP 2008251795A
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Prior art keywords
semiconductor device
die pad
lead
exposed
semiconductor
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JP4836854B2 (en
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Masahiro Tomiya
正博 富家
Daisuke Takao
大輔 高尾
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Aoi Electronics Co Ltd
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Aoi Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the occurrence of cracks, during processes of plate-processing leads, bending the leads, or the like, is prevented, and to provide a manufacturing method therefor. <P>SOLUTION: In the semiconductor device 1A, lead frames 3A and a semiconductor element 2A mounted on a die pad 4A are sealed by a resin 6A. The semiconductor element 2A is die-bonded to the die pad 4A of the lead frame, and is wire-bonded by lead frames 3A and wires 5A of the lead frame. At the bottom surface 11A of the semiconductor device 1A, the entire of the bottom surface of the die pad 4A (the surface to which the semiconductor element 2A is not die-bonded) is exposed. Around the exposed die pad 4A, there are formed projection portions 61A of a picture frame shape composed of the resin 6A for sealing the semiconductor element 2A. The projections 61A are away from the outer peripheral ends 41A of the die pad 4A by a predetermined length. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体素子を樹脂封止した半導体装置に関する。   The present invention relates to a semiconductor device in which a semiconductor element is sealed with a resin.

一方の面に半導体素子を載置し、載置部の他方の面を露出するように樹脂封止する半導体装置において、露出する載置部の外周側の封止材を額縁状に形成した半導体装置が従来技術として知られている（たとえば、特許文献１）。
特開平６−２０９０５４号公報 In a semiconductor device in which a semiconductor element is placed on one surface and resin-sealed so as to expose the other surface of the placement portion, a semiconductor in which a sealing material on the outer peripheral side of the exposed placement portion is formed in a frame shape An apparatus is known as a prior art (for example, Patent Document 1).
JP-A-6-209054

特許文献１に記載されているような従来の半導体装置では、リードをめっき処理する工程やリードを曲げる工程などで半導体素子の載置部の端面近傍を封止している樹脂材よりクラックが発生する。また、半導体装置をリフロー炉に通して半田付けするときも、リフローストレスにより同様のクラックが発生するという問題点がある。   In the conventional semiconductor device as described in Patent Document 1, cracks are generated from the resin material sealing the vicinity of the end face of the mounting portion of the semiconductor element in the lead plating process and the lead bending process. To do. Further, when soldering a semiconductor device through a reflow furnace, there is a problem that similar cracks are generated due to reflow stress.

（１）請求項１の発明は、半導体素子と、半導体素子を接合するダイパッドおよび半導体素子の表面の電極とワイヤによって接合するリードを有するリードフレームと、半導体素子、ワイヤおよびリードフレームを封止する封止材とを備えた半導体装置において、ダイパッドの半導体素子と接合していない面全体が半導体装置の底面に露出するとともに、ダイパッドの露出面の全周囲または周囲の一部に、ダイパッドの露出面の外周端より離間して凸部を備えることを特徴とする。
（２）請求項２の発明は、請求項１に記載の半導体装置において、ダイパッドは複数であり、凸部は、複数のダイパッドの露出面の全てを囲うように設けられることを特徴とする。
（３）請求項３の発明は、半導体素子と、電子部品と、半導体素子を一方の面に、電子部品を他方の面に接合するダイパッドおよび半導体素子の表面の電極とワイヤによって接合するリードを有するリードフレームと、半導体素子、電子部品、ワイヤおよびリードフレームを封止する封止材とを備えた半導体装置において、電子部品におけるダイパッドの接合面と反対側の面全体が半導体装置の底面に露出するとともに、電子部品の露出面の全周囲または周囲の一部に、電子部品の露出面の外周端より離間して凸部を備えることを特徴とする。
（４）請求項４の発明は、請求項３に記載の半導体装置において、電子部品は複数であり、凸部は、複数の電子部品の露出面の全てを囲うように設けられることを特徴とする。
（５）請求項５の発明は、請求項３または４に記載の半導体装置において、電子部品は、受光素子または撮光素子であることを特徴とする。
（６）請求項６の発明は、請求項１乃至５のいずれか１項に記載の半導体装置において、チップオンリードタイプであることを特徴とする。 (1) The invention of claim 1 encapsulates a semiconductor element, a die pad for bonding the semiconductor element, a lead frame having a lead bonded to the electrode on the surface of the semiconductor element by a wire, and the semiconductor element, the wire and the lead frame. In a semiconductor device provided with a sealing material, the entire surface of the die pad that is not bonded to the semiconductor element is exposed on the bottom surface of the semiconductor device, and the exposed surface of the die pad is entirely or partially around the exposed surface of the die pad. A convex portion is provided apart from the outer peripheral end.
(2) The invention according to claim 2 is the semiconductor device according to claim 1, wherein there are a plurality of die pads, and the convex portions are provided so as to surround all of the exposed surfaces of the plurality of die pads.
(3) The invention of claim 3 includes a semiconductor element, an electronic component, a die pad that joins the semiconductor element to one surface, and the electronic component to the other surface, and a lead that joins the electrode on the surface of the semiconductor element by a wire. In a semiconductor device having a lead frame having a semiconductor element, an electronic component, a wire, and a sealing material for sealing the lead frame, the entire surface of the electronic component opposite to the bonding surface of the die pad is exposed to the bottom surface of the semiconductor device In addition, the whole or a part of the periphery of the exposed surface of the electronic component is provided with a convex portion spaced from the outer peripheral end of the exposed surface of the electronic component.
(4) The invention of claim 4 is the semiconductor device according to claim 3, wherein there are a plurality of electronic components, and the convex portion is provided so as to surround all of the exposed surfaces of the plurality of electronic components. To do.
(5) The invention according to claim 5 is the semiconductor device according to claim 3 or 4, characterized in that the electronic component is a light receiving element or a photographing element.
(6) The invention of claim 6 is the semiconductor device according to any one of claims 1 to 5, which is a chip-on-lead type.

本発明によれば、ダイパッドの露出面の全周囲または周囲の一部に、または電子部品の露出面の全周囲または周囲の一部に、露出面の外周端より離間して凸部を備えるようにした。したがって、リードをめっき処理する工程やリードを曲げる工程、リフロー炉に通して半田付けする工程などにおけるクラックの発生を防止することができる。   According to the present invention, the entire periphery or a part of the periphery of the exposed surface of the die pad, or the entire periphery or a part of the periphery of the exposed surface of the electronic component is provided with a convex portion spaced from the outer peripheral end of the exposed surface. I made it. Therefore, it is possible to prevent the occurrence of cracks in the step of plating the lead, the step of bending the lead, the step of soldering through a reflow furnace, and the like.

−第１の実施形態−
本発明の第１の実施形態の半導体装置について図１を参照して説明する。図１（ａ）は、第１の実施形態の半導体装置１Ａの底面図であり、図１（ｂ）は、図１（ａ）のＡ−Ａ断面図である。第１の実施形態の半導体装置１Ａはリードフレームタイプである。 -First embodiment-
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1A is a bottom view of the semiconductor device 1A according to the first embodiment, and FIG. 1B is a cross-sectional view taken along line AA of FIG. The semiconductor device 1A of the first embodiment is a lead frame type.

図１（ｂ）に示すように、半導体装置１Ａは、リードフレーム３Ａ，４Ａに搭載した半導体素子２Ａを樹脂６Ａで封止したものである。半導体素子２Ａは、リードフレームのダイパッド４Ａにダイボンディングされ、リードフレームのリード３Ａとワイヤ５Ａでワイヤボンディングされる。半導体装置１Ａの底面１１Ａには、ダイパッド４Ａの底面（半導体素子２Ａがダイボンディングされていない面）全体が露出している。露出しているダイパッド４Ａの周囲には、半導体素子２Ａを封止している樹脂６Ａからなる額縁状の凸部６１Ａが形成されている。凸部６１Ａとダイパッド４Ａの外周端４１Ａとは所定長だけ離れている。凸部６１Ａの上端の幅は約０．３ｍｍであり、突起部６１Ａの底面１１Ａに対する高さは３０μｍである。   As shown in FIG. 1B, a semiconductor device 1A is obtained by sealing a semiconductor element 2A mounted on lead frames 3A and 4A with a resin 6A. The semiconductor element 2A is die-bonded to the die pad 4A of the lead frame and wire-bonded with the lead 3A of the lead frame and the wire 5A. The entire bottom surface of the die pad 4A (the surface on which the semiconductor element 2A is not die-bonded) is exposed on the bottom surface 11A of the semiconductor device 1A. Around the exposed die pad 4A, a frame-like convex portion 61A made of resin 6A sealing the semiconductor element 2A is formed. The convex portion 61A and the outer peripheral end 41A of the die pad 4A are separated by a predetermined length. The width of the upper end of the protrusion 61A is about 0.3 mm, and the height of the protrusion 61A with respect to the bottom surface 11A is 30 μm.

次に、上述した半導体装置１Ａの製造方法について、図２を参照して説明する。半導体装置１Ａの製造方法は、ダイボンディング工程、ワイヤボンディング工程、モールド工程、外装処理工程、リード成形工程およびマーク工程を備える。予めリードフレーム３Ａ，４Ａが作製されているものとして説明する。   Next, a manufacturing method of the above-described semiconductor device 1A will be described with reference to FIG. The manufacturing method of the semiconductor device 1A includes a die bonding process, a wire bonding process, a molding process, an exterior processing process, a lead molding process, and a mark process. A description will be given assuming that the lead frames 3A and 4A are prepared in advance.

（１）ダイボンディング工程
ダイボンディング工程では、不図示のダイボンディング材をダイパッド４Ａに塗布した後、図２（ａ）に示すように、ダイパッド４Ａに半導体素子２Ａを搭載する。 (1) Die Bonding Step In the die bonding step, after applying a die bonding material (not shown) to the die pad 4A, the semiconductor element 2A is mounted on the die pad 4A as shown in FIG.

（２）ワイヤボンディング工程
ワイヤボンディング工程では、図２（ｂ）に示すように、半導体素子２Ａの表面上の電極とリード３Ａとをワイヤ５Ａで接続する。 (2) Wire Bonding Step In the wire bonding step, as shown in FIG. 2B, the electrode on the surface of the semiconductor element 2A and the lead 3A are connected by the wire 5A.

（３）モールド工程
モールド工程では、まず、図２（ｃ）に示すように、半導体素子２Ａを搭載したリードフレーム３Ａ，４Ａを予備加熱された金型１０１Ａ，１０２Ａに設置する。下金型１０２Ａは、ダイパッド４Ａの底面全体と接触するので、ダイパッド４Ａの底面は樹脂に覆われない。また、下金型１０２Ａには、凹部１０３Ａが形成されている。これにより、半導体装置１Ａの底面１１Ａに凸部６１Ａを形成することができる。次に、金型１０１Ａ，１０２Ａを加熱し、金型１０１Ａ，１０２Ａ内に樹脂６Ａを投入する。樹脂６Ａには、フィラを混合したエポキシ樹脂が使用される。金型１０１Ａ，１０２Ａ内に樹脂６Ａが充填した状態で数分間保持し、樹脂を硬化させる。そして、図２（ｄ）に示すように、金型１０１Ａ，１０２Ａから樹脂封止したもの（以下、樹脂封止体１０４Ａと呼ぶ）を取り出す。取り出した樹脂封止体１０４Ａは、数時間、高温（１６０〜１８０℃）加熱される。 (3) Molding process In the molding process, first, as shown in FIG. 2 (c), lead frames 3A and 4A on which semiconductor elements 2A are mounted are placed on preheated molds 101A and 102A. Since the lower mold 102A contacts the entire bottom surface of the die pad 4A, the bottom surface of the die pad 4A is not covered with resin. Further, a recess 103A is formed in the lower mold 102A. Thereby, the convex portion 61A can be formed on the bottom surface 11A of the semiconductor device 1A. Next, the molds 101A and 102A are heated, and the resin 6A is put into the molds 101A and 102A. For the resin 6A, an epoxy resin mixed with filler is used. Holding the resin 6A in the molds 101A and 102A for several minutes, the resin is cured. Then, as shown in FIG. 2 (d), a resin-sealed one (hereinafter referred to as a resin sealing body 104A) is taken out from the molds 101A and 102A. The taken out resin sealing body 104A is heated at a high temperature (160 to 180 ° C.) for several hours.

（４）外装処理工程
外装処理工程では、半導体装置１Ａを基板に半田実装しやすくするためとリードの耐食性を向上させるために、リード３Ａにめっきを施す。 (4) Exterior treatment process In the exterior treatment process, the lead 3A is plated in order to facilitate solder mounting of the semiconductor device 1A on the substrate and to improve the corrosion resistance of the lead.

（５）リード成形工程
リード成形工程では、樹脂封止体１０４Ａのリード３Ａを曲げ、図２（ｅ）に示すように、ガルウィング形状にする。 (5) Lead molding process In the lead molding process, the lead 3A of the resin encapsulant 104A is bent into a gull wing shape as shown in FIG.

（６）マーク工程
マーク工程では、樹脂封止体１０４Ａの表面に、商標、製品名、ロット番号、識別マークなどを印字する。印字は、インクによる捺印またはレーザ加工による刻印により行う。 (6) Marking process In the marking process, a trademark, a product name, a lot number, an identification mark, and the like are printed on the surface of the resin sealing body 104A. Printing is performed by printing with ink or marking by laser processing.

以上のようにして、半導体装置１Ａが作製される。   As described above, the semiconductor device 1A is manufactured.

以上の実施形態による半導体装置１Ａは次のような作用効果を奏する。
（１）ダイパッド４Ａを全域露出させ、その露出面の全周囲に、ダイパッド４Ａの露出面の外周端４１Ａより離間して凸部６１を半導体装置１Ａに備えるようにした。したがって、リードをめっき処理する工程やリードを曲げる工程などで発生するクラック（ダイパッド４Ａと樹脂６Ａとの境界から発生するクラックなど）を防止することができる。また、リフローストレスによる同様のクラックの発生も防止することができる。 The semiconductor device 1A according to the above embodiment has the following operational effects.
(1) The entire area of the die pad 4A is exposed, and the protrusion 61 is provided in the semiconductor device 1A at a distance from the outer peripheral end 41A of the exposed surface of the die pad 4A around the entire exposed surface. Therefore, it is possible to prevent cracks (such as cracks generated from the boundary between the die pad 4A and the resin 6A) generated in the lead plating process, the lead bending process, and the like. Moreover, the occurrence of similar cracks due to reflow stress can also be prevented.

（２）半導体装置１Ａの底面１１Ａの凸部６１Ａによってダイパッド４Ａの露出面に傷が入るのを防止することができる。また、作製した複数の半導体装置１Ａは重ねられ、一時的にトレーに収納される。このとき、半導体装置１Ａの表面の印字部分と他の半導体装置１Ａのダイパッド４Ａの底面とが擦り接触して、ダイパッド４Ａの底面を被覆しているめっきが半導体装置１Ａの表面に付着して、印字が読み取れなくなることがあった。しかし、半導体装置１Ａの底面１１Ａに形成した凸部６１Ａによって、このような印字が読み取れなくなることを防止することができる。 (2) It is possible to prevent the exposed surface of the die pad 4A from being damaged by the convex portion 61A of the bottom surface 11A of the semiconductor device 1A. Further, the plurality of manufactured semiconductor devices 1A are stacked and temporarily stored in a tray. At this time, the printed portion on the surface of the semiconductor device 1A and the bottom surface of the die pad 4A of the other semiconductor device 1A rub against each other, and the plating covering the bottom surface of the die pad 4A adheres to the surface of the semiconductor device 1A. The print could not be read. However, the convex portion 61A formed on the bottom surface 11A of the semiconductor device 1A can prevent such printing from being unreadable.

−第２の実施形態−
本発明の第２の実施形態の半導体装置について図２を参照して説明する。図３（ａ）は、第２の実施形態の半導体装置１Ｂの底面図であり、図３（ｂ）は、図３（ａ）のＢ−Ｂ断面図である。第２の実施形態の半導体装置１Ｂもリードフレームタイプである。 -Second Embodiment-
A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3A is a bottom view of the semiconductor device 1B of the second embodiment, and FIG. 3B is a cross-sectional view taken along the line BB in FIG. The semiconductor device 1B of the second embodiment is also a lead frame type.

図３（ｂ）に示すように、半導体装置１Ｂは、リードフレーム３Ｂ，４Ｂに搭載した半導体素子２Ｂと受光素子７Ｂとを樹脂６Ｂで封止したものである。半導体素子２Ｂは、リードフレームのダイパッド４Ｂの一方の面（以下、表面と呼ぶ）にダイボンディングされ、受光素子７Ｂはリードフレームのダイパッド４Ｂの他方の面（以下、底面と呼ぶ）にダイボンディングされる。半導体素子２Ｂは、リードフレームのリード３Ｂとワイヤ５Ｂでワイヤボンディングされる。半導体装置１Ｂの底面１１Ｂには、受光素子７Ｂの受光面（受光素子７Ｂのダイボンディングされた面の反対の面）全体が露出している。受光素子７Ｂの受光部を保護するため、受光素子７Ｂの受光面にはガラス基板またはプラスチック基板が設けられている。露出している受光素子７Ｂの周囲には、半導体素子２Ｂおよび受光素子７Ｂを封止している樹脂６Ｂからなる額縁状の凸部６１Ｂが形成されている。凸部６１Ｂと受光素子７Ｂの露出面の外周端７１Ｂとは所定長だけ離間している。凸部６１Ｂの上端の幅は約０．３ｍｍであり、突起部６１Ｂの底面１１Ｂに対する高さは３０μｍである。   As shown in FIG. 3B, the semiconductor device 1B is obtained by sealing a semiconductor element 2B and a light receiving element 7B mounted on lead frames 3B and 4B with a resin 6B. The semiconductor element 2B is die-bonded to one surface (hereinafter referred to as the front surface) of the die pad 4B of the lead frame, and the light receiving element 7B is die-bonded to the other surface (hereinafter referred to as the bottom surface) of the die pad 4B of the lead frame. The The semiconductor element 2B is wire-bonded with leads 3B of the lead frame and wires 5B. On the bottom surface 11B of the semiconductor device 1B, the entire light receiving surface of the light receiving element 7B (the surface opposite to the die-bonded surface of the light receiving element 7B) is exposed. In order to protect the light receiving portion of the light receiving element 7B, a glass substrate or a plastic substrate is provided on the light receiving surface of the light receiving element 7B. Around the exposed light receiving element 7B, a frame-shaped convex portion 61B made of resin 6B sealing the semiconductor element 2B and the light receiving element 7B is formed. The convex portion 61B and the outer peripheral end 71B of the exposed surface of the light receiving element 7B are separated by a predetermined length. The width of the upper end of the protrusion 61B is about 0.3 mm, and the height of the protrusion 61B with respect to the bottom surface 11B is 30 μm.

次に、上述した半導体装置１Ｂの製造方法について、図４を参照して説明する。半導体装置１Ｂの製造方法は、半導体素子ダイボンディング工程、受光素子ダイボンディング工程、ワイヤボンディング工程、モールド工程、外装処理工程、リード成形工程およびマーク工程を備える。予めリードフレーム３Ｂ，４Ｂが作製されているものとして説明する。   Next, a method for manufacturing the semiconductor device 1B described above will be described with reference to FIG. The manufacturing method of the semiconductor device 1B includes a semiconductor element die bonding process, a light receiving element die bonding process, a wire bonding process, a molding process, an exterior processing process, a lead molding process, and a mark process. A description will be given assuming that the lead frames 3B and 4B are manufactured in advance.

（１）半導体素子ダイボンディング工程
半導体素子ダイボンディング工程では、不図示のダイボンディング材をダイパッド４Ｂの表面に塗布した後、図４（ａ）に示すように、ダイパッド４Ｂの表面に半導体素子２Ｂを搭載する。 (1) Semiconductor Element Die Bonding Step In the semiconductor element die bonding step, a die bonding material (not shown) is applied to the surface of the die pad 4B, and then the semiconductor element 2B is formed on the surface of the die pad 4B as shown in FIG. Mount.

（２）受光素子ダイボンディング工程
受光素子ダイボンディング工程では、不図示のダイボンディング材をダイパッド４Ｂの裏面に塗布した後、図４（ｂ）に示すように、ダイパッド４Ｂの裏面に受光素子７Ｂを搭載する。 (2) Light receiving element die bonding process In the light receiving element die bonding process, after applying a die bonding material (not shown) to the back surface of the die pad 4B, the light receiving element 7B is placed on the back surface of the die pad 4B as shown in FIG. Mount.

（３）ワイヤボンディング工程
ワイヤボンディング工程では、図４（ｃ）に示すように、半導体素子２Ｂの表面上の電極とリード３Ｂとをワイヤ５Ｂで接続する。 (3) Wire Bonding Step In the wire bonding step, as shown in FIG. 4C, the electrode on the surface of the semiconductor element 2B and the lead 3B are connected by the wire 5B.

（４）モールド工程
モールド工程では、まず、図４（ｄ）に示すように、半導体素子２Ｂおよび受光素子７Ｂを搭載したリードフレーム３Ｂ，４Ｂを予備加熱された金型１０１Ｂ，１０２Ｂに設置する。下金型１０２Ｂは、受光素子７Ｂの受光面全体と接触するので、受光素子７Ｂの受光面は樹脂に覆われない。また、下金型１０２Ｂには、凹部１０３Ｂが形成されているので、半導体装置１Ｂの底面１１Ｂに凸部６１Ｂを形成することができる。次に、金型１０１Ｂ，１０２Ｂを加熱し、金型１０１Ｂ，１０２Ｂ内に樹脂６Ｂを投入する。樹脂６Ｂにも、フィラを混合したエポキシ樹脂が使用される。金型１０１Ｂ，１０２Ｂ内に樹脂８Ｂが充填した状態で数分間保持し、樹脂を硬化させる。そして、図４（ｅ）に示すように、金型１０１Ｂ，１０２Ｂから樹脂封止したもの（以下、樹脂封止体１０４Ｂと呼ぶ）を取り出す。取り出した樹脂封止体１０４Ｂは、数時間、高温（１６０〜１８０℃）加熱される。 (4) Molding Process In the molding process, first, as shown in FIG. 4D, lead frames 3B and 4B on which the semiconductor element 2B and the light receiving element 7B are mounted are placed on preheated molds 101B and 102B. Since the lower mold 102B contacts the entire light receiving surface of the light receiving element 7B, the light receiving surface of the light receiving element 7B is not covered with resin. Further, since the recess 103B is formed in the lower mold 102B, the protrusion 61B can be formed on the bottom surface 11B of the semiconductor device 1B. Next, the molds 101B and 102B are heated, and the resin 6B is put into the molds 101B and 102B. An epoxy resin mixed with filler is also used for the resin 6B. The molds 101B and 102B are held for several minutes in a state where the resin 8B is filled, and the resin is cured. And as shown in FIG.4 (e), what was resin-sealed (henceforth the resin sealing body 104B) is taken out from metal mold | die 101B, 102B. The taken out resin sealing body 104B is heated at a high temperature (160 to 180 ° C.) for several hours.

（５）外装処理工程
外装処理工程では、半導体装置１Ｂを基板に半田実装しやすくするためとリードの耐食性を向上させるために、リード３Ｂにめっきを施す。 (5) Exterior treatment process In the exterior treatment process, the lead 3B is plated in order to facilitate solder mounting of the semiconductor device 1B on the substrate and to improve the corrosion resistance of the lead.

（６）リード成形工程
リード成形工程では、樹脂封止体１０４Ｂのリード３Ｂを曲げ、図４（ｆ）に示すように、コの字形状にする。 (6) Lead molding process In the lead molding process, the lead 3B of the resin encapsulant 104B is bent into a U shape as shown in FIG.

（７）マーク工程
マーク工程では、樹脂封止体１０４Ｂの表面に、商標、製品名、ロット番号、識別マークなどを印字する。印字は、インクによる捺印またはレーザ加工による刻印により行う。 (7) Marking process In the marking process, a trademark, a product name, a lot number, an identification mark, and the like are printed on the surface of the resin sealing body 104B. Printing is performed by printing with ink or marking by laser processing.

以上のようにして、半導体装置１Ｂが作製される。   As described above, the semiconductor device 1B is manufactured.

以上の実施形態による半導体装置１Ｂは次のような作用効果を奏する。
（１）電子部品７Ｂの露出面の全周囲に、電子部品７Ｂの露出面の外周端７１Ｂより離間して凸部６１Ｂを半導体装置１Ｂに備えるようにした。したがって、第１の実施形態と同様にリードをめっき処理する工程やリードを曲げる工程、リフローストレスなどで発生するクラックを防止することができる。 The semiconductor device 1B according to the above embodiment has the following operational effects.
(1) The convex portion 61B is provided in the semiconductor device 1B at a distance from the outer peripheral end 71B of the exposed surface of the electronic component 7B around the entire exposed surface of the electronic component 7B. Therefore, as in the first embodiment, it is possible to prevent cracks caused by the process of plating the lead, the process of bending the lead, reflow stress, and the like.

（２）半導体装置１Ｂの底面１１Ｂの凸部６１Ｂによって、受光素子７Ｂの露出面である受光面に傷が入るのを防止することができる。 (2) The convex portion 61B on the bottom surface 11B of the semiconductor device 1B can prevent the light receiving surface that is the exposed surface of the light receiving element 7B from being damaged.

以上の実施形態の半導体装置１Ａ，１Ｂを次のように変形することができる。
（１）半導体装置１Ａ，１Ｂの底面１１Ａ，１１Ｂにおいて、半導体装置１Ａ，１Ｂの突起部６１Ａ，６１Ｂは、露出しているダイパッド４Ａや受光素子７Ｂの受光面の周囲全部に設けられた。しかし、半導体装置１Ａ，１Ｂの突起部６１Ａ，６１Ｂを露出しているダイパッド４Ａや受光素子７Ｂの受光面の周囲の一部に設けるようにしてもよい。たとえば、図５（ａ）に示す半導体装置１Ｃのように、突起部６１Ｃをコの字形状とし、受光素子７Ｂの表面の周囲の一部に設けるようにしてもよい。また、図５（ｂ）に示す半導体装置１Ｄのように、一の字形状の突起部６１Ｄを受光素子７Ｂの受光面の外周に沿って設けるようにしてもよい。このようにしても、第１の実施形態および第２の実施形態と同様にリードをめっき処理する工程やリードを曲げる工程などで発生するクラックを防止することができる。また、第１の実施形態および第２の実施形態と同様に、ダイパッド４Ａや受光素子７Ｂの露出面に傷が入るのを防止することができる。 The semiconductor devices 1A and 1B of the above embodiment can be modified as follows.
(1) On the bottom surfaces 11A and 11B of the semiconductor devices 1A and 1B, the protruding portions 61A and 61B of the semiconductor devices 1A and 1B are provided all around the exposed light receiving surfaces of the die pad 4A and the light receiving element 7B. However, the protrusions 61A and 61B of the semiconductor devices 1A and 1B may be provided on a part of the periphery of the light receiving surface of the exposed die pad 4A or the light receiving element 7B. For example, like the semiconductor device 1C shown in FIG. 5A, the protrusion 61C may be formed in a U shape and provided on a part of the periphery of the surface of the light receiving element 7B. Further, like the semiconductor device 1D shown in FIG. 5B, a single-shaped protrusion 61D may be provided along the outer periphery of the light receiving surface of the light receiving element 7B. Even if it does in this way, the crack which generate | occur | produces in the process of plating a lead, the process of bending a lead, etc. similarly to 1st Embodiment and 2nd Embodiment can be prevented. Further, similarly to the first embodiment and the second embodiment, it is possible to prevent the exposed surface of the die pad 4A and the light receiving element 7B from being damaged.

（２）半導体装置１Ｂにおいて、半導体素子２Ｂとともに搭載する電子部品は受光素子７Ｂに限定されない。たとえば、撮光素子や撮像素子でもよい。撮光素子の撮光部や撮像素子の撮像部を覆っているガラス基板やプラスチック基板を保護することができる。 (2) In the semiconductor device 1B, the electronic component mounted together with the semiconductor element 2B is not limited to the light receiving element 7B. For example, a photo sensor or an image sensor may be used. It is possible to protect the glass substrate and the plastic substrate that cover the imaging unit of the imaging device and the imaging unit of the imaging device.

（３）半導体装置１Ａ，１Ｂは、ダイパッド４Ａ，４Ｂに半導体素子２Ａ，２Ｂを搭載するリードフレームタイプの半導体装置に限定されない。たとえば、図６に示す半導体装置１Ｅのように、リード３Ｅに半導体素子２Ａを搭載するもの（チップオンリード（ＣＯＬ）タイプ）でもよい。この場合、ダイアタッチフィルム（ＤＡＦ）をリード３Ｅに貼り付け、半導体素子２Ａを搭載する。 (3) The semiconductor devices 1A and 1B are not limited to lead frame type semiconductor devices in which the semiconductor elements 2A and 2B are mounted on the die pads 4A and 4B. For example, as in the semiconductor device 1E shown in FIG. 6, a semiconductor chip 2A mounted on the lead 3E (chip-on-lead (COL) type) may be used. In this case, a die attach film (DAF) is attached to the lead 3E, and the semiconductor element 2A is mounted.

（４）半導体装置１Ａの底面１１Ａに露出するダイパッド４Ａの数は複数でもよい。たとえば、図７に示す半導体装置１Ｆのように、２つのダイパッド４Ｃ，４Ｄが半導体装置１Ｆの底面１１Ｆに露出するようにしてもよい。この場合、半導体装置１Ｆの突起部６１Ｆは、複数のダイパッド４Ｃ，４Ｄの全てを囲うように設けられる。また、半導体装置１Ｂの底面１１Ｂに露出する電子部品７Ｂの数は複数でもよい。たとえば、図８に示す半導体装置１Ｇのように、２つの電子部品７Ｃ，７Ｄの表面が半導体装置１Ｇの底面１１Ｇに露出するようにしてもよい。この場合、半導体装置１Ｇの突起部６１Ｇは、複数の電子部品７Ｃ，７Ｄの露出面の全てを囲うように設けられる。これらの場合もクラックや複数の露出面に発生する傷などを防止することができる。 (4) The number of die pads 4A exposed on the bottom surface 11A of the semiconductor device 1A may be plural. For example, as in the semiconductor device 1F shown in FIG. 7, two die pads 4C and 4D may be exposed on the bottom surface 11F of the semiconductor device 1F. In this case, the protrusion 61F of the semiconductor device 1F is provided so as to surround all of the plurality of die pads 4C and 4D. Also, the number of electronic components 7B exposed on the bottom surface 11B of the semiconductor device 1B may be plural. For example, like the semiconductor device 1G shown in FIG. 8, the surfaces of the two electronic components 7C and 7D may be exposed on the bottom surface 11G of the semiconductor device 1G. In this case, the protrusion 61G of the semiconductor device 1G is provided so as to surround all of the exposed surfaces of the plurality of electronic components 7C and 7D. In these cases as well, cracks and scratches generated on a plurality of exposed surfaces can be prevented.

以上の説明はあくまで一例であり、発明は、上記の実施形態に何ら限定されるものではない。   The above description is merely an example, and the present invention is not limited to the above embodiment.

本発明の第１の実施形態の半導体装置の構成を説明するための図である。It is a figure for demonstrating the structure of the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施形態の半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の第２の実施形態の半導体装置の構成を説明するための図である。It is a figure for demonstrating the structure of the semiconductor device of the 2nd Embodiment of this invention. 本発明の第２の実施形態の半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention. 本発明の第２の実施形態の半導体装置の突起部における変形例を説明するための図である。It is a figure for demonstrating the modification in the projection part of the semiconductor device of the 2nd Embodiment of this invention. 本発明の第２の実施形態の半導体装置をチップオンリードタイプに変形したときの変形例を説明するための図である。It is a figure for demonstrating the modification when the semiconductor device of the 2nd Embodiment of this invention deform | transforms into a chip on lead type. 本発明の第１の実施形態の半導体装置のダイパッドを２つにしたときの変形例を説明するための図である。It is a figure for demonstrating the modification when the die pad of the semiconductor device of the 1st Embodiment of this invention is made into two. 本発明の第２の実施形態の半導体装置の内蔵電子部品を２つにしたときの変形例を説明するための図である。It is a figure for demonstrating the modification when the built-in electronic component of the semiconductor device of the 2nd Embodiment of this invention is made into two.

符号の説明Explanation of symbols

１Ａ〜１Ｇ 半導体装置
２Ａ〜２Ｄ 半導体素子
３Ａ，３Ｂ リード
４Ａ〜４Ｃ ダイパッド
５Ａ，５Ｂ，５Ｆ ワイヤ
６Ａ，６Ｂ，６Ｅ〜６Ｇ 樹脂
７Ｂ〜７Ｄ 電子部品
１１Ａ，１１Ｂ，１１Ｅ〜１１Ｇ 半導体装置の裏面
６１Ａ〜６１Ｇ 突起部 1A to 1G Semiconductor devices 2A to 2D Semiconductor elements 3A and 3B Leads 4A to 4C Die pads 5A, 5B, 5F Wires 6A, 6B, 6E to 6G Resins 7B to 7D Electronic components 11A, 11B, 11E to 11G 61G Protrusion

Claims (6)

半導体素子と、
前記半導体素子を接合するダイパッドおよび前記半導体素子の表面の電極とワイヤによって接合するリードを有するリードフレームと、
前記半導体素子、前記ワイヤおよび前記リードフレームを封止する封止材とを備えた半導体装置において、
前記ダイパッドの前記半導体素子と接合していない面全体が前記半導体装置の底面に露出するとともに、前記ダイパッドの露出面の全周囲または周囲の一部に、前記ダイパッドの露出面の外周端より離間して凸部を備えることを特徴とする半導体装置。 A semiconductor element;
A lead frame having a die pad for bonding the semiconductor element and a lead bonded to the electrode on the surface of the semiconductor element by a wire;
In a semiconductor device including the semiconductor element, the wire, and a sealing material for sealing the lead frame,
The entire surface of the die pad that is not bonded to the semiconductor element is exposed at the bottom surface of the semiconductor device, and is spaced apart from the outer peripheral edge of the exposed surface of the die pad at the entire periphery or a part of the periphery of the exposed surface of the die pad. And a convex portion. 請求項１に記載の半導体装置において、
前記ダイパッドは複数であり、
前記凸部は、前記複数のダイパッドの露出面の全てを囲うように設けられることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The die pad is plural,
The convex portion is provided so as to surround all of the exposed surfaces of the plurality of die pads. 半導体素子と、
電子部品と、
前記半導体素子を一方の面に、前記電子部品を他方の面に接合するダイパッドおよび前記半導体素子の表面の電極とワイヤによって接合するリードを有するリードフレームと、
前記半導体素子、前記電子部品、前記ワイヤおよび前記リードフレームを封止する封止材とを備えた半導体装置において、
前記電子部品における前記ダイパッドの接合面と反対側の面全体が前記半導体装置の底面に露出するとともに、前記電子部品の露出面の全周囲または周囲の一部に、前記電子部品の露出面の外周端より離間して凸部を備えることを特徴とする半導体装置。 A semiconductor element;
Electronic components,
A lead frame having a lead for joining the semiconductor element to one surface, a die pad for joining the electronic component to the other face, and an electrode on the surface of the semiconductor element by a wire;
In a semiconductor device comprising the semiconductor element, the electronic component, the wire and a sealing material for sealing the lead frame,
The entire surface of the electronic component opposite to the bonding surface of the die pad is exposed on the bottom surface of the semiconductor device, and the entire periphery of the exposed surface of the electronic component or a part of the periphery is the outer periphery of the exposed surface of the electronic component. A semiconductor device comprising a convex portion spaced apart from an end. 請求項３に記載の半導体装置において、
前記電子部品は複数であり、
前記凸部は、前記複数の電子部品の露出面の全てを囲うように設けられることを特徴とする半導体装置。 The semiconductor device according to claim 3.
The electronic component is plural,
The convex portion is provided so as to surround all of the exposed surfaces of the plurality of electronic components. 請求項３または４に記載の半導体装置において、
前記電子部品は、受光素子または撮光素子であることを特徴とする半導体装置。 The semiconductor device according to claim 3 or 4,
The semiconductor device according to claim 1, wherein the electronic component is a light receiving element or a photographic element. 請求項１乃至５のいずれか１項に記載の半導体装置において、
チップオンリードタイプであることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 5,
A semiconductor device characterized by being a chip-on-lead type.
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JP2012195492A (en) * 2011-03-17 2012-10-11 Mitsubishi Electric Corp Power semiconductor module and attachment structure of the same
WO2016092938A1 (en) * 2014-12-08 2016-06-16 株式会社村田製作所 Packaged power semiconductor and mounted structure of packaged power semiconductors
JPWO2016092938A1 (en) * 2014-12-08 2017-09-07 株式会社村田製作所 Packaged power semiconductor and packaged power semiconductor mounting structure

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