JP2008249611A - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device Download PDF

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JP2008249611A
JP2008249611A JP2007093633A JP2007093633A JP2008249611A JP 2008249611 A JP2008249611 A JP 2008249611A JP 2007093633 A JP2007093633 A JP 2007093633A JP 2007093633 A JP2007093633 A JP 2007093633A JP 2008249611 A JP2008249611 A JP 2008249611A
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solder film
original image
semiconductor device
manufacturing
luminance
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JP5018182B2 (en
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Takanori Okita
孝典 沖田
Koichi Suzuki
浩一 鈴木
Kanehisa Yamamoto
兼久 山本
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Renesas Technology Corp
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Renesas Technology Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device capable of accurately determining the existence of defectives. <P>SOLUTION: A solder film is formed at first on an electrode. Then, the solder film is irradiated diagonally with a light, and a reflected light thereof is measured to obtain an original image. Then, the laminance of the original image is differentiated along the long-side direction to obtain a differential data. Then, the differential data are integrated along a short-side direction to find an integrated value. Then, the defective is determined, when a difference between the maximum value and the minimum value of the integrated value is a prescribed value or larger; and when the width between the position of the integrated value becoming a maximum and the position of the integrated value becoming a minimum is equal to a prescribed width or smaller. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、電極上に半田膜を形成し、この半田膜について不良の有無を判定する半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device in which a solder film is formed on an electrode and whether or not the solder film is defective is determined.

半導体チップと配線基板とを接続する場合にフリップチップボンディングが用いられる。フリップチップボンディングは、予め配線基板の電極上に半田膜を形成し、この半田膜を介して半導体チップの外部端子を配線基板の電極に接続するものである(例えば、特許文献1参照)。   Flip chip bonding is used when connecting a semiconductor chip and a wiring board. In flip chip bonding, a solder film is formed in advance on an electrode of a wiring board, and external terminals of the semiconductor chip are connected to the electrode of the wiring board through this solder film (see, for example, Patent Document 1).

図48,図49は、電極上に形成した半田膜を上方から撮影した図である。図48に示すように電極の途中に半田が無い部分があるDC(Dewet Center)不良や、図49に示すように電極の端に半田が無い部分があるDE(Dewet Edge)不良が発生する場合がある。   48 and 49 are images of the solder film formed on the electrode taken from above. 48, when there is a DC (Dewet Center) defect where there is no solder in the middle of the electrode or a DE (Dewet Edge) defect where there is no solder at the end of the electrode as shown in FIG. There is.

特開2006−324642号公報JP 2006-324642 A

従来は、DC不良やDE不良の有無を下記のように判定していた。まず、半田膜に斜めから光を当て反射光を測定して原画像を得る。そして、この原画像を輝度が閾値より上か下かで2値化したものを見て不良の有無を判定していた。しかし、電極の狭ピッチ化などにより、従来の方法では、不良品の見逃しや、良品を不良と判断する虚報が多いという問題があった。   Conventionally, the presence or absence of DC failure or DE failure has been determined as follows. First, light is applied obliquely to the solder film and the reflected light is measured to obtain an original image. Then, the presence or absence of a defect is determined by looking at the original image binarized depending on whether the luminance is above or below the threshold. However, due to the narrowing of the pitch of the electrodes and the like, the conventional method has a problem that there are many false reports for overlooking a defective product and determining that a non-defective product is defective.

また、半田膜の半田量が不足する不良が発生する場合がある。しかし、従来は、レーザ変位計による高さ測定により半田量不足の有無を判定していたため、測定に時間がかかるという問題があった。   Moreover, a defect that the solder amount of the solder film is insufficient may occur. However, conventionally, since it was determined whether or not the amount of solder was insufficient by measuring the height with a laser displacement meter, there was a problem that it took a long time to measure.

また、異物の存在などによりリード間のギャップが狭くなり過ぎる不良が発生する場合がある。しかし、異物はDC不良やDE不良に比べて配線基板の絶縁膜表面との輝度の差が小さいため、識別が困難であった。   In addition, there may be a defect in which the gap between the leads becomes too narrow due to the presence of foreign matter. However, it is difficult to identify the foreign matter because the difference in luminance from the surface of the insulating film of the wiring board is smaller than the DC failure or the DE failure.

また、フラックス残渣などに起因して半田が腐食して黒くなる黒色不良が発生する場合がある。図50は、黒色不良が発生した半田膜を示すレーザ顕微鏡画像である。従来は、半田膜に斜めから光を当て反射光を測定して得た原画像を見ることで、黒色不良の有無を判定していた。しかし、従来の方法により得た原画像では、図51に示すように、半田膜の傾斜面は白く映るが、平面が黒く映る。従って、軽微な黒色不良については検出が困難であった。   In addition, black defects may be generated in which the solder corrodes and becomes black due to a flux residue or the like. FIG. 50 is a laser microscope image showing a solder film in which a black defect has occurred. Conventionally, the presence or absence of a black defect has been determined by observing an original image obtained by irradiating light on the solder film obliquely and measuring the reflected light. However, in the original image obtained by the conventional method, as shown in FIG. 51, the inclined surface of the solder film appears white, but the plane appears black. Therefore, it was difficult to detect minor black defects.

本発明は、上述のような課題を解決するためになされたもので、その第1の目的は、不良の有無を正確に判定することができる半導体装置の製造方法を得るものである。   The present invention has been made to solve the above-described problems, and a first object thereof is to obtain a semiconductor device manufacturing method capable of accurately determining the presence or absence of defects.

本発明の第2の目的は、半田膜の半田量不足の有無を迅速に判定することができる半導体装置の製造方法を得るものである。   A second object of the present invention is to obtain a method of manufacturing a semiconductor device that can quickly determine whether or not the solder film has a short amount of solder.

本発明の第3の目的は、異物の存在などによりリード間のギャップが狭くなり過ぎる不良の有無を判定することができる半導体装置の製造方法を得るものである。   A third object of the present invention is to obtain a method of manufacturing a semiconductor device that can determine the presence or absence of a defect in which the gap between leads becomes too narrow due to the presence of foreign matter.

本発明の第4の目的は、軽微な黒色不良についても検出することができる半導体装置の製造方法を得るものである。   A fourth object of the present invention is to obtain a method of manufacturing a semiconductor device that can detect even a slight black defect.

本発明の一実施例に係る半導体装置の製造方法では、まず、電極上に半田膜を形成する。次に、半田膜に斜めから光を当て反射光を測定して原画像を得る。次に、原画像の輝度を長辺方向に微分して微分データを得る。次に、微分データを短辺方向に積算して積算値を求める。次に、積算値の最大値と最小値の差が所定の値以上であり、積算値が最大となる位置と最小となる位置の幅が所定の幅以下である場合に不良と判定する。   In the method of manufacturing a semiconductor device according to one embodiment of the present invention, first, a solder film is formed on an electrode. Next, light is applied obliquely to the solder film and the reflected light is measured to obtain an original image. Next, differential data is obtained by differentiating the luminance of the original image in the long side direction. Next, the differential data is integrated in the short side direction to obtain an integrated value. Next, when the difference between the maximum value and the minimum value of the integrated values is equal to or greater than a predetermined value and the width between the position where the integrated value is maximum and the minimum position is equal to or less than the predetermined width, it is determined as defective.

この実施例によれば、不良の有無を正確に判定することができる。   According to this embodiment, the presence / absence of a defect can be accurately determined.

以下、本発明の実施の形態に係る半導体装置の製造方法について図面を参照しながら詳細に説明する。   Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described in detail with reference to the drawings.

まず、図1に示すように、配線基板11上にCu電極12(電極)を形成する。このCu電極12は40μmピッチで並んでおり、その平面形状は長辺と短辺を有する。   First, as shown in FIG. 1, a Cu electrode 12 (electrode) is formed on a wiring board 11. The Cu electrodes 12 are arranged at a pitch of 40 μm, and the planar shape has a long side and a short side.

次に、図2に示すように、Cu電極12上に、半田粒子と液状有機物を混合した半田ペースト13を印刷する。ここで、半田粒子として鉛フリー半田を用いる。鉛フリー半田とは、鉛が含まれていないか、又は環境負荷が少ない程度(1wt%未満)の鉛しか含まれていない半田である。ここでは、鉛フリー半田として、SnにAgが1〜3%含有したものを用いる。   Next, as shown in FIG. 2, a solder paste 13 in which solder particles and a liquid organic material are mixed is printed on the Cu electrode 12. Here, lead-free solder is used as the solder particles. The lead-free solder is a solder that does not contain lead or contains only lead with a low environmental load (less than 1 wt%). Here, as the lead-free solder, Sn containing 1 to 3% of Ag is used.

次に、図3に示すように、リフローを行ってCu電極12上に半田膜14を形成する。ただし、この際に、半田膜14上に半田ボール15も形成される。次に、図4に示すように、半田ペースト13を洗浄により除去する。そして、図5に示すように、再びリフローを行って半田ボール15を消滅させる。この後に、半田膜14について不良の有無を判定するが、これについては後で詳細に説明する。   Next, as shown in FIG. 3, reflow is performed to form a solder film 14 on the Cu electrode 12. At this time, however, solder balls 15 are also formed on the solder film 14. Next, as shown in FIG. 4, the solder paste 13 is removed by washing. Then, as shown in FIG. 5, reflow is performed again to eliminate the solder balls 15. Thereafter, whether or not the solder film 14 is defective is determined. This will be described in detail later.

次に、図6に示すように、ディスペンサ16を用いて、Cu電極12を覆うようにNCP(Non Conductive Paste)17を塗布する。そして、図7に示すように、半導体チップ18の実装面を下に向けて、半導体チップ18を配線基板11上に仮搭載する。この際、半導体チップ18の実装面に形成されたAuスタッドバンプ19(外部端子)を、配線基板11のCu電極12に形成された半田膜14に接触させる。   Next, as shown in FIG. 6, NCP (Non Conductive Paste) 17 is applied using a dispenser 16 so as to cover the Cu electrode 12. Then, as shown in FIG. 7, the semiconductor chip 18 is temporarily mounted on the wiring board 11 with the mounting surface of the semiconductor chip 18 facing down. At this time, the Au stud bump 19 (external terminal) formed on the mounting surface of the semiconductor chip 18 is brought into contact with the solder film 14 formed on the Cu electrode 12 of the wiring board 11.

次に、図8に示すように、ツール21を用いてテフロン(登録商標)シート22を介して半導体チップ18を上から加圧する。この際、ツール21により半導体チップ18を150℃程度に加熱する。これにより、NCP17を硬化させるとともに、半田膜14を溶融させて半導体チップ18のAuスタッドバンプ19を配線基板11のCu電極12に半田付けする。以上の工程により、図9に示すように、配線基板11上に半導体チップ18がフリップチップボンディングされた半導体装置が製造される。   Next, as shown in FIG. 8, the semiconductor chip 18 is pressed from above through a Teflon (registered trademark) sheet 22 using a tool 21. At this time, the semiconductor chip 18 is heated to about 150 ° C. by the tool 21. As a result, the NCP 17 is cured and the solder film 14 is melted to solder the Au stud bump 19 of the semiconductor chip 18 to the Cu electrode 12 of the wiring board 11. Through the above steps, a semiconductor device in which the semiconductor chip 18 is flip-chip bonded onto the wiring substrate 11 is manufactured as shown in FIG.

次に、半田膜14について不良の有無を判定する工程について、図10のフローチャートを参照しながら詳細に説明する。   Next, the process of determining whether or not the solder film 14 is defective will be described in detail with reference to the flowchart of FIG.

図11は、半田膜を照明及び撮影するための光学系を示す図である。この光学系は、CCDエリアカメラ31と、XYZテーブル32と、ガラス校正基板33と、X,Y軸のガルバノミラー34,35と、X,Y軸のラインセンサ36,37と、レンズ38と、対物レンズ23と、同軸照明手段24と、リング照明手段25とを有する。CCDエリアカメラ31は測定対象を撮影する撮影手段である。XYZテーブル32は、測定対象をX軸、Y軸、Z軸方向にそれぞれ移動させる。   FIG. 11 is a diagram showing an optical system for illuminating and photographing the solder film. This optical system includes a CCD area camera 31, an XYZ table 32, a glass calibration substrate 33, X and Y axis galvanometer mirrors 34 and 35, X and Y axis line sensors 36 and 37, a lens 38, The objective lens 23, the coaxial illumination means 24, and the ring illumination means 25 are provided. The CCD area camera 31 is a photographing means for photographing a measurement target. The XYZ table 32 moves the measurement target in the X-axis, Y-axis, and Z-axis directions, respectively.

照明系について更に詳細に説明する。図12は、半田膜を照明するための光学系を示す図である。対物レンズ23は反射光を入力する光入力手段である。同軸照明手段24は、例えば青色LEDからなり、対物レンズ23と同軸で半田膜14を照明する。リング照明手段25は、半田膜14の上に円心が位置するリング状に構成され、13°,21°,32°の3段階の角度で半田膜14を照明する。リング照明手段25により半田膜14に斜めから光を当てると、図13に示すように半田膜14の斜面からの反射光が得られる。また、同軸照明手段24により半田膜14を照明すると、図14に示すように半田膜14の平面からの反射光が得られる。   The illumination system will be described in further detail. FIG. 12 is a diagram showing an optical system for illuminating the solder film. The objective lens 23 is a light input means for inputting reflected light. The coaxial illumination means 24 is made of, for example, a blue LED, and illuminates the solder film 14 coaxially with the objective lens 23. The ring illumination means 25 is configured in a ring shape with a circular center located on the solder film 14, and illuminates the solder film 14 at three angles of 13 °, 21 °, and 32 °. When light is applied obliquely to the solder film 14 by the ring illumination means 25, reflected light from the slope of the solder film 14 is obtained as shown in FIG. When the solder film 14 is illuminated by the coaxial illumination means 24, reflected light from the plane of the solder film 14 is obtained as shown in FIG.

まず、リング照明手段25を用いて半田膜14に斜めから光を当て反射光を測定して図15に示すような原画像を得る。この原画像において、半田膜14の斜面は白く写り、半田膜14の平面は黒く写る。なお、図面の横方向がCu電極の短辺方向であり、図面の縦方向がCu電極の長辺方向である。   First, the ring illumination means 25 is used to apply light obliquely to the solder film 14 and measure the reflected light to obtain an original image as shown in FIG. In this original image, the slope of the solder film 14 appears white, and the plane of the solder film 14 appears black. In addition, the horizontal direction of drawing is the short side direction of Cu electrode, and the vertical direction of drawing is the long side direction of Cu electrode.

次に、原画像の輝度を長辺方向に微分して図16に示すような微分データを得る。そして、この微分データを短辺方向に積算して図17に示すように積算値を求める。この積算値の最大値と最小値の差が所定の値以上であり、積算値が最大となる位置と最小となる位置の幅が所定の幅以下である場合に不良と判定する(ステップS1)。   Next, differential data as shown in FIG. 16 is obtained by differentiating the luminance of the original image in the long side direction. Then, the differential data is integrated in the short side direction to obtain an integrated value as shown in FIG. When the difference between the maximum value and the minimum value of the integrated values is equal to or greater than a predetermined value, and the width between the position where the integrated value is maximum and the minimum position is equal to or less than the predetermined width, it is determined as defective (step S1). .

次に、ステップS1で閾値を大きく外れて不良と判定された場合は、不良であると確定して判定を終了する。一方、ステップS1で良否判定の閾値ぎりぎりで不良と判定された場合は、次の検出を行う(ステップS2)。   Next, when it is determined that the threshold value is greatly deviated in step S1, it is determined as defective and the determination is terminated. On the other hand, if it is determined in step S1 that there is a defect just below the threshold for determining pass / fail, the next detection is performed (step S2).

図18に示すようにDC不良があると、Cu電極上において輝度が閾値より低い黒い領域が2個以上に分かれる。従って、黒い領域が2個以上に分かれている場合は不良と判定し、黒い領域が1個以下の場合は良好と判断する(ステップS3)。白い領域から黒い領域への変化が明確で無い場合には、ステップS1の検査ではDC不良の有無を判定することはできないが、ステップS3の検査ならば判定することができる。   As shown in FIG. 18, when there is a DC failure, the black region whose luminance is lower than the threshold is divided into two or more on the Cu electrode. Therefore, when the black area is divided into two or more, it is determined as defective, and when the black area is one or less, it is determined as good (step S3). If the change from the white area to the black area is not clear, the presence or absence of DC failure cannot be determined by the inspection in step S1, but it can be determined by the inspection in step S3.

ステップS1で良好と判定した場合やS3で黒い領域が1個以下と判定した場合には、下記のようにDE不良の有無を検査する。まず、ステップS1と同様に、図19に示す原画像の輝度を長辺方向に微分して微分データを得て、この微分データの輝度を短辺方向に積算して図20に示すように積算値を求める。Cu電極上において、この積算値の最大値が所定の値以上である場合に不良と判定する(ステップS4)。   If it is determined in step S1 that it is good, or if it is determined in S3 that there are one or less black areas, the presence or absence of a DE failure is inspected as follows. First, as in step S1, the luminance of the original image shown in FIG. 19 is differentiated in the long side direction to obtain differential data, and the luminance of this differential data is integrated in the short side direction and integrated as shown in FIG. Find the value. On the Cu electrode, when the maximum value of the integrated value is not less than a predetermined value, it is determined as defective (step S4).

なお、Cu電極が細い場合は半田膜の斜面の割合が多くなる。そこで、微分データを得る際に、図21に示すようにCu電極の短辺方向の真中部分だけについて原画像の輝度を長辺方向に微分するのが好ましい。これにより、Cu電極が細い場合でもDE不良の特徴を捉えることができる。   When the Cu electrode is thin, the ratio of the slope of the solder film increases. Therefore, when obtaining the differential data, it is preferable to differentiate the luminance of the original image in the long side direction only for the middle part of the Cu electrode in the short side direction as shown in FIG. Thereby, even when the Cu electrode is thin, it is possible to capture the feature of DE failure.

ステップS4で不良と判定した場合には、 図19に示すような原画像の輝度を短辺方向に積算して図22に示すように積算値を求める。Cu電極上において、この積算値が、その最大値の60%以下となる部分があると不良と判定する(ステップS5)。   If it is determined to be defective in step S4, the luminance of the original image as shown in FIG. 19 is integrated in the short side direction to obtain an integrated value as shown in FIG. If there is a portion on the Cu electrode where the integrated value is 60% or less of the maximum value, it is determined as defective (step S5).

ステップS4又はS5で良好と判定した場合、図23に示すように原画像において半田膜の外周部の近似曲線を最小二乗法により求める(ステップS6)。近似曲線を求めることができない場合は、判定値を厳しくしてステップS4と同様の検査を行う(ステップS7)。一方、近似曲線が求められた場合は、原画像を輝度が閾値より上か下かで2値化し、白い領域の近似曲線からのはみ出し面積が所定の値以上の場合は不良と判定する(ステップS8)。これによりCu電極上における異物の有無を検査することができる。   If it is determined as good in step S4 or S5, an approximate curve of the outer periphery of the solder film in the original image is obtained by the least square method as shown in FIG. 23 (step S6). If the approximate curve cannot be obtained, the determination value is tightened and the same inspection as in step S4 is performed (step S7). On the other hand, when the approximate curve is obtained, the original image is binarized depending on whether the luminance is above or below the threshold value, and when the protruding area from the approximate curve of the white region is equal to or larger than a predetermined value, it is determined as defective (step S8). Thereby, the presence or absence of foreign matter on the Cu electrode can be inspected.

次に、DE不良の有無について2値検査を行う。図24はDE不良を有する半田膜のレーザ顕微鏡画像であり、図25はDE不良を有する半田膜に斜めから光を当て反射光を測定して得た原画像であり、図26は図25の原画像を輝度が閾値より上か下かで2値化した画像である。この2値化した画像において、白色領域の長辺方向のエッジと電極の中心との幅が所定の幅以下の場合は不良と判定する(ステップS9)。   Next, a binary inspection is performed for the presence or absence of a DE failure. FIG. 24 is a laser microscope image of a solder film having a DE defect, FIG. 25 is an original image obtained by measuring the reflected light by shining light on the solder film having a DE defect, and FIG. This is an image obtained by binarizing the original image depending on whether the luminance is above or below the threshold. In the binarized image, if the width between the edge of the long side direction of the white region and the center of the electrode is equal to or smaller than a predetermined width, it is determined as defective (step S9).

ステップS9で不良と判定した場合は、DE不良の有無について多値検査を行う。即ち、図27に示すように原画像にエッジ強調処理を行う。この処理後の画像において、白色領域の長辺方向のエッジと電極の中心との幅が所定の幅以下の場合は不良と判定する(ステップS10)。このようにエッジ強調処理を行うことにより、半田膜の表面のシワの影響を排除することができる。   If it is determined to be defective in step S9, a multi-value inspection is performed for the presence or absence of a DE defect. That is, edge enhancement processing is performed on the original image as shown in FIG. In this processed image, if the width between the edge of the long side direction of the white region and the center of the electrode is equal to or smaller than a predetermined width, it is determined as defective (step S10). By performing the edge emphasis process in this way, the influence of wrinkles on the surface of the solder film can be eliminated.

ステップS10で不良と判断した場合は、図28に示すように原画像において半田膜の外周部の近似曲線を最小二乗法により求める(ステップS11)。近似曲線が求められた場合は、近似曲線同士の短辺方向の幅が所定の幅以下の場合は不良と判定する(ステップS12)。これにより、Cu電極上に半田が殆ど載っていないディウェットの有無を検査することができる。   If it is determined that it is defective in step S10, an approximate curve of the outer periphery of the solder film is obtained in the original image by the least square method as shown in FIG. 28 (step S11). When the approximate curve is obtained, if the width in the short side direction between the approximate curves is equal to or smaller than the predetermined width, it is determined as defective (step S12). Thereby, it is possible to inspect for the presence or absence of dewetting with almost no solder on the Cu electrode.

次に、DE不良の有無について2値面積検査を行う。即ち、図29に示すように、原画像の所定の測定領域内において輝度が閾値以上の白い領域の面積が所定の値以下の場合に不良と判定する(ステップS13)。これにより、半田の斜面が少ない不良を検出することができる。   Next, a binary area inspection is performed for the presence or absence of a DE failure. That is, as shown in FIG. 29, when the area of a white area whose luminance is equal to or greater than a threshold value within a predetermined measurement area of the original image is equal to or less than a predetermined value, it is determined as defective (step S13). Thereby, it is possible to detect a defect with a small solder slope.

ステップS13で不良と判定した半田膜に限り、図30に示すようにレーザ変位計により高さを測定する(ステップS14)。これにより、測定時間の長いレーザ高さ測定の回数を減らして生産効率を上げることができる。   Only the solder film determined to be defective in step S13 is measured with a laser displacement meter as shown in FIG. 30 (step S14). As a result, the number of laser height measurements with a long measurement time can be reduced to increase production efficiency.

レーザ高さ測定は、図31,図32に示すようにA点、B点、C点について行う。A点はCu電極12から引き出されたCuリード26上の領域であり、B点はCu電極12からA点とは反対方向に引き出されたCuリード26上の領域であり、C点はCu電極12の中心を含む16μm四方の領域である。各点においてそれぞれ長辺方向及び短辺方向に複数箇所の高さを測定し、最高点を各点の測定値とする。   Laser height measurement is performed at points A, B, and C as shown in FIGS. Point A is a region on the Cu lead 26 drawn from the Cu electrode 12, point B is a region on the Cu lead 26 drawn from the Cu electrode 12 in the direction opposite to the point A, and point C is the Cu electrode. This is a 16 μm square region including 12 centers. At each point, the height of a plurality of points is measured in the long side direction and the short side direction, and the highest point is taken as the measured value of each point.

A点とB点の低い方の高さをHABとし、C点の高さをHとして、5<H−HAB+2<20(μm)の関係を満たせば、良好と判定する。即ち、Cu電極12上の半田膜14の高さとCu電極12から引き出されたCuリード26の高さとの差が3μm以下又は18μm以上の場合は不良と判定する。 The lower height of the point A and point B and H AB, the height of the point C as H C, satisfies the relationship 5 <H C -H AB +2 < 20 (μm), determined as good. That is, if the difference between the height of the solder film 14 on the Cu electrode 12 and the height of the Cu lead 26 drawn from the Cu electrode 12 is 3 μm or less or 18 μm or more, it is determined as defective.

ここで、2μmを足しているのは、A点,B点においても2μm程度は半田が載っているからである。また、A点とB点の低い方を基準にC点との差を求めたのは、Cuリード26が傾いている場合があるからである。   Here, the reason why 2 μm is added is that the solder is placed on the points A and B about 2 μm. The reason why the difference between the point A and the point B is obtained on the basis of the lower one of the points A and B is that the Cu lead 26 may be inclined.

次に、以下の第1,第2の画像処理を施した原画像において、輝度が閾値以上の領域同士の最も近い位置の間隔が所定の長さ以下の場合に不良と判定する狭ギャップ検査を行う(ステップS15)。これにより、図33に示すように、異物27の存在などによりギャップが狭くなり過ぎる不良の有無を判定することができる。   Next, in the original image subjected to the following first and second image processing, a narrow gap inspection is performed in which a defect is determined when the distance between the closest positions of areas having luminance equal to or higher than a threshold is equal to or less than a predetermined length. This is performed (step S15). Accordingly, as shown in FIG. 33, it is possible to determine whether there is a defect in which the gap is too narrow due to the presence of the foreign matter 27 or the like.

第1の画像処理として、原画像について、図34に示すように、Cu電極12から引き出されたCuリード26に相当する部分の輝度を閾値以上に上げる処理(白く塗りつぶす)を行う。Cuリード26上には薄く半田が載っているだけなので、原画像において黒と白が混ざったように写る。従って、この部分を白く塗りつぶすことで、狭ギャップ検査において誤判定を防ぐことができる。   As the first image processing, as shown in FIG. 34, processing for increasing the luminance of the portion corresponding to the Cu lead 26 drawn from the Cu electrode 12 to a threshold value or more (filled in white) is performed on the original image. Since only a thin solder is placed on the Cu lead 26, it appears as if black and white are mixed in the original image. Therefore, it is possible to prevent erroneous determination in the narrow gap inspection by painting this portion white.

Figure 2008249611
Figure 2008249611

ただし、図36に示すように、下記の3方向について第2の画像処理を行って得た第1〜第3処理画像を合成し、この合成した画像を2値化して狭ギャップ検査を行う。まず、処理方向を短辺方向に平行な第1方向(図面右方向)として第2の画像処理を行って第1処理画像を得る。これにより、半田膜と異物の左側を際立たせることができる。次に、処理方向を長辺方向に平行な第2方向(図面下方向)として画像処理工程を行って第2処理画像を得る。これにより、異物の上側を際立たせることができる。次に、処理方向を第2方向とは反対の第3方向(図面上方向)として画像処理工程を行って第3処理画像を得る。これにより、異物の下側を際立たせることができる。   However, as shown in FIG. 36, the first to third processed images obtained by performing the second image processing in the following three directions are combined, and the combined image is binarized to perform a narrow gap inspection. First, the second processing is performed with the processing direction as a first direction parallel to the short side direction (the right direction in the drawing) to obtain a first processed image. Thereby, the left side of a solder film and a foreign material can be made to stand out. Next, an image processing step is performed with the processing direction as a second direction (downward in the drawing) parallel to the long side direction to obtain a second processed image. Thereby, the upper side of a foreign material can be made to stand out. Next, the third processing image is obtained by performing the image processing step with the processing direction as the third direction (upward direction in the drawing) opposite to the second direction. Thereby, the lower side of a foreign material can be made to stand out.

ここで、原画像を単純に2値化すると全体が膨張し、正確な狭ギャップ検査を行うことができない。これに対し、第1〜第3処理画像を合成することで異物を際立たせることができるため、正確な狭ギャップ検査を行うことができる。   Here, if the original image is simply binarized, the whole image expands, and an accurate narrow gap inspection cannot be performed. On the other hand, since a foreign material can be made conspicuous by combining the first to third processed images, an accurate narrow gap inspection can be performed.

次に、下記の方法により半田膜について原画像を撮影し、この原画像内で判定領域を決め、判定領域内において輝度が閾値以下の領域の面積が所定の値以上の場合に不良と判定する(ステップS16)。これにより黒色不良の有無を判定することができる。   Next, an original image of the solder film is taken by the following method, a determination area is determined in the original image, and it is determined to be defective when the area of the area whose luminance is below the threshold in the determination area is a predetermined value or more. (Step S16). Thereby, the presence or absence of a black defect can be determined.

図37は、黒色不良検査において半田膜を照明及び撮影するための光学系を示す図である。この光学系は、図12の光学系と同様に対物レンズ23,同軸照明手段24及びリング照明手段25を有するだけでなく、無影リング照明手段28を有する。無影リング照明手段28は、半田膜14の上に円心が位置するリング状の導光材を有する。発光ダイオードなどの光源から導光材に投入された光は、導光材内部で様々な方向に拡散される。即ち、無影リング照明手段28は、影が出にくい拡散均一照射型の無影照明である。この無影リング照明手段28を用いて、図38に示すように半田膜14を複数の方向から照明する。   FIG. 37 is a diagram showing an optical system for illuminating and photographing the solder film in the black defect inspection. This optical system has not only the objective lens 23, the coaxial illumination means 24, and the ring illumination means 25, but also a shadowless ring illumination means 28 as in the optical system of FIG. The shadowless ring illumination means 28 has a ring-shaped light guide material with a circular center located on the solder film 14. Light input to the light guide from a light source such as a light emitting diode is diffused in various directions inside the light guide. That is, the shadowless ring illumination means 28 is a diffusion uniform irradiation type shadowless illumination in which a shadow is not easily generated. The shadowless ring illumination means 28 is used to illuminate the solder film 14 from a plurality of directions as shown in FIG.

まず、同軸照明手段24,リング照明手段25及び無影リング照明手段28を用いて、半田膜14に上方及び斜めから光を当て反射光を測定して図39に示すような原画像を得る。このように半田膜14に対して、斜めからだけでなく上方からも光を当てることにより、半田膜14の全体を均一に光らせることができる。これにより、軽微な黒色不良についても検出することができる。特に、無影リング照明手段28を用いることにより、半田膜14に多方向から光を当てることができるため、黒色不良の検出が容易になる。また、直接照明を用いて半田膜14を複数の方向から照明すると、照明が対物レンズ23の中央に寄ってきて視野が狭くなる。これに対し、無影リング照明手段28を用いれば広い視野を確保することができる。   First, the coaxial illumination unit 24, the ring illumination unit 25, and the shadowless ring illumination unit 28 are used to apply light to the solder film 14 from above and obliquely to measure the reflected light, thereby obtaining an original image as shown in FIG. In this way, the entire solder film 14 can be uniformly illuminated by irradiating the solder film 14 not only obliquely but also from above. Thereby, even a minor black defect can be detected. In particular, by using the shadowless ring illumination means 28, it is possible to irradiate the solder film 14 with light from multiple directions, so that black defects can be easily detected. If the solder film 14 is illuminated from a plurality of directions using direct illumination, the illumination approaches the center of the objective lens 23 and the field of view is narrowed. On the other hand, if the shadowless ring illumination means 28 is used, a wide visual field can be secured.

ここで、図40に示すように、ワーク29の周辺領域からの反射光は無影リング照明手段28により遮られて対物レンズ23に入射されない。このため、図41に示すように、原画像の周辺領域では、中央領域に比べて輝度が低くなり、そのままでは黒色不良の判定を行うことができない。そこで、図42に示すように、原画像の周辺領域の輝度を上げた後に不良判定を行う。これにより、画像の中央領域だけでなく周辺領域でも黒色不良の判定を行うことができるため、判定時間を短縮することができる。   Here, as shown in FIG. 40, the reflected light from the peripheral region of the work 29 is blocked by the shadowless ring illumination means 28 and is not incident on the objective lens 23. For this reason, as shown in FIG. 41, the luminance in the peripheral area of the original image is lower than that in the central area, and it is not possible to determine the black defect as it is. Therefore, as shown in FIG. 42, defect determination is performed after increasing the brightness of the peripheral area of the original image. As a result, it is possible to determine the black defect not only in the central region of the image but also in the peripheral region, so that the determination time can be shortened.

次に、上記のように撮影した原画像において、図43に示すように、半田膜の外周部の近似曲線(点線)を最小二乗法により求める。そして、Cu電極の中心から長辺の1/2までの範囲と近似曲線とで囲まれる領域を黒色不良の判定領域とする。ただし、最小二乗法では外側の暗い部分を近似曲線の内側に含んでしまうため、近似曲線から所定の幅(例えば3μm)だけ内側の領域(実線)を判定領域とするのが好ましい。   Next, in the original image taken as described above, as shown in FIG. 43, an approximate curve (dotted line) of the outer periphery of the solder film is obtained by the method of least squares. A region surrounded by a range from the center of the Cu electrode to ½ of the long side and the approximate curve is determined as a black defect determination region. However, since the least square method includes an outer dark portion inside the approximate curve, it is preferable to set a region (solid line) on the inner side (solid line) by a predetermined width (for example, 3 μm) from the approximate curve as the determination region.

また、上記の黒色不良の判定工程において不良と判定した場合に、原画像のコントラストを強調して再び不良判定工程を行う。これにより、半田膜14の表面の荒れを黒色不良と誤判定するのを防ぐことができる。原画像のコントラストの強調は以下のように行う。   Further, when it is determined that the black defect is defective in the black defect determination process, the defect determination process is performed again while enhancing the contrast of the original image. Thereby, it is possible to prevent the surface roughness of the solder film 14 from being erroneously determined as a black defect. The contrast of the original image is enhanced as follows.

まず、図44は、撮影した原画像、その輝度の度数分布グラフ及び輝度の累積度数分布グラフである。この原画像に対して、図45に示すように階調イコライゼーションを行う。次に、図46に示すようにγ補正を行う。最後に、図47に示すようにコントラストを改善することで最終画像を得る。   First, FIG. 44 shows a photographed original image, a luminance frequency distribution graph thereof, and a luminance cumulative frequency distribution graph. As shown in FIG. 45, gradation equalization is performed on the original image. Next, γ correction is performed as shown in FIG. Finally, the final image is obtained by improving the contrast as shown in FIG.

本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る不良判定方法を示すフローチャートである。It is a flowchart which shows the defect determination method which concerns on embodiment of this invention. 半田膜を照明及び撮影するための光学系を示す図である。It is a figure which shows the optical system for illuminating and image | photographing a solder film. 半田膜を照明するための光学系を示す図である。It is a figure which shows the optical system for illuminating a solder film. リング照明手段により半田膜を照明する様子を示す断面図である。It is sectional drawing which shows a mode that a solder film is illuminated by a ring illumination means. 同軸照明手段により半田膜を照明する様子を示す断面図である。It is sectional drawing which shows a mode that a solder film is illuminated by a coaxial illumination means. DC不良を有する半田膜の原画像である。It is an original image of a solder film having a DC defect. 原画像の輝度を長辺方向に微分した微分データである。This is differential data obtained by differentiating the luminance of the original image in the long side direction. 微分データを短辺方向に積算した積算値を示す図である。It is a figure which shows the integrated value which integrated the differential data in the short side direction. DC不良を有する半田膜の原画像である。It is an original image of a solder film having a DC defect. DE不良を有する半田膜の原画像である。It is an original image of a solder film having a DE defect. 微分データを短辺方向に積算した積算値を示す図である。It is a figure which shows the integrated value which integrated the differential data in the short side direction. Cu電極の真中部分だけについて輝度を微分することを説明するための図である。It is a figure for demonstrating differentiating a brightness | luminance only about the center part of Cu electrode. 図19の原画像の輝度を短辺方向に積算した積算値を示す図である。It is a figure which shows the integrated value which integrated the brightness | luminance of the original image of FIG. 19 in the short side direction. 半田膜の外周部の近似曲線を描いた原画像である。It is the original image which drew the approximated curve of the outer peripheral part of a solder film. DE不良を有する半田膜のレーザ顕微鏡画像である。It is a laser microscope image of the solder film which has DE defect. DE不良を有する半田膜に斜めから光を当て反射光を測定して得た原画像である。It is the original image obtained by irradiating light to the solder film which has DE defect from diagonally, and measuring reflected light. 図25の原画像を2値化した画像である。It is the image which binarized the original image of FIG. DE不良の多値検査を説明するための図である。It is a figure for demonstrating the multi-value test | inspection of DE failure. ディウェットの検査を説明するための図である。It is a figure for demonstrating the inspection of a dewet. DE不良の2値面積検査を説明するための図である。It is a figure for demonstrating the binary area test | inspection of DE failure. レーザ変位計による高さ測定の結果を示す図である。It is a figure which shows the result of the height measurement by a laser displacement meter. レーザ高さ測定を行う位置を示す断面図である。It is sectional drawing which shows the position which performs a laser height measurement. レーザ高さ測定を行う位置を示す上面図である。It is a top view which shows the position which performs a laser height measurement. リード間のギャップを示す上面図である。It is a top view which shows the gap between leads. 第1の画像処理を説明するための図である。It is a figure for demonstrating 1st image processing. 第2の画像処理を説明するための図である。It is a figure for demonstrating 2nd image processing. 第1〜第3処理画像の合成を説明するための図である。It is a figure for demonstrating the synthesis | combination of a 1st-3rd process image. 黒色不良検査において半田膜を照明及び撮影するための光学系を示す図である。It is a figure which shows the optical system for illuminating and image | photographing a solder film in a black defect test | inspection. 無影リング照明手段により半田膜を照明する様子を示す断面図である。It is sectional drawing which shows a mode that a solder film is illuminated by a shadowless ring illumination means. 半田膜に上方及び斜めから光を当て反射光を測定して得た原画像である。It is the original image obtained by applying light to the solder film from above and obliquely and measuring the reflected light. 無影リング照明手段を用いた場合の反射光の経路を説明するための拡大断面図である。It is an expanded sectional view for demonstrating the path | route of the reflected light at the time of using a shadowless ring illumination means. 複数のCu配線上に形成された半田膜を撮影した原画像である。It is the original image which image | photographed the solder film formed on the some Cu wiring. 図41の原画像の周辺領域の輝度を上げた画像である。It is the image which raised the brightness | luminance of the peripheral area | region of the original image of FIG. 黒色不良の判定領域を決めた原画像である。This is an original image in which a black defect determination area is determined. 撮影した原画像、その輝度の度数分布グラフ及び輝度の累積度数分布グラフである。It is the image | photographed original image, the frequency distribution graph of the brightness | luminance, and the cumulative frequency distribution graph of a brightness | luminance. 階調イコライゼーションを行った画像、その輝度の度数分布グラフ及び輝度の累積度数分布グラフである。It is the image which performed the gradation equalization, the frequency distribution graph of the brightness | luminance, and the cumulative frequency distribution graph of the brightness | luminance. γ補正を行った画像、その輝度の度数分布グラフ及び輝度の累積度数分布グラフである。It is the image which performed (gamma) correction | amendment, the frequency distribution graph of the brightness | luminance, and the cumulative frequency distribution graph of the brightness | luminance. コントラストを改善した画像、その輝度の度数分布グラフ及び輝度の累積度数分布グラフである。It is the image which improved contrast, the frequency distribution graph of the brightness | luminance, and the cumulative frequency distribution graph of the brightness | luminance. DC不良を有する半田膜を撮影した画像である。It is the image which image | photographed the solder film which has DC defect. DE不良を有する半田膜を撮影した画像である。It is the image which image | photographed the solder film which has DE defect. 黒色不良が発生した半田膜を示すレーザ顕微鏡画像である。It is a laser microscope image which shows the solder film which black defect generate | occur | produced. 従来の方法により得た原画像である。It is the original image obtained by the conventional method.

符号の説明Explanation of symbols

11 配線基板
12 Cu電極(電極)
14 半田膜
24 同軸照明手段
25 リング照明手段
26 Cuリード(リード)
28 無影リング照明手段
11 Wiring board 12 Cu electrode (electrode)
14 Solder film 24 Coaxial illumination means 25 Ring illumination means 26 Cu lead (lead)
28 Shadowless ring illumination means

Claims (17)

長辺と短辺を有する電極上に半田膜を有する配線基板を準備する工程と、
前記半田膜に斜めから光を当て反射光を測定して原画像を得る工程と、
前記原画像の輝度を長辺方向に微分して微分データを得る工程と、
前記微分データを短辺方向に積算して積算値を求める工程と、
前記積算値の最大値と最小値の差が所定の値以上であり、前記積算値が最大となる位置と最小となる位置の幅が所定の幅以下である場合に不良と判定する第1検査工程とを備えることを特徴とする半導体装置の製造方法。
Preparing a wiring board having a solder film on an electrode having a long side and a short side;
Applying an oblique light to the solder film and measuring the reflected light to obtain an original image;
Differentiating the luminance of the original image in the long side direction to obtain differential data;
A step of integrating the differential data in the short side direction to obtain an integrated value;
A first inspection for determining a defect when a difference between the maximum value and the minimum value of the integrated values is equal to or greater than a predetermined value, and a width between a position where the integrated value is maximum and a minimum position is equal to or less than a predetermined width. A method of manufacturing a semiconductor device.
前記第1検査工程において不良と判定した場合に、前記原画像において前記電極上に輝度が閾値より低い領域が2個以上に分かれている場合は不良と判定し、1個以下の場合は良好と判断する第2検査工程を更に備えることを特徴とする請求項1に記載の半導体装置の製造方法。   When it is determined as defective in the first inspection process, it is determined as defective when the original image is divided into two or more regions whose luminance is lower than the threshold on the electrode, and is determined as good when the number is one or less. The method of manufacturing a semiconductor device according to claim 1, further comprising a second inspection step for determining. 長辺と短辺を有する電極上に半田膜を有する配線基板を準備する工程と、
前記半田膜に斜めから光を当て反射光を測定して原画像を得る工程と、
前記原画像の輝度を長辺方向に微分して微分データを得る工程と、
前記微分データの輝度を短辺方向に積算して積算値を求める工程と、
前記積算値の最大値が所定の値以上である場合に不良と判定する工程とを備えることを特徴とする半導体装置の製造方法。
Preparing a wiring board having a solder film on an electrode having a long side and a short side;
Applying an oblique light to the solder film and measuring the reflected light to obtain an original image;
Differentiating the luminance of the original image in the long side direction to obtain differential data;
Integrating the luminance of the differential data in the short side direction to obtain an integrated value;
And a step of determining a failure when the maximum value of the integrated values is equal to or greater than a predetermined value.
前記微分データを得る工程において、前記電極の真中部分だけについて輝度を微分することを特徴とする請求項1〜3の何れか1項に記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of obtaining the differential data, the luminance is differentiated only with respect to a middle portion of the electrode. 5. 電極上に半田膜を有する配線基板を準備する工程と、
前記半田膜に斜めから光を当て反射光を測定して原画像を得る工程と、
前記原画像において輝度が閾値以上の領域の面積が所定の値以下の場合に不良と判定する第1検査工程とを備えることを特徴とする半導体装置の製造方法。
Preparing a wiring board having a solder film on the electrode;
Applying an oblique light to the solder film and measuring the reflected light to obtain an original image;
A method for manufacturing a semiconductor device, comprising: a first inspection step for determining a defect when an area of a region having a luminance equal to or higher than a threshold in the original image is equal to or less than a predetermined value.
前記第1検査工程において不良と判定した前記半田膜についてレーザ変位計により高さを測定する第2検査工程を更に備えることを特徴とする請求項5に記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, further comprising a second inspection step of measuring a height of the solder film determined to be defective in the first inspection step with a laser displacement meter. 前記第2検査工程において、前記電極上の前記半田膜の高さと前記電極から引き出されたリードの高さとの差が所定の値の範囲内から外れる場合は不良と判定することを特徴とする請求項6に記載の半導体装置の製造方法。   In the second inspection step, if the difference between the height of the solder film on the electrode and the height of the lead drawn out from the electrode is out of a predetermined value range, it is determined as defective. Item 7. A method for manufacturing a semiconductor device according to Item 6. 電極上に半田膜を有する配線基板を準備する工程と、
前記半田膜に斜めから光を当て反射光を測定して原画像を得る工程と、
前記原画像について、前記電極から引き出されたリードに相当する部分の輝度を閾値以上に上げる処理を行う工程と、
処理後の画像において、輝度が閾値以上の領域同士の間隔が所定の長さ以下の場合に不良と判定する工程とを有することを特徴とする半導体装置の製造方法。
Preparing a wiring board having a solder film on the electrode;
Applying an oblique light to the solder film and measuring the reflected light to obtain an original image;
For the original image, performing a process of raising the luminance of the portion corresponding to the lead extracted from the electrode to a threshold value or more;
A method of manufacturing a semiconductor device, comprising: determining a defect when an interval between regions having a luminance equal to or higher than a threshold in a processed image is equal to or less than a predetermined length.
電極上に半田膜を有する配線基板を準備する工程と、
前記半田膜に斜めから光を当て反射光を測定して原画像を得る工程と、
前記原画像の各画素について、その画素から所定の処理方向に所定の個数分の画素の輝度を積算したものから、その画素から前記処理方向とは反対の方向に前記所定の個数分の画素の輝度を積算したものを差し引いた値をその画素の輝度とする処理を行う画像処理工程と、
処理後の画像において、輝度が閾値以上の領域同士の間隔が所定の長さ以下の場合に不良と判定する検査工程とを有することを特徴とする半導体装置の製造方法。
Preparing a wiring board having a solder film on the electrode;
Applying an oblique light to the solder film and measuring the reflected light to obtain an original image;
For each pixel of the original image, the luminance of the predetermined number of pixels in the predetermined processing direction from the pixel is integrated, and the predetermined number of pixels from the pixel in the direction opposite to the processing direction An image processing step for performing a process of setting a value obtained by subtracting the sum of luminance to the luminance of the pixel;
A method for manufacturing a semiconductor device, comprising: an inspection step of determining a defect when an interval between regions having luminance equal to or higher than a threshold value is equal to or less than a predetermined length in a processed image.
前記処理方向を短辺方向に平行な第1方向として前記画像処理工程を行って第1処理画像を得る工程と、
前記処理方向を長辺方向に平行な第2方向として前記画像処理工程を行って第2処理画像を得る工程と、
前記処理方向を前記第2方向とは反対の第3方向として前記画像処理工程を行って第3処理画像を得る工程と、
前記第1処理画像、前記第2処理画像及び前記第3処理画像を合成し、この合成した画像について前記検査工程を行うことを特徴とする請求項9に記載の半導体装置の製造方法。
Performing the image processing step with the processing direction as a first direction parallel to the short side direction to obtain a first processed image;
Performing the image processing step with the processing direction as a second direction parallel to the long side direction to obtain a second processed image;
Performing the image processing step with the processing direction as a third direction opposite to the second direction to obtain a third processed image;
The method for manufacturing a semiconductor device according to claim 9, wherein the first processed image, the second processed image, and the third processed image are combined, and the inspection process is performed on the combined image.
電極上に半田膜を有する配線基板を準備する工程と、
前記半田膜に上方及び斜めから光を当て反射光を測定して原画像を得る工程と、
前記原画像内で判定領域を決め、前記判定領域内において輝度が閾値以下の領域の面積が所定の値以上の場合に不良と判定する不良判定工程とを備えることを特徴とする半導体装置の製造方法。
Preparing a wiring board having a solder film on the electrode;
Applying the light from above and obliquely to the solder film to measure reflected light to obtain an original image;
A semiconductor device manufacturing method, comprising: determining a determination region in the original image; and determining a failure when an area of a region having a luminance of a threshold value or less in the determination region is equal to or greater than a predetermined value. Method.
前記原画像を得る工程において、前記反射光を入力する光入力手段と、前記光入力手段と同軸で前記半田膜を照明する同軸照明手段と、前記半田膜の上に円心が位置するリング状のリング照明手段とを用いることを特徴とする請求項11に記載の半導体装置の製造方法。   In the step of obtaining the original image, a light input means for inputting the reflected light, a coaxial illumination means for illuminating the solder film coaxially with the light input means, and a ring shape in which a circular center is located on the solder film 12. The method of manufacturing a semiconductor device according to claim 11, wherein the ring illumination means is used. 前記原画像を得る工程において、光源からの光を拡散して前記半田膜を複数の方向から照明する無影リング照明手段を更に用いることを特徴とする請求項12に記載の半導体装置の製造方法。   13. The method of manufacturing a semiconductor device according to claim 12, wherein in the step of obtaining the original image, a shadowless ring illuminating unit that diffuses light from a light source and illuminates the solder film from a plurality of directions is further used. . 前記原画像の周辺領域の輝度を上げた後に前記不良判定工程を行うことを特徴とする請求項13に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 13, wherein the defect determination step is performed after increasing the luminance of a peripheral area of the original image. 前記原画像において前記半田膜の外周部の近似曲線を最小二乗法により求める工程を更に有し、
前記近似曲線で囲まれる領域を前記判定領域とすることを特徴とする請求項11〜14の何れか1項に記載の半導体装置の製造方法。
A step of obtaining an approximate curve of the outer periphery of the solder film in the original image by a least square method;
The method for manufacturing a semiconductor device according to claim 11, wherein a region surrounded by the approximate curve is set as the determination region.
前記近似曲線から所定の幅だけ内側の領域を前記判定領域とすることを特徴とする請求項15に記載の半導体装置の製造方法。   16. The method of manufacturing a semiconductor device according to claim 15, wherein an area inside the predetermined curve by a predetermined width is set as the determination area. 前記不良判定工程において不良と判定した場合に、前記原画像のコントラストを強調して再び前記不良判定工程を行うことを特徴とする請求項11〜16の何れか1項に記載の半導体装置の製造方法。   17. The semiconductor device manufacturing according to claim 11, wherein when the defect is determined to be defective in the defect determination step, the defect determination step is performed again with emphasis on the contrast of the original image. Method.
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